Academia.edu no longer supports Internet Explorer.
To browse Academia.edu and the wider internet faster and more securely, please take a few seconds to upgrade your browser.
2007, 2007 International Conference on Field-Programmable Technology
As one of the most promising Spintronics applications, MRAM combines the advantages of high writing and reading speed, limitless endurance and non-volatility. The integration of MRAM in FPGA allows the logic circuit to rapidly configure the algorithm, the routing and logic functions, easily realize the dynamical reconfiguration and multicontext configuration. However, the conventional MRAM technology based on Field Induced Magnetic Switching (FIMS) writing approach consumes very high power and large circuit surface, and produces high disturbance between memory cells. These drawbacks prevent FIMS-MRAM's further development in memory and logic circuit. Thermally Assisted Switching (TAS) based MRAM is then evaluated to address these issues and some design techniques for FPGA logic circuits based on TAS-MRAM technology are presented. By using STMicroelectronics CMOS 90nm technology, some chip characteristic results have been calculated to demonstrate the expected performance of TAS-MRAM based FPGA logic circuits.
ACM Transactions on Reconfigurable Technology and Systems, 2009
As one of the most promising Spintronics applications, MRAM combines the advantages of high writing and reading speed, limitless endurance, and nonvolatility. The integration of MRAM in FPGAs allows the logic circuit to rapidly configure the algorithm, the routing and logic functions, and easily realize the Runtime Reconfiguration (RTR) and multicontext configuration. However, the conventional MRAM technology based on the Field Induced Magnetic Switching (FIMS) writing approach consumes very high power, large circuit surfaces, and produces high disturbance between memory cells. These drawbacks prevent FIMS-MRAM’s further development in memory and logic circuit. Thermally Assisted Switching (TAS)-based MRAM is then evaluated to address these issues. In this article, some design techniques, novel computing architecture, and logic components for FPGA logic circuits based on TAS-MRAM technology are presented. By using STMicroelectronics CMOS 90nm technology and a complete TAS-MTJ spice ...
2008 International Conference on Field Programmable Logic and Applications, 2008
This paper describes the integration of a thermally assisted switching magnetic random access memory (TAS-MRAM) in FPGA design. The non-volatility of the latter is achieved through the use of magnetic tunneling junctions (MTJ) in the MRAM cell. A thermally assisted switching scheme is used to write data in the MTJ device, which helps to reduce power consumption during write operation in comparison to the writing scheme in classical MTJ device. Plus, the non-volatility of such a design should reduce both power consumption and configuration time required at each power up of the circuit in comparison to classical SRAM based FPGAs. A real time reconfigurable (RTR) micro-FPGA using TAS-MRAM allows dynamic reconfiguration mechanisms, while featuring simple design architecture.
2006 IEEE International Conference on IC Design and Technology, 2006
In this paper, we propose a new structure of FPGA based on MRAM technology; we name it MFPGA (Magnetic FPGA). FPGA i based on SRAM technology has been developed in the last years, because of its high speed and near limitless number of reprogramming, however SRAM is volatile thereby the configuration information and the intermediate data will be lost when power is turned off. By using MTJs (Magnetic Tunnel Junction) as the storage elements of FPGA, 1 the position of MTJs we can realize the non-volatility of FPGA, and then we will not need the external memory. In our simulation, the start-up time of circuit
ACM Transactions on Embedded Computing Systems, 2009
As the minimum fabrication technology of CMOS transistor shrink down to 90nm or below, the high standby power has become one of the major critical issues for the SRAM-based FPGA circuit due to the increasing leakage currents in the configuration memory. The integration of MRAM in FPGA instead of SRAM is one of the most promising solutions to overcome this issue, because its nonvolatility and high write/read speed allow to power down completely the logic blocks in “idle” states in the FPGA circuit. MRAM-based FPGA promises as well as some advanced reconfiguration methods such as runtime reconfiguration and multicontext configuration. However, the conventional MRAM technology based on field-induced magnetic switching (FIMS) writing approach consumes very high power, large circuit surface and produces high disturbance between memory cells. These drawbacks prevent FIMS-MRAM's further development in memory and logic circuit. Spin transfer torque (STT)-based MRAM is then evaluated to ...
International Journal of Reconfigurable Computing, 2008
This paper describes the integration of field-induced magnetic switching (FIMS) and thermally assisted switching (TAS) magnetic random access memories in FPGA design. The nonvolatility of the latter is achieved through the use of magnetic tunneling junctions (MTJs) in the MRAM cell. A thermally assisted switching scheme helps to reduce power consumption during write operation in comparison to the writing scheme in the FIMS-MTJ device. Moreover, the nonvolatility of such a design based on either an FIMS or a TAS writing scheme should reduce both power consumption and configuration time required at each power up of the circuit in comparison to classical SRAM-based FPGAs. A real-time reconfigurable (RTR) micro-FPGA using FIMS-MRAM or TAS-MRAM allows dynamic reconfiguration mechanisms, while featuring simple design architecture.
IEEE Journal of the Electron Devices Society
In this paper a new experimental technique for measuring the switching dynamics and extracting the energy consumption of Spin Transfer Torque MRAM (STT-MRAM) device is presented. This technique is performed by a real-time current reading while a pulsed bias is applied. The switching from a high resistive state, anti-parallel (AP) alignment, to a low resistive state, parallel (P) alignment, is investigated as well as the impact of the cell diameter on the switching parameters. We demonstrate that preswitching and switching times and energies have a log-linear relationship with the applied voltage. Increasing the applied voltage leads to a higher spin torque on the free layer in a shorter time. This decreases the time needed to change the magnetization orientation of this layer, thus the time required before the switching occurs. We have also shown that for a given applied voltage, the smaller the cell the longer the time before switching. For low applied voltages, the preswitching time increases exponentially dominating the whole reversal time. The longer switching times can be explained by a lower Joule heating not sufficient to induce the thermally activated reversal process. This phenomenon is accentuated for smaller cells, where the heating is more significant and the time before switching is shorter than for larger cells. INDEX TERMS Magnetic switching, MRAM devices, perpendicular magnetic tunnel junction, spin transfer torque.
2008 9th International Conference on Solid-State and Integrated-Circuit Technology, 2008
In this paper~we present a non-volatile register based on hybrid Spintronics/CMOS technology, which can store securely and non-vocatively all the intermediate data in the logic circuits as FPGA and ASIC. The non-volatility of this register allows to power down the circuits keeping the data thereby reduce significantly the standby power and accelerate the chip re (boot) latency. Based on STMicroelectronics 90nm design kit and a complete MTJ Spice model for MRAM development, the delay propagation of this register is lower than 500ps. We propose also the solutions to overcome the high sensitivity issue for this non-volatile register.
Current Science, 2020
In this study, the schematics for Magnetic Tunnel Junction-Magnetoresistive Random Access Memory (MTJ-MRAM) are designed and simulations are carried out in 45 and 90 nm Complementary Metal-Oxide Semiconductor (CMOS) Very Large Scale Integration (VLSI) technology using analog design environment. Other memory circuits like volatile Static Random Access Memory (SRAM) and non-volatile flash memory are designed and behavioural waveforms verified. The output behavioural characteristics of MTJ-MRAM are compared with that of SRAM and flash memory. The attributes like power and delay are calculated and compared with SRAM and flash memory circuits. The study was carried out in order to integrate the non-volatile memory with field-programmable gate array (FPGA) architecture and design a nonvolatile memory-based FPGA. MTJ-MRAM shows better performance than volatile SRAM and nonvolatile flash memory in terms of power and delay parameters.
IEEE Transactions on Magnetics, 2000
Key design parameters of 64 Mb STT-MRAM at 90-nm technology node are discussed. A design point was developed with adequate TMR for fast read operation, enough energy barrier for data retention and against read disturbs, a write voltage satisfying the long term reliability against dielectric breakdown and a write bit error rate below 10 09 . A direct experimental method was developed to determine the data retention lifetime that avoids the discrepancy in the energy barrier values obtained with spin current-and field-driven switching measurements. Other parameters detrimental to write margins such as backhopping and the existence of a low breakdown population are discussed. At low bit-error regime, new phenomenon emerges, suggestive of a bifurcation of switching modes. The dependence of the bifurcated switching threshold on write pulse width, operating temperature, junction dimensions and external field were studied. These show bifurcated switching to be strongly influenced by thermal fluctuation related to the spatially inhomogeneous free layer magnetization. An external field along easy axis direction assisting switching was shown to be effective for significantly reducing the percentage of MTJs showing bifurcated switching.
IEEE Transactions on Electron Devices, 2018
We analyze the augmentation of spin-transfer torque (STT) MRAM with electrically driven selective phase transition of a threshold switch (TS) to enhance the read operation. This paper provides a comprehensive discussion on necessary design considerations for TS augmented (TSA) MRAMs. We deduce constraints for read and write biasing that yields improved read operation of TSA MRAMs. We explain the dependence of read/write performance metrics on read/write biases and the properties (resistance and critical currents for transitions) of the TS. With proper device-circuit optimization, TSA MRAM shows up to 70% larger sense margin, ∼27% higher data stability with ∼40% less power for read operation compared to STT MRAM (in nominal condition). We evaluate the impact of variation on TSA MRAM through Monte Carlo simulations. We report that even with variation induced spread in the distribution of bit-line voltages, TSA MRAM provides ∼1.7× larger voltage differential between parallel and antiparallel states. For the write operation, the TSA MRAM consumes ∼10% less average power and demands only ∼5% more write time extension than the STT MRAM to achieve the same level of variation tolerance. Index Terms-Monte Carlo analysis, magnetic tunnel junction (MTJ), phase transition, sense margin (SM), spintransfer torque (STT) MRAM, threshold switch (TS), tunneling magneto resistance (TMR), variation. I. INTRODUCTION S PIN-TRANSFER torque (STT) MRAM has drawn immense attention as a nonvolatile memory device due to several promising features including high retention time, thermal stability, impressive reliability, and CMOS compatibility [1], [2]. STT MRAM comprises a magnetic tunnel junction (MTJ) and an access transistor [Fig. 1(a)]. The MTJ stores data in the form of relative magnetization between its two magnetic layers called a pinned layer (PL) and the free layer (FL). These two layers are separated by an oxide (usually MgO) layer which acts as a tunnel barrier. If the FL possesses a magnetization parallel to the PL, the MTJ Manuscript
International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006., 2006
In this paper, we propose a non-volatile flip-flop, which presents simultaneously low power dissipation and high speed. This flip-flop is based on MRAM (Magnetic RAM) technology on standard CMOS. In this non-volatile flip-flop design, we use Magnetic Tunnel Junctions (MTJ) as storage element. Contrary to the complex sense amplifier circuit in standard MRAM circuits, a simple one based on SRAM cell is used to couple with two MTJs per bit in Magnetic logic circuit. The flip-flop works exactly as a classical flip-flop but the information is stored simultaneously in the two MTJs, which makes this flip-flop non-volatile. As the writing frequency has a strong impact on the power consumption, the MTJ writing frequency is designed to be defined by the users depending on different usage. During the startup or reset phase, the flip-flop master stage is used as the MTJ sense amplifier and the flipflop is initialized to the previously stored state in about 200 ps. This figure has been demonstrated by electrical simulation on a 90 nm CMOS technology and with a complete and precise MTJ model.
2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, 2006
In this paper, we propose a new non-volatile FPGA circuit based on Spin-RAM technology (Spin Transfer Torque Magnetisation Switching RAM), new generation of MRAM (Magnetic RAM). This Spin-RAM based FPGA circuit could process securely the information in low power dissipation and high speed; meanwhile all the data processed are stored permanently in the distributed Spin-RAM memory. In this non-volatile FPGA design, MTJs (Magnetic Tunnel Junction) are used as storage elements. Contrary to conventional MRAM circuits we don't use a complex sense amplifier, but a simple SRAM based sense amplifier couples two MTJs per bit. The non-volatility of Spin-RAM allows the dynamical configuration of FPGA circuits and the start-up time of circuit can be decreased up to some hundred pico seconds. As conventional MRAM, the MTJs of Spin-RAM will be on the semiconductor surface; therefore the circuit die area will not be enlarged comparing with the conventional FPGA.
2012
As the technolody node shrinks down to 90nm and below, high standby power becomes one of the major critical issues for CMOS highspeed computing circuits (e.g. logic and cache memory) due to the high leakage currents. A number of non-volatile storage technologies, such as FRAM, MRAM, PCRAM and RRAM, are under investigation to bring the non-volatility into the logic circuits and then eliminate completely the standby power issue. Thanks to its infinite endurance, high switching/sensing speed and easy integration on top of CMOS process, MRAM is considered as the most promising one. Numerous logic circuits based on MRAM technology have been proposed and prototyped in the last years. In this paper, we present an overview and current status of these logic circuits and discuss their potential applications in the future from both physical and architectural points of view.
IEEE Transactions on Magnetics, 2000
A new class of spin-transfer torque magnetic random access memory (STT-MRAM) is discussed, in which writing is achieved using thermally initiated magnonic current pulses as an alternative to conventional electric current pulses. The magnonic pulses are used to destabilize the magnetic free layer from its initial direction, and are followed immediately by a bipolar electric current exerting conventional spin-transfer torque on the free layer. The combination of thermal and electric currents greatly reduces switching errors, and simultaneously reduces the electric switching current density by more than an order of magnitude as compared to conventional STT-MRAM. The energy efficiency of several possible electro-thermal circuit designs have been analyzed numerically. As compared to STT-MRAM with perpendicular magnetic anisotropy, magnonic STT-MRAM reduces the overall switching energy by almost 80%. Furthermore, the lower electric current density allows the use of thicker tunnel barriers, which should result in higher tunneling magnetoresistance and improved tunnel barrier reliability.
Journal of Physics: Condensed Matter, 2007
Magnetic random access memories (MRAM) are a new non-volatile memory technology trying establish itself as a mainstream technology. MRAM cell operation using a thermally assisted writing scheme (TA-MRAM) is described in this review as well as its main design challenges. This approach is compared to conventional MRAM highlighting the improvements in write selectivity, power consumption and thermal stability. The TA-MRAM writing was tested and validated in the dynamic regime down to 500ps write pulses. The heating process was investigated for the influence of the voltage pulse width, junction area and lead volume looking at the required write power density. The possibilities to control and reduce the write power density are described. The most promising solution to optimize the heating process and reduce the power consumption is to insert two thermal barrier layers at both ends of the MTJ layer stack, between the junction and the electrical leads, using low thermal conductivity materials. This minimizes the heating losses and improves the heating efficiency.
2011
As the fabrication technology node shrinks down to 90nm or below, high standby power becomes one of the major critical issues for CMOS logic circuits due to the high leakage currents. A number of non-volatile storage technologies such as FRAM, MRAM, PCRAM and RRAM and so on, are under investigation to bring the non-volatility into the logic circuits and then eliminate completely the standby power issue. Thanks to its infinite endurance, high switching/sensing speed and easy 3D integration after CMOS process, MRAM is considered as the most promising one. Numerous logic circuits based on MRAM technology have been proposed and prototyped in the last years. In this paper, we present an overview and current status of these logic circuits and their potential applications in the future.
The main objective of this paper is to give an overview of different hybrid MRAM / CMOS cells to use in the context of reconfigurable computing. The way to convert magnetic information into an electrical one is not unique and we propose to compare different kind of hybrid cells. These hybrid cells can be used to define structures as Look-up configuration memory point, Flip-flop and other basic elements needed to define programmable logic. Even if these cells were designed for the TAS (Thermally Assisted Switching) MRAM technology, it is possible to adapt them to more advanced technologies such as STT (Spin Transfer Torque).
As the fabrication technology node shrinks down to 90nm or below, high standby power becomes one of the major critical issues for CMOS high-speed computing circuits (e.g. logic and cache memory) due to the high leakage currents. A number of non-volatile storage technologies such as FeRAM, MRAM, PCRAM and RRAM and so on, are under investigation to bring the non-volatility into the logic circuits and then eliminate completely the standby power issue. Thanks to its infinite endurance, high switching/sensing speed and easy 3D integration after CMOS process, MRAM is considered as the most promising one. Numerous logic circuits based on MRAM technology have been proposed and prototyped in the last years. In this paper, we present an overview and current status of these logic circuits and discuss their potential applications in the future from both the physics and architecture points of view.
Journal of Applied Physics, 2007
In this paper we have studied the dynamic switching in magnetic random access memory ͑MRAM͒ and its dependence on thermal effects due to a finite temperature. The model is based on the Landau-Lifshitz-Gilbert equation and the stochastic Landau-Lifshitz-Gilbert equation which are numerically integrated. The magnetic layers are assumed to be ellipsoid shaped with each magnetic layer single domain. In addition, we have taken into account the uniaxial intrinsic anisotropy. Simulations were performed for both balanced and nonbalanced synthetic antiferromagnetic elements. The switching properties are discussed as a function of applied field pulses' length and shape. In this paper we present how the thermal fluctuations affect the switching behavior, the reliability, and the writing speed of MRAM devices.