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2022, arXiv (Cornell University)
Existing graph theoretic approaches are mainly restricted to floor-plans with rectangular boundary. In this paper, we introduce floor-plans with L-shaped boundary (boundary with only one concave corner). To ensure the L-shaped boundary, we introduce the concept of non-triviality of a floor-plan. A floor-plan with a rectilinear boundary with at least one concave corner is non-trivial if the number of concave corners can not be reduced, without affecting the modules adjacencies within it. Further, we present necessary and sufficient conditions for the existence of a non-trivial L-shaped floor-plan corresponding to a properly triangulated planar graph (PTPG) G. Also, we develop an O(n 2 ) algorithm for its construction, if it exists.
ArXiv, 2020
Let G = (V, E) be a planar triangulated graph (PTG) having every face triangular. A rectilinear dual or an orthogonal floor plan (OFP) of G is obtained by partitioning a rectangle into \mid V \mid rectilinear regions (modules) where two modules are adjacent if and only if there is an edge between the corresponding vertices in G. In this paper, a linear-time algorithm is presented for constructing an OFP for a given G such that the obtained OFP has B_{min} bends, where a bend in a concave corner in an OFP. Further, it has been proved that at least B_{min} bends are required to construct an OFP for G, where \rho - 2 \leq B_{min} \leq \rho + 1 and \rho is the sum of the number of leaves of the containment tree of G and the number of K_4 (4-vertex complete graph) in G.
IEEE Transactions on Circuits and Systems, 1988
The topics discussed in this paper are minimization of the area occupied by a layout and related results concerning networks flow and rectilinear representation of planar graphs, based on a graph model of floorplans and layouts. We do not restrict OUT analysis to sliced floorplans but allow arbitrary floorplans. Given an arbitrary floorplan and the areas of the embedded building blocks, we prove the existence and uniqueness of a zero wasted area layout, and characterize it by a necessary and sufficient condition. On the basis of this condition we develop a scheme to generate zero wasted area layouts. We prove that given a family of dual network pairs for which the product of dual arc lengths are invariant, the minimal product of their longest paths is not smaller than the maximal product of their shortest paths. We also show that the maximal product of the flows in such a family of dual network pairs is given by the total sum of the arc length product of each individual pair of dual arcs. Finally, based on the zero wasted area layout, we present an efficient procedure to derive a rectilinear representation for any planar graph.
Artificial Intelligence for Engineering Design, Analysis and Manufacturing, 2018
An important task in the initial stages of most architectural design processes is the design of planar floor plans, that are composed of non-overlapping rooms divided from each other by walls while satisfying given topological and dimensional constraints. The work described in this paper is part of a larger research aimed at developing the mathematical theory for examining the feasibility of given topological constraints and providing a generic floor plan solution for all possible design briefs.In this paper, we mathematically describe universal (or generic) rectangular floor plans with n rooms, that is, the floor plans that topologically contain all possible rectangular floor plans with n rooms. Then, we present a graph-theoretical approach for enumerating generic rectangular floor plans upto nine rooms. At the end, we demonstrate the transformation of generic floor plans into a floor plan corresponding to a given graph.
CAADRIA proceedings
For most of the architectural design problems, there are underlying mathematical sub-problems, they may require to consider for generating architectural layouts. One of these sub-problems is to satisfy adjacency constraints for obtaining an initial layout. But in the literature, there does not exist a mathematical procedure that can address any given adjacency requirements, i.e., there does not exist a tool for generating a floor plan corresponding to any given adjacency (planar) graph (there exist algorithms for constructing floor plans for planar triangulated graphs only). In this paper, we are going to present an algorithm that would generate a floor plan corresponding to any given planar graph. The larger aim of this research is to develop a user-friendly tool that can generate a variety of initial layouts corresponding to a given graph, which can be further modified by the architects/designers.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1998
Existing algorithms for floorplan topology generation by rectangular dualization usually do not consider sizing issues. In this paper, given a rectangularly dualizable adjacency graph and a set of aspect ratios of the modules, a topology which is likely to yield an optimally sized floorplan, is produced first in a top-down fashion by an AI-based search technique with novel heuristic estimates based on size parameters. It is shown that for any rectangular graph, there exists a feasible topology using only either straight or Z-cutlines recursively within a bounding rectangle. The significance of this result is four-fold: 1) considerable acceleration of the heuristic search, 2) topology generation with minimal number of nonslice cores, 3) guaranteed safe routing order without addition of pseudo modules, and 4) design of an efficient bottom-up heuristic for optimal sizing. Experimental results show that this integrated method elegantly solves floorplan optimization problem for general including inherently nonslicible adjacency graphs.
Interdisciplinary Information Sciences, 2002
A plane drawing of a graph is called a floorplan if every face (including the outer face) is a rectangle. A based floorplan is a floorplan with a designated base line segment on the outer face. In this paper we give a simple algorithm to generate all based floorplans with at most n faces. The algorithm uses OðnÞ space and generates such floorplans in Oð1Þ time per floorplan without duplications. The algorithm does not output entire floorplans but the difference from the previous floorplan. By modifying the algorithm we can generate without duplications all based floorplans having exactly n faces in Oð1Þ time per floorplan, and all (non-based) floorplans having exactly n faces in OðnÞ time per floorplan. Also, given three integers n, k 1 and k 2 , we can generate all based floorplans with exactly n faces containing at least k 1 and at most k 2 inner rooms in Oð1Þ time per floorplan, where an inner room means a face which does not contain a line segment of the contour of the outer face.
2009 International Conference on Microelectronics - ICM, 2009
A new and efficient heuristic methodology, called Full-and-Elimination (FAE), is proposed to solve the floorplan area minimization problem. This approach is inspired by the game, Tetris . The modules are selected one at a time and placed to the partial floorplan, while attempting to grow on upper, in a row-by-row manner, until all the modules are arranged to the floorplan. In each row, modules are tried to be placed without deadspace. If any row is filled up, this row is viewed as "full" and thus it is "eliminated". The modules are sorted and constructively moved into the partial floorplan. A contour that encloses the top of the packed modules in the floorplan is constructed to help for arrangement of the modules. Experimental results on MCNC and GSRC benchmarks demonstrate that we obtain significant improvements on the area minimization and computational efforts. Particularly, our methodology provides greater improvement over other floorplanners as the number of modules increases, which is a feature of scalability.
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2004
In this paper, we extend the concept of the P-admissible floorplan representation to that of the P -admissible one. A P -admissible representation can model the most general floorplans. Each of the currently existing P -admissible representations, sequence pair (SP), bounded-slicing grid, and transitive closure graph (TCG), has its strengths as well as weaknesses. We show the equivalence of the two most promising P -admissible representations, TCG and SP, and integrate TCG with a packing sequence (part of SP) into a representation, called TCG-S. TCG-S combines the advantages of SP and TCG and at the same time eliminates their disadvantages. With the property of SP, a fast packing scheme is possible. Inherited nice properties from TCG, the geometric relations among modules are transparent to TCG-S (implying faster convergence to a desired solution), placement with position constraints becomes much easier, and incremental update for cost evaluation can be realized. These nice properties make TCG-S a superior representation which exhibits an elegant solution structure to facilitate the search for a desired floorplan/placement. Extensive experiments show that TCG-S results in the best area utilization, wirelength optimization, convergence speed, and stability among existing works and is very flexible in handling placement with special constraints. and 4) the best evaluated packing in the space corresponds to an optimal placement. We extend in this paper the concept of the P-admissible representation to that of the P 3 -admissible one by adding the fifth condition: 5) both horizontal and vertical [and thus two dimensional (2-D)] geometrical information between modules are defined in the representation. With this condition, any placement can be modeled. Therefore, a P 3 -admissible representation can represent the most general floorplans and contains a complete structure for searching for an optimal floorplan/placement solution. It is thus desirable to develop an effective and flexible P 3 -admissible representation.
2002
This paper presents a novel layout model and floorplanning tool particularly suitable for taking into account user defined layout constraints on specific sets of modules and specific locations. The user defined layout constraints can be the setting of any common topological property associated with a group of specific modules such as the neighboring property for example. Or the use of any topological regularities in a design such as regular bus structure or the use of the structural property such as the bit-sliceable or non bitsliceable feature of a module set, or their similar shape. The exploitation of these structural information helps in producing more compact layout especially for datapath oriented architectures. Moreover, in addition to the area and total wiring length, the critical path delay is systematically minimized through a global cost function. The potential candidates for the critical path computation can be specifically defined by the user. The core of the optimization process is based on Shuhted Annealing (S.A.).
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1995
In this paper we study the area minimization problem in floorplanning (also known as the floorplan sizing problem). For a given floorplan, the problem is to select a layout alternative for each subcircuit on a chip so as to minimize the chip area. Two area minimization methods for general floorplans are proposed. Both methods can be viewed as generalizations of the classical algorithm for slicing floorplans of Otten and Stockmeyer in the sense that they reduce naturally to their algorithm for slicing floorplans. Compared with the branch-and-bound algorithm of Wimer et al., which does not have a nontrivial performance bound, our methods are provably better than an exhaustive method for all the examples we examined.
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD), 1995
In this paper, it is shown that for any rectangularly dualizable graph, a feasible topology can be obtained by using only either straight or Z-cutlines recursively within a bounding rectangle. Given an adjacency graph, a potential topology, which may be nonslicible and is likely to yield an optimally sized oorplan, is produced rst in a top-down fashion using heuristic search in AND-OR graphs. The advantage of this technique is four-fold: (i) accelerates topdown search phase, (ii) generates a oorplan with minimal number of nonslice c ores, (iii) ensures safe routing order without addition of pseudo-modules, and (iv) solves the bottom-up algorithm eciently for optimal sizing of general oorplans in the second phase.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2005
In this paper, we introduce the concept of the P*-admissible representation and propose a P*-admissible, transitive closure graph-based representation for general floorplans, called TCG, and show its superior properties. TCG combines the advantages of popular representations such as sequence pair, BSG, and B*-tree. Like sequence pair and BSG, but unlike O-tree, B*-tree, and CBL, TCG is P*-admissible. Like B*-tree, but unlike sequence pair, BSG, O-tree, and CBL, TCG does not need to construct additional constraint graphs for the cost evaluation during packing, implying faster runtime. Further, TCG supports incremental update during operations and keeps the information of boundary modules as well as the shapes and the relative positions of modules in the representation. More importantly, the geometric relation among modules is transparent not only to the TCG representation but also to its operations, facilitating the convergence to a desired solution. All these properties make TCG an effective and flexible representation for handling the general floorplan/placement design problems with various constraints. Experimental results show the promise of TCG.
The main issue we are after here is space layout planning, space layout planning which examine the capability to better utilization of architecture space, this paper will investigate the potentials of evolutionary computation in solving the combinatorial problem of space layout planning; it will focus on the topological level of problems, topological allocation concern with the relationships between two spaces, i.e. the adjacency and proximity between two spaces.
Proceedings of the 28th Conference on Computer Aided Architectural Design Research in Asia (CAADRIA) [Volume 2]
The principle of symmetry has beneficial applications in architecture. Symmetry mainly creates order and equilibrium in complex designs. This study presents a graph theoretic approach for the automatic generation of rectangular floorplans with block symmetry. Existing graph theoretical approaches focus on the floorplan's outer boundary design, different room shapes, and spatial arrangements. This paper introduces block symmetry as a new concept in floorplan generation. Based on this concept, an algorithm is proposed for generating a rectangular floorplan with rectangular blocks for a given adjacency graph if one exists. Further, suppose two blocks are required to be symmetric, i.e., of equal size. In that case, an optimisation framework is used to equate the widths and heights of the blocks, resulting in the generation of a rectangular floorplan with block symmetry. A GUI is provided for users to perform the automatic generation of floorplans.
ArXiv, 2020
In this paper, we present GPLAN, software aimed at constructing dimensioned floorplan layouts based on graph-theoretical and optimization techniques. GPLAN takes user requirements as input in the following two forms: i. Adjacency graph: It allows user to draw an adjacency graph on a GUI(graphical user interface) corresponding to which GPLAN produces a set of dimensioned floorplans with a rectangular boundary, where each floorplan is topologically distinct from others. ii. Dimensionless layout: Here, user can draw any layout with rectangular or non-rectangular boundary on a GUI and GPLAN transforms it into a dimensioned floorplan while preserving adjacencies, positions, shapes of the rooms. The above approaches represent different ways of inserting adjacencies and GPLAN generate dimensioned floorplans corresponding to the given adjacencies. The larger aim is to provide alternative platforms to user for producing dimensioned floorplans for all given (architectural) constraints, which ...
Journal of Civil Engineering and Management, 2003
Knowledge-based tools assisting the designer in engineering represent further improvement of expert systems. The present paper shows how such software can be developed in the particular domain of floor layout design for buildings. The recently developed paradigm of hierarchical graphs is taken as the knowledge representation scheme. The user of the system is encouraged to undertake the search for rational solution at two levels. First, an analysis of functionality requirements for the designed object is performed. This results in a graph capturing main functions and relations between them. Further, this graph is mapped onto another graph depicting the floor layout in terms of areas and rooms. Both graphs produced by the user are checked against the constraints resulting from the requirements of the relevant code of practice. The final result is converted into the format accepted by a commercial CAD-tool in order to proceed with the detailed design.
Algorithmica, 2012
In this paper, we consider the problem of representing graphs by polygons whose sides touch. We show that at least six sides per polygon are necessary by constructing a class of planar graphs that cannot be represented by pentagons. We also show that the lower bound of six sides is matched by an upper bound of six sides with a linear time algorithm for representing any planar graph by touching hexagons. Moreover, our algorithm produces convex polygons with edges with slopes 0, 1, -1. Fig. 1. Given a drawing of a planar graph(a), we apportion the edges to the endpoints by cutting each edge in half (b), and then apportion the faces to form polygons (c).
2005
and Technology. His vast experience and in-depth knowledge in graph theory has helped significantly to achieve a smooth completion of this thesis work. He gives me valuable guide lines through out the thesis work.
ACM Transactions on Design Automation of Electronic Systems, 2003
Floorplan representation is a fundamental issue in designing a floorplanning algorithm. In this paper, we first present a twin binary trees structure for mosaic floorplans. It is a nonredundant representation. We then derive the exact number of configurations for mosaic floorplans and slicing floorplans. Finally, the relationships between various state-of-the-art floorplan representations are discussed and explored.
Theoretical Computer Science, 1992
We present a new linear-time algorithm to construct a rectilinear planar layout (horvertrepresentation. visibility representation) for a given planar graph. Our approach is based on the canonical representation of planar graphs and it is basically different from previous algorithms. If we direct the edges from lower-numbered vertices to higher-numbered vertices and there are)I vertices out of which k vertices have out-degree greater than in-degree, then the maximum width of the constructed layout is r/ 1 max jt/~",(1.,)-d,"(f.,).O1 <2/t-46(1\-2)62n-4. and the maximum height is /I+ I <n. where It is length of the longest directed path. We discuss the selection of a good canonical numbering to be used when constructing layouts. We also show how our algorithm can be applied to compute planar layouts for planar graphs using other drawings for vertices than horizontal segments. In these layouts the drawings for vertices may have arbitrary nonequal sizes and shapes. We know of two earlier linear-time methods for constructing rectilinear planar layouts. First, in 1978 Otten and van Wijk [9] proposed an algorithm for constructing
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