Visual register-transfer description of VLSI microarchitectures

Computer, 1995

Superscalar processor design requires increasingly sophisticated software tools. The visualization-based microarchitecture workbench described here addresses weaknesses common to most performance simulators: the lack of retargetability, visualization support, and interactive control.

2004

Abstract—We detail the syntax and semantics of ISA_ML, a visual modeling language for describing Instruction Set Achitectures of microprocessors, and an accompanying tool that takes a description in the language and generates decoders from it in the form of a disassembler and a micro-architectural trace interfacer.

Proceedings of the 2003 workshop on …, 2003

Understanding modern processors requires a good knowledge of the dynamic behavior of processors. Traditional media like books use text for describing the dynamic behavior of processors. Visualization of this behavior, however, is impossible, due to the ...

Abstract Graph rewriting-based model transformation is an essential tool to process graph-based visual models. If the execution of transformations is not supported by the continuous presentation of the modifications performed on the model, the traceability and the debugging of transformations becomes difficult. Recent modeling tools usually support the definition of rewriting rules based transformations in a visual or textual way, and only a few of them support visual debugging facilities.

Frontiers in Education …, 2008

- Processor implementation and performance analysis are fundamental in computer architecture education. A processor can be described at different abstraction levels: a black box with inputs and outputs, the composition of RT (Register-Transfer) level components, the ...

This paper proposes a new educational tool for Computer Architecture, which can provide simulation of assembly program code (instead of machine language), demonstration of several kinds of sample programs and visualization of register-transfer-level structure/behavior, namely micro-operation. Our educational tool for CPU simulation has been designed and implemented in Javascript language as Web service. Its users select simulation modes by micro step, by machine cycle and by automatic repetition of such cycles. So they can learn how a computer works graphically, recognize inner structure of CPU and understand micro-operation based behavior of CPU. Our Simulator has been also evaluated through some kinds of questionnaires by users/learners in classroom lectures. It is confirmed that the simulator has been very useful and effective to learn Computer Architecture and behav- ior/organization of CPU by means of its application.

This article presents a methodology to describe digital circuits from register transfer level to system level. When designing systems it encapsulates the functionality of several modules and also encapsulates the connections between those modules. To achieve these results, the possibilities of Algorithmic State Machines (ASM charts) have been extended to develop a compiler. Using this approach, a System-on-a-Chip (SoC) design becomes a set of linked boxes where several special boxes encapsulate the connections between modules. The compiler processes all required boxes and files, and then generates the corresponding HDL code, valid for simulation and synthesis. A small SoC example is shown.

Silicon Compilation is a promising approach to designing today's complex ICs, which have rendered traditional design methods inadequate. Here we describe PICSIL, a graphical input language for a silicon compiler, based on Data Flow Diagrams. A PICSIL diagram is a network representation of a digital system. Several devices have been described in PICSIL. One is included here as a demonstration.

Proceedings of the 1990 IEEE Workshop on Visual Languages, 1990

Novis, a visual environment which supports the interactive development and animated simulation of special purpose parallel architectures, is presented. In sharp contrast with other systems which concentrate on the representation of parallelism within programs, Novis lets users design networks at an abstract level by placing processing elements into a connected grid of arbitrary (user selected) shape. The environment's underlying philosophy of maximal information hiding makes intimate familiarity on the part of the user with the details of low{level issues such as process schedule maintenance and event dispatching unnecessary. Layout violations and exceptions detected during execution simulation (e.g., deadlock) are automatically reported to the user. An overview of Novis's features is followed by examples that show o the environment's capabilities in a variety of useful applications.

… of the 33rd annual Design Automation …, 1996

33rd Design Automation Conference 簧 Permission to make digital/hard copy of all or part of this work forpersonal or class-room use is granted without fee provided that copiesare not made or distributed for profit or commercial advantage, thecopyright notice, the title of the ...