Memristor: A Unique Discovery for Reducing Power
vartika pandey2020, International Journal of Innovative Technology and Exploring Engineering
Sign up for access to the world's latest research
checkGet notified about relevant papers
checkSave papers to use in your research
checkJoin the discussion with peers
checkTrack your impact
Abstract
A Process parameter variation has increasing, which results unpredictable device behaviour, due to occurrence of deep submicron CMOS technology. As the time passage this issue is exasperated by low power requirements which are approaching transistor operation into sub threshold regime. Principally for portable devices efficient, capable and process variation amiable memory is the most demandable in the market. In designing of low power memories, leakage power is observant parameter to design low power devices, because leakage power plays a dominant role in the total power utilization of the devices. In this paper, simple 6T SRAM formed with memristor has compared with the technique based 6T SRAM for the various parameters like total power and leakage power
Related papers
Power Dissipation Analysis of Memristor for Low Power Integrated Circuit Applications
This seminar reports a memory resistance (memristor) behavior for low power integrated circuit applications. The power dissipation of memristor is analyzed by using Simulation Program with Integrated Circuit Emphasis (SPICE). For power dissipation checking, the memristor is driven by some power supplies: sinusoidal, trapezoidal, triangular, and rectangle waveforms. From the SPICE simulation results, we found that the power dissipation which is driven by the triangular supply waveform is smaller as compared with the other power supplies.
Comparative analysis of SRAM cell with leakage power reduction approaches
International Journal of Engineering & Technology, 2018
In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T ...
A Novel Low Power Design of SRAM cell and its Performance Analysis
2011
SRAM is a type of semiconductor memory which does not need to be periodically refreshed. With scaling down of the technology, the feature sizes have shrink more and more and miniaturization at chip level has occurred. But as a trade off, the demand for power has also increased. SRAM continues to be a critical component across a gamut of microelectronics applications. Leakage is a serious problem particularly for SRAM. To address sub threshold leakage issue sleepy stack approach is used .The sleepy stack SRAM cell design, is a new technique which involves changing the circuit structure as well as using high-V th. The sleepy stack technique achieves greatly reduced leakage power while maintaining precise logic state in sleep mode. This paper compares performance of SRAM using sleepy stack approach with that of conventional design. The impact of temperature and voltage on the performance of sleepy stack design is also analyzed. Berkeley Predictive Technology Model (BPTM), level 49 targeting 0.18μm technology is used. The design is successfully simulated and analyzed using HSPICE tools.
LEAKAGE POWER REDUCTION IN DEEP SUB MICRON SRAM DESIGN -A REVIEW
Present day electronic industry faces the major problem of standby leakage current, as the processor speed increases, there is requirement of high speed cache memory. SRAM being mainly used for cache memory design, several low power techniques are being used for SRAM cell design. Full CMOS 6T SRAM cell is the most preferred choice for digital circuits. This paper reviews various leakage power techniques used in 6T SRAM cell and their comparative study.
Analysis of Low Leakage Architecture of SRAM 8x1 Using Leakage Power Reduction Technique in Different Technology
as the size of ic's is becoming small, day by day the demand of high density vlsi circuits has been increasing .the supply voltage reduction is necessary to reduce the active power. By lowering the supply voltage it is effective ways to suppress the energy consumption because reducing the supply voltage could reduce the dynamic power and leakage power respectively. In this paper, a technique called cluster technique has been proposed to reduce the active power requirement and the simulation has been done on 8x1 sram cell. In this work firstly the power dissipation of all the cells are connected to an without sleep is taken out then sleep transistor shared with two cells and after that all the four cells are connected to only sleep. Leakage reduction techniques for cmos based transistor level design and the techniques have been proposed like leakage lector technique transistor stack based low leakage approach, sleeper keeper technique for leakage reduction, multiple threshold transistor design technique, gated-clock based low power design etc. Various proposed techniques provide benefits with respect to specific design application. Therefore, result with cluster technique improved result than an individual sleep when connected to the sram cell. In this paper, sram cell without sleep transistor dissipates more power during different states as compared to sram cell with an individual transistor.asthe conventional design is simulated on different cmos fabrication technology using microwind tool. I. INTRODUCTION As with every generation of technology, the demand of handling the large amount of data in embedded memory has been increasing. To fulfill the requirement handling large data feature size of transistor is continuously reducing. With respect to high transistor density the problem of power consumption is becoming prominent issue to tackle. Static Random Access Memory is the first choice of designing semiconductor embedded memories because of low power dissipation. The low power feature for on chip SRAMs is becoming more important especially for battery operated portable applications .It is however one of the most significant challenges of high density VLSI circuit .The main aim of this paper is to estimate the effect of clustering technique on 6T SRAM cell and to investigate transistor sizing of the 6T SRAM cell for optimum power and delay. In this work , an average power dissipation of 6T SRAM Cell has been compared with SRAM cell using cluster technique.The cluster technique reduces the power dissipation of 6T SRAM cell in read, write , and hold operation .
A novel design of low power nonvolatile 10T1R SRAM cell
2016 5th International Conference on Wireless Networks and Embedded Systems (WECON), 2016
Power is a major issue in today's system on chip design at deep submicron. It is very important to control power dissipation in cache memories because 70 % of chip area is covered by memory in microprocessors. Various low power circuits are proposed in the past for volatile memories to alleviate the problem of power dissipation. However in today's era nonvolatile SRAMs (NVSRAMs) are being proposed to restore data along with faster access after power off operation. This paper proposes a nonvolatile Low power 10T1R SRAM cell. The proposed non volatile SRAM cell comprises a conventional 6T SRAM cell, memristor with 1 Transistor, USL technique comprising of 3 transistors, thus making a 10T-1R SRAM Cell. The proposed cell operates in three modes namely write, power off and restore. By simulating the proposed design, the power dissipation has reduced substantially. Experimental results shows that various parameters such as power, delay, power delay product and leakage current has also improved compared to the previous work. The work is done in cadence virtuoso tool at 45nm technology using GDPK045 library with supply voltage V dd =1V
Study and Analysis of Low Power SRAM Memory Array at nano-scaled Technology
IRJET, 2023
The cache memory design of microprocessors makes use of Static Random-Access Memory (SRAM) cells. Their efficiency is crucial because they are an integral part of the central computer system. Only 10-15 percent of a modern system on a chip's (SoC) transistors are dedicated to logic, whereas the rest are used for cache memory, increasing the performance strain. On top of that, the AI-reliant nature of today's implantable, portable, as well as wearable electronic equipment highlights the need for a robust SRAM architecture for CIM. Modern mobile communication devices include ample storage space for users' extensive media collections. Here, we adapt the Multi-threshold CMOS design to create a low-power SRAM cell. Power usage and read/write cycle Access Time can be lowered by using CMOS transistors with various threshold voltages. This work proposes a novel approach to reducing leakage in the idle state to cut down on power usage. The power usage of an SRAM cell is affected by the temperature, size of the transistors as well as the voltage used in the test. Data storage is an important function of several electronic components, specifically digital ones. The overall power usage of an SRAM is heavily influenced by leakage current. The research utilized a 1-bit 6T SRAM cell to construct a 1 KB memory array using CMOS technology and 0.6 volts for the supply voltage. In this section, we use deep submicron (130nm, 90nm, and 65nm) CMOS technology and the six-transistor (6T) SRAM cell to analyze how varying topologies impact the performance of a 12T SRAM array.
Design of Power- and Variability-Aware Nonvolatile RRAM Cell Using Memristor as a Memory Element
IEEE Journal of the Electron Devices Society, 2019
A 3 CNFETs and 2 memristors-based half-select disturbance free 3T2R resistive RAM (RRAM) cell is proposed in this paper. While the two memristors act as the nonvolatile memory elements, CNFETs are employed as high-performance switches. The proposed cell is capable of implementing bit-interleaving architecture and various error correction coding (ECC) schemes can be applied to mitigate soft-errors. The 3T2R cell has been compared with the standard 6T SRAM (S6T) and 2T2R cells. At a supply voltage of 2 V, the 3T2R cell exhibits 7.24× shorter write delay (T WA) and 2.89× lower variability in T WA than that of 2T2R. Moreover, it exhibits 5.08 × /4.33× lower variability in T RA and 1.46 × 10 7 × /2.07× lower hold power (H PWR) dissipation than that of S6T/ 2T2R at V DD = 2 V. In addition, it exhibits tolerance to variations in V th of memristor while being immune to resistance-state drift and random telegraph noise (RTN)-induced instabilities during the read operation. The vastly superior characteristics of CNFET devices over MOSFETs, in combination with memristor technology, leads to such appreciable improvement in design metrics of the proposed design.
Comparative Analysis of Low Leakage SRAM Cell at 32nm Technology
International Journal of Computer Applications, 2016
Continuous scaling of the transistor size and reduction of the operating voltage has led to a significant performance improvement of integrated circuits. Low power consumption and smaller area are the most important criteria for the fabrication of DSP systems. Static random access memories (SRAMs) consist of almost 90% of very large scale integrated (VLSI) circuits. The ever-increasing demand for larger data storage capacity has driven the fabrication technology and memory development toward more compact design rules and, consequently, toward higher storage densities. This paper deals with design of low power static random-access memory (RAM) cells and peripheral circuits for standalone RAMs, in 32nm focusing on stable operation and reduced leakage power dissipation. The work is carried out on Tanner Tool version 13 at 32nm technology.
DESIGN AND ANALYSIS OF 2T2M RRAM-BASED MEMRISTOR
Memory-based memristor technology, referred to as Resistive RAM (RRAM), is one of the emerging memory technologies that can play an efficient role to replace conventional semiconductor memories such as SRAM, DRAM, and eDRAM. The nonvolatile characteristics of the memory-based memristor cells make them more attractive for nonvolatile random access memory design. Existing research on memristor technology focuses mainly on the integration between CMOS and non-CMOS, reliability improvement and fabrication techniques. In this thesis, a 2T2M memory-based memristor cell is introduced which, offers higher stability and noise margins than previous works. The proposed 2T2M RRAM module are similar to conventional 6T SRAM module in terms of number of interface pins and delay. However, the predicted area of the proposed RRAM cell is significantly lower compared to the conventional 6T SRAM cell, and is also expected to consume lower energy. Write and read operations of the proposed RRAM cell are briefly explained. Moreover, the noise margin is analyzed analytically as well as by simulation for memory-based memristor cells in both write and read modes. The proposed analysis is applied on various types of memristor cells used in RRAM modules. Being a passive element, the Static Noise Margin (SNM) analysis used for the traditional 6T SRAM is not applicable on memory-based memristor cells. The effect of noise on the memristor internal state during read and write modes is discussed. An easy-to-use SNM simulation method is presented, the results are in good agreement with the results predicted by the analytic SNM expressions. In addition, based on the introduced noise margin definition, a performance comparison between the RRAM cells is shown using Cadence simulation and a 130-nm technology node for CMOS.
Related topics
Related papers
Trade-off for Leakage Power Reduction in Deep Sub Micron SRAM Design
IJEER, 2016
Present day electronic industry faces the major problem of standby leakage current, as the processor speed increases, there is requirement of high speed cache memory. SRAM being mainly used for cache memory design, several low power techniques are being used for SRAM cell design. Full CMOS 6T SRAM cell is the most preferred choice for digital circuits. This paper reviews various leakage power techniques used in 6T SRAM cell and their comparative study.
Comparison and analysis of various low power SRAM cells
With the advancement of CMOS technology, an outsized variety of transistors used thanks to that scaling happens. Currently on a daily basis memory plays a crucial role within the entire chip and provides the most power to the SOC system. during this paper, 6-T HVP, 7-T HVP, 8-T HVP and 9-T HVP is projected that improve the soundness of SRAM cell, reduce power in read-write operation and reduce escape power in standby mode. 2 techniques accustomed reduce power and escape power. In 1st technique offer voltage of one.1V is taken to look at the power within the overall circuit. In second technique offer voltage of one.1V is taken and voltage given to inputs is about to zero and thence power and escape the power of projected circuits are reduced. The Designed SRAM cells are compared to Existing SRAM cells in term of power, escape power, SNM, RSNM, PULL UP ratio (PR), CELL quantitative relation (CR), Temperature and Voltage. The simulation meted out in Tanner EDA tool with 32nm technology at 1V and CADENCE VIRTUOSO tool with 45nm technology at 1.1V power offer severally.
Study of Speed and Leakage Power Trade-off in Various SRAM Circuits for Mobile Application
International Journal on Emerging Technologies (Special Issue NCETST-2017), 2017
The growing demand of multimedia rich applications in handled portable mobile devices continuously driving the need for bigger and higher speed embedded Static Random Access Memory (SRAM) to boost the system performance. Lots of circuit technique, e.g. body bias, bit charge recycle etc., have been proposed to expand design margins at low voltage operation while reducing leakage current at standby condition, but the performance is analyze at the rate of speed and this issue is not addressed widely. Also due to unbroken scaling of CMOS, the process variation also affect the feature of SRAMs. Paper presents the study of low leakage SRAM along with the speed factor.
Design and Analysis of Two Low-Power SRAM Cell Structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000
In this paper, two Static Random Access Memory (SRAM) cells that reduce the static power dissipation due to gate and sub-threshold leakage currents are presented. The first cell structure results in reduced gate voltages for the NMOS pass transistors, and thus lowers the gate leakage current. It reduces the subthreshold leakage current by increasing the ground level during the idle (inactive) mode. The second cell structure makes use of PMOS pass transistors to lower the gate leakage current. In addition, dual threshold voltage technology with forward body biasing is utilized with this structure to reduce the subthreshold leakage while maintaining performance. Compared to a conventional SRAM cell, the first cell structure decreases the total gate leakage current by 66% and the idle power by 58% and increases the access time by approximately 2% while the second cell structure reduces the total gate leakage current by 27% and the idle power by 37% with no access time degradation.
Design of low-leakage and high writable proposed SRAM cell structure
2014 International Conference on Electronics and Communication Systems (ICECS), 2014
The high demand of embedding more and more functionality in a single chip has enforced the use of scaling. As scaling drastically reduce the channel length the leakage current also increases significantly which increases the static power dissipation. A novel 8T-SRAM cell (Leakage Current Reduced SRAM cell) is proposed which reduces the leakage power dissipation significantly in comparison to the conventional 6T-SRAM cell. The cell is designed using GPDK-90 nm technology library and simulated under Cadence Virtuoso design environment. The proposed cell uses a lower voltage than Vdd during standby mode which leads to a reduction of leakage current and hence the static power consumption. The lower voltage is generated using an NMOS which creates a threshold voltage drop when transfer a high logic. The power consumption is found to be 25.02 % lesser than that of conventional six transistors SRAM cell .The stability and the write ability are measured using the N-Curve technique.
Design and Analysis of 6 T SRAM Cell with low Power Dissipation
2012
In the current technology demand for SRAM is increasing drastically due to its usage in almost all embedded systems, forms a integral part of computer, System On Chip and high performance processors and VLSI circuits etc. The Power Consumption has become a major concern in Very Large Scale Integration circuit designs and reducing the power dissipation has become challenge to the Low power VLSI designers. As power dissipation increases with the scaling of the technologies. As the feature size shrinks ,static power has become a great challenge for current and future technologies. In this research work, we design 6T SRAM and some of the techniques to reduce the leakage power using like sleep approach, stack approach techniques which reduces the leakage power without changing the exact operation of SRAM. The proposed circuits were designed in 0.18um CMOS VLSI technology with a Microwind tool, and measure the power dissipation for the different design approach in Advanced BSIM4 level. Po...
10 T Sram Memory Cell for Leakage Reduction and Low Power Operations
2019
This paper focuses on 10T SRAM Memory Cell for leakage reduction and low power operations. 4T read port with RBL decouples at single end in10T static access memory for reducing power and leakage. Based on the stored data bit RBL discharges. at o.5vdd cells supply voltage RBL is precharged. During operations at read line complementary data node QB , virtual rail of power interfaces to RBL through pass transistor gate.RBL Leakage decreases at virtual rail having control dynamically. For read 1 ,at vdd RBL increases and for read-0 ,it discharges at vss.virtual power rail is connected to true supply level at read operation. At hold and write mode same RBL recharges with virtual power.In 45nm cmos technology, 10t sram cell is proposed with 2.35 times the size of 6T.It has 50% of reduction in dissipation of read power than 6transistor cell. RBL leakage also decreases and read static noise margin increases 2.7 times the 6T .Current ratio during ON and OFF mode has great improvements. Propo...
Novel Design of Low Power Nonvolatile 10T1R SRAM Cell
2017
Power is a major issue in today's system on chip design at deep submicron. It is very important to control power dissipation in cache memories because 70 % of chip area is covered by memory in microprocessors. Various low power circuits are proposed in the past for volatile memories to alleviate the problem of power dissipation. However in today's era nonvolatile SRAMs (NVSRAMs) are being proposed to restore data along with faster access after power off operation. This paper proposes a nonvolatile Low power 10T1R SRAM cell. The proposed non volatile SRAM cell comprises a conventional 6T SRAM cell, memristor with 1 Transistor, USL technique comprising of 3 transistors, thus making a 10T-1R SRAM Cell. The proposed cell operates in three modes namely write, power off and restore. By simulating the proposed design, the power dissipation has reduced substantially. Experimental results shows that various parameters such as power, delay, power delay product and leakage current has ...
Deep sub-micron SRAM design for low leakage
2010
This paper deals with design opportunities of Static Random Access Memory (SRAM) for low power consumption. Initially three major leakage current components are reviewed and then for a 6T SRAM cell, some of the leakage current reduction techniques are discussed. Finally double finger latch is analyzed and compared with single finger latch which shows reduction in sub threshold leakage current.
A Review on Low Power Sram
International Journal of Recent Trends in Engineering and Research, 2017
The main issue in VLSI design are optimizing speed, scaling in silicon technology and increased packing density. These issues account for increased power dissipation in SoC (System on Chips) making them unsuitable for portable operations. Since SRAM consist of almost 60% of VLSI circuits, hence, it is needed that a low power SRAM design to maximize the run time with minimum requirements on size, battery life and weight allocated to batteries. In this paper the basic operation of SRAM along with techniques to reduce total power dissipation are discussed.
Loading Preview
Sorry, preview is currently unavailable. You can download the paper by clicking the button above.