and Communication

Proceedings of the 36th ACM/IEEE conference on Design automation conference - DAC '99, 1999

Partitioning and clustering are crucial steps in circuit layout for handling large scale designs enabled by the deep submicron technologies. Retiming is an important sequential logic optimization technique for reducing the clock period by optimally repositioning flipflops [7]. In our exploration of a logical and physical co-design flow, we developed a highly efficient algorithm on combining retiming with circuit partitioning or clustering for clock period minimization. Compared with the recent result by Pan et al. [lo] on quasioptimal clustering with retiming, our algorithm is able to reduce both runtime and memory requirement by one order of magnitude without losing quality. Our results show that our algorithm can be over 1000X faster for large designs.

Circuit partitioning is the first and the most important step in the designing of VLSI circuits. Owing to the rapidly increasing size of the designs, partitioning tools are becoming more important for the future. The partitioning algorithms are of two types, namely, constructive algorithms and iterative algorithms. In constructive algorithms, partition sets are formed with the help of algorithms; whereas, in case of iterative algorithms, new improved partition sets are formed at each iteration stepwith the modified netlist. A variety of heuristic algorithms have been developed to solve the problem of mincut which is NP-complete. With the main objective of minimizing the cutsize, numerous algorithms have been proposed for circuit partition which includes genetic and evolutionary algorithms, probability-based algorithms, clustering algorithms, and nature-based heuristics. The main intention of this paper is to provide a concise review of the VLSI CAD algorithms adopted for designing VLSI circuits. From the numerous partitioning methods available in the literature, a subjective selection has been made.

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004

When designing a circuit, it may be too large to fit on a single layer of a chip, on a single chip, or on a single board. Regardless of the design level, the same objectives remain. Normally, it is desirable to minimize the number of layers, chips, or boards, along with minimizing the delay. Additional constraints, such as the number of interconnections and power consumption, must often be considered. We have developed two k-way bounded partitioning algorithms; one is evolutionary-based, while the other is a hierarchical graph center-based approach. The algorithms are implemented and compared with known partitioning algorithms. Since VLSI circuits can be naturally modeled by graphs, experiments were conducted by partitioning graphs from various graph families against both simulated and real-world partitioning criteria. A direct result of this research is a high-level abstract graph-partitioning model. This model allows one to specify mathematical evaluation metrics and control parameters, permitting inter-domain comparison of algorithms and allowing one to identify the particular scenarios they are best applicable to.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000

The complexity and size of digital circuits have grown exponentially, and today's circuits can contain millions of logic elements. Clustering algorithms have become popular due to their ability to reduce circuit sizes, so that the circuit layout can be performed faster and with higher quality. This paper presents a deterministic net-reduction-based clustering algorithm called Net Cluster. The basic idea of the proposed technique is to put the emphasis on reducing the number of nets versus the number of cells, thereby capturing the natural clusters of a circuit. The proposed algorithm has proven a linear-time complexity of O(p), where p is the number of pins in a circuit. To demonstrate the effectiveness of the proposed clustering technique, it has been applied to multilevel partitioning and wire length-driven placement.

Iterative methods are greedy or local in nature and get easily trapped in local optima. Usually interchange methods fail to converge to optimal solutions unless they initially begin from good starting points. The choice of starting point is a very crucial factor in the performance of the iterative improvement algorithms. GRASP is a random adaptive simple heuristic that intelligently constructs good initial solutions in an efficient manner. Good initial partitions obtained by GRASP allow the iterative improvement method to refine that initial partition quality in a reasonable amount of time, thus reducing the computational time and enhancing the solution quality. Results obtained indicate that on average the cut-size is reduced by 20% and speedups of up to 90% were achieved using the GRASP technique

Bulletin of Electrical Engineering and Informatics, 2024

The standardization of very-large-scale integration (VLSI) physical architecture for VLSI chips and multichip platforms is now in its early stages of development. The purpose of VLSI partitioning is to divide the circuit into numerous smaller circuits with few connections in between. Partitioning is the fundamental problem in circuit design and division. The efficient method of evolutionary computation may be used to tackle the partitioning problem in VLSI circuit design. It provides a heuristic approach to solve this problem by exploring the solution space and incrementally improving the quality of the solutions. In order to obtain the shortest wire length (WL), area, and connections, an evolutionary optimized simulated annealing memetic algorithm (OSAMA) that incorporates one or more local search phases inside its evolutionary cycle was developed

2007

Partitioning is a critical area of VLSI CAD. In order to build complex digital logic circuits its often essential to sub-divide multi -million transistor design into manageable Pieces. This paper looks at the various partitioning techniques aspects of VLSI CAD, targeted at various applications. We proposed an evolutionary time- series model and a statistical glitch prediction system using a neural network with selection of global feature by making use of clustering method model, for partitioning a circuit. For evolutionary time-series model, we made use of genetic, memetic & neuro-memetic techniques. Our work focused in use of clustering methods - K- means & EM methodology. A comparative study is provided for all techniques to solve the problem of circuit partitioning pertaining to VLSI design. The performance of all approaches is compared using benchmark data provided by MCNC standard cell placement benchmark net lists. Analysis of the investigational results proved that the Neuro-...

2003

2020

Key words: The relevance of VLSI in performance computing, telecommunications, and consumer electronics has been expanding progressively, and at a very hasty pace. In order to build complex digital logic circuits it is often essential to sub-divide multi -million transistors design into manageable pieces. Circuit partitioning is a general approach used to solve problems that are too large and complex to be handled at once. In partitioning, the problem is divided into small and manageable parts recursively, until the required complexity level is reached. In the area of VLSI, circuit complexity is rapidly multiplying, together with the reducing chip sizes; the integrated chips being produced today are highly sophisticated. There are many diverse problems that occur during the development phase of an IC that can be solved by using circuit partitioning which aims at obtaining the sub circuits with minimum interconnections between them. This paper aims at circuit partitioning using clust...

… -Aided Design of Integrated Circuits and …, 2000

In FM algorithm initial partitioning matrix of the given circuit is assigned randomly, as a result for larger circuit having hundred or more nodes will take long time to arrive at the final partition if the initial partitioning matrix is close to the final partitioning then the computation time (iteration) required is small. Here we have proposed novel approach to arrive at initial partitioning by using spectral factorization method the results was verified using several circuits. Keyword-FM algorithm, nodes, spectral factorization method, partitioning I. INTRODUCTION Circuit partitioning serves as one of the most vital part of designing a VLSI circuit. For more than three to four decade, partitioning of circuits has been an interest for many around the globe. After the design is synthesized, the synthesized netlist must undergo a sequence of step before the design can reach the foundry. Circuit partitioning is one of those steps which is involved to partition or separate the whole netlist into some groups of blocks commonly denoted as logical blocks. The circuit partitioning is actually done in order to optimize the circuit by means of separating the circuit into a group of logical block to make the circuit to work efficiently. Although partitioning helps in optimization of circuits, the size of the circuit decides the complexity involved in the task. As the size of the circuit increase the complexity associated in partitioning the circuit into different logical blocks will also increase. To partition the circuit effectively, there were different partitioning algorithms that were used in the past decades. These partitioning algorithm were used to partition the circuit on some constraints, they are 1) Reduction of interconnections between partitions. 2) Reduction of delay due to partitions. 3) Reduction in total number of terminals(less than the predetermined maximum value). 4) Maintenance of area of the partition within specified bounds. 5) Maintenance of number of partition within specified bounds. Different partitioning algorithm may work with different partitioning protocols to partition the circuit. But they all work to achieve the same goals to optimize the circuit. FM algorithm is one of the efficient partitioning technique in which size of each partition is different for different logical block. However, to reduce the complexity involved in partitioning the circuit, each circuit must be modeled as a graph with its nodes representing some logical block and vertices representing the interconnections between those logical blocks. Although there are tools which exist to partition the circuit, the partitioning of circuit in terms of graphs were always viewed as a simpler way to do the partition. To partition the graph in an effective manner, a clustering concept called spectral factorization were used with FM algorithm. Spectral factorization is a concept for which nodes of a graph is clustered in terms of some criterion associated with the graph. This paper gives a novel approach of partitioning irregular graphs by spectral factorization method using FM algorithm.

2013

This article presents a new approach for electronic circuit partitioning. The idea is the usage of hierarchically built clusters of arbitrary sizes created from the border elements of nets that belong to the cut. The process consists of four stages. At the first stage, some initial partitioning is either carried out by a constructive algorithm or generated randomly. At the second stage, two Optimal Reduction Trees are constructed from border elements. The remaining fragments are considered as single elements without border elements. The third stage is the main optimization phase. Iterative optimization procedures consisting in exchanging and transferring of the arbitrary size clusters chosen by the transfer gain are performed during it. The perturbation of the solution concerning the transference of one or a few clusters from one partition to another is used at the fourth stage to escape from the local extrema. (Abstract)

Journal of Algorithms & Computational Technology, 2009

In this paper, clustering for the circuit placement problem is examined from the perspective of wire length contribution from groups of nets. First, the final wire length data of groups of nets with different degrees are extracted and studied. It is illustrated that nets with high-degree contribute a high percentage to the total wire length. To remedy this problem, a clustering algorithm for placement is proposed that focuses on clustering nets with high-degree. This new clustering algorithm is implemented as a preprocessing step in the placement stage. ICCAD04 benchmark circuits abstracted from IBM are used to validate the placement quality by using four academic placers with and without the proposed preprocessing step. Experiments show that the overall placement results can be improved by up to 5%.

Very Large Scale Integration (VLSI) Systems, …, 1993

Proceedings of the 33rd annual Design …, 1996