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1995
There are many methods for the synthesis of logical functions. All these methods can be divided into two classes the first one is Two-Level Logic Synthesis and the second one is Multi-Level Logic Synthesis. The multi-level circuits and their structure are easier for practical realization if there is a large number of variables. In this paper we concentrate on a part of the second class - synthesis of multi-level-circuits with EXOR-gates. We present six methods for EXOR-decomposition for both, completely and incompletely specified functions. In detail, we give an iterative algorithm for checking and calculating the EXOR - groupability for the incompletely specified functions relating to sets of variables. Using this method, it is possible to fully utilize the characteristics and properties of incompletely specified functions enabling synthesis of very efficent circuits.
33rd Design Automation Conference Proceedings, 1996, 1996
The arithmetic functions, as a subclass of Boolean functions, have very compact descriptions in the AND and XOR operators. Any n-bit adder is a prime example. This paper presents a multilevel logic synthesis method which is particularly suited for arithmetic functions and utilizes their natural representations in the field GF(2). Algebraic factorization is performed to reduce the literal count. A direct translation of the AND/XOR representations of arithmetic functions into multilevel networks often results in excessive area, mainly due to the large area cost of XOR gates. We present a process of redundancy removal which reduces many XOR gates to single AND or OR gates without altering the functional behavior of the network. The redundancy removal process requires only to simulate a small and decidable set of primary input patterns. Preliminary results show that our method produces circuits, before and after technology mapping, with area improvement averaging 17% when compared to Berkeley SIS 1.2. The run time is reduced by at least 50%. The resulting circuits also have good testability and power consumption properties.
Lecture Notes in Computer Science, 2014
This paper introduces a new concept of reversible circuits based on EXOR-sum of Products-of-EXOR-sums (EPOE). Two algorithms are introduced that synthesize reversible functions using these new EPOE structures. The motivation for this work is to reduce the number of multiple controlled Toffoli gates and their number of inputs. To achieve these reductions the paper generalizes from existing 2-level AND-EXOR structures (ESOP) commonly used in reversible logic to a mixture of 3level EXOR-AND-EXOR structures and ESOPs. Our approach can be applied to reversible and permutative quantum circuits to synthesize single output functions with one ancilla line per output. In addition, a variant of the algorithm with garbage lines is presented. A comparison of the ESOP minimizer EXORCISM-4 and variants of the new EPOE minimizer, called EPOEM-1s and EPOEM-1f, is presented. The results show that EPOE circuits do in fact achieve the above-stated cost reductions, in particular when expressed in terms of Maslov's quantum cost model commonly used in quantum circuit synthesis.
Springer eBooks, 2007
We define a new algebraic form for Boolean function representation, called EXOR-Projected Sum of Products (EP-SOP ), consisting in a four level network that can be easily implemented in practice. Deriving an optimal EP-SOP from an optimal SOP form is a NP NP -hard problem; nevertheless we propose a very efficient approximation algorithm, which returns, in polynomial time, an EP-SOP form whose cost is guaranteed to be near the optimum. Experimental evidence shows that for about 35% of the classical synthesis benchmarks, EP-SOP networks have a smaller area and delay with respect to the optimal SOPs (sometimes gaining even 40-50% of the area). Since the computational times required are extremely short, we recommend the use of the proposed approach as a post-processing step after SOP minimization.
The paper presents a theorem that forms a foundation to all well-known and all possible new canonical circuits with EXOR output gates. Let M be a 2 n 2 n binary matrix with columns corresponding to minterms and rows corresponding to a family of Boolean functions of n variables. M i,j] = 1 means that the Boolean function of row "i" includes the minterm corresponding to column "j". If the rows are linearly independent with respect to bit-by-bit EXOR operation, then the family is called "orthogonal family of Boolean functions". The functions from the family are c alled "orthogonal" functions. The theorem states that for any orthogonal family of 2 n Boolean functions f i of n variables represented a s a 2 n 2 n matrix M, there exists a canonical three-level realization F = f 0 S 0 ::: f 2 n ;1 S 2 n ;1 , where functions f i are the given orthogonal functions, and coe cients S i are determined by multiplying matrix M ;1 by the vector of minterms FV of function F. Each such canonical expansion creates also an universal cell that can be u s e d in multi-level trees, Directed Acyclic Graphs (DAGs), and generalized functional decision diagrams. Generalizations to multi-output incompletely speci ed functions F, and the concept of partitioned AND/OR/EXOR PLAs are a l s o p r esented. Finally we illustrate practicality of these concepts in application to Fine Grain Field Programmable Gate Arrays (FPGAs) and to cellular logic in general.
VLSI Design, 1995
During the last decade, many different approaches have been proposed to solve the multiple-level synthesis problem with different minimum functionally complete systems of primitive logic blocks. The most popular of them is the division-based approach. However, modem microelectronic technology provides a large variety of building blocks which considerably differ from those typically considered. The traditional methods are therefore not suitable for synthesis with many modem building blocks. Furthermore, they often fail to find global optima for complex designs and leave unconsidered some important design aspects. Some of their weaknesses can be eliminated without leaving the paradigm they are based on, other ones are more fundamental. A paradigm which enables efficient exploitation of the opportunities created by the microelectronic technology is the general decomposition paradigm. The aim of this paper is to analyze and compare the general decomposition approach and the division-based approach. The most important advantages of the general decomposition approach are its generality (any network of any building blocks can be considered) and totality (all important design aspects can be considered) as well as handling the incompletely specified functions in a natural way. In many cases, the general decomposition approach gives much better results than the traditional approaches.
Logic Programming languages and combinational circuit synthesis tools share a common "combinatorial search over logic formulae" background. This paper attempts to reconnect the two fields with a fresh look at Prolog encodings for the combinatorial objects involved in circuit synthesis. While benefiting from Prolog's fast unification algorithm and built-in backtracking mechanism, efficiency of our search algorithm is ensured by using parallel bitstring operations together with logic variable equality propagation, as a mapping mechanism from primary inputs to the leaves of candidate DAGs implementing a combinational circuit specification. Using a new exact synthesizer that automatically induces minimal universal boolean function libraries, we introduce two indicators for comparing their expressiveness: the first, based on how many gates are used to synthesize all binary operators, the second based on how many N-variable truth table values are covered by combining up to M gates from the library. By applying the indicators to an exhaustive enumeration of minimal universal libraries, two dual asymmetrical operations, Logic Implication "⇒" and Half XOR "<" are found to consistently outperform their symmetrical counterparts, NAND and NOR. Our expressiveness metrics bring support to the conjecture that asymmetrical operators are significantly more expressive that their well studied symmetric counterparts, omnipresent in various circuit design tools.
An efficient technique of multiple input digital circuit minimizations is proposed in this paper. The proposed method is very simple and less laborious approach to determine the minimal gate count for multiple input digital switching circuits. This exact method of minimization technique provides a minimal solution based on the breaking of minterms and arrange them in adjacent groups. To avoid bulky size of the truth table for multiple input combinational circuits, a reduced truth table is proposed here and this methodology is able to reduce its present size and at least one operation per minterms. A recursive algorithm for breaking of minterms and set formation is proposed here for computer programming. A 'Set Combine Map' is also proposed here to determine the optimal solution for manual synthesis. The proposed 'Set Combine Map' will be able to overcome successfully all the problems related to Karnaugh Map simplification process for more than four inputs systems by reducing complexity arises in finding and grouping of adjacent minterms in different levels of Karnaugh Map. An efficient minimization technique for multiple inputs and multiple outputs switching system is also proposed here.
2005
This paper proposes a genetic algorithm for designing combinational logic circuits and studies four different case examples: the 2-to-1 multiplexer, the one-bit full adder, the four-bit parity checker and the two-bit multiplier. The objective of this work is to generate a functional circuit with the minimum number of logic gates. It is also studied the scalability problem that emerges from the exponential growth of the truth table when the circuits complexity increases. Furthermore, it is as well investigated the population size and the processing time for achieving a solution in order to establish a compromise between the two parameters.
2016
In this paper, an application of the PKmin program for functional decomposition of multiinput multi-output combinational circuits is presented. The main focus is on balanced multilevel decomposition of logic circuits into minimal number of blocks, such as LUTs in FPGAs. Reduction of the input redundancy is available. Decomposition schemes include parallel, joint/ disjoint serial and a mixed one. The decomposition with PKmin can be automated by means of a heuristic algorithm or can be supervised by the designer. A distinctive feature of PKmin is the visualization of the design steps and the final layout of blocks and their interconnections. PKmin is compared in an example with the program DEMAIN.
Proceedings of the 41st annual conference on Design automation - DAC '04, 2004
This paper shows a method to decompose a given multipleoutput circuit into two circuits with intermediate outputs. We use a BDD for characteristic function (BDD for CF) to represent a multiple-output function. Many benchmark functions were realized by LUT cascades with intermediate outputs. Especially, adders and a binary to BCD converter were successfully designed. Comparison with FPGAs is also presented.
2019
Today, the design of electronic systems is largely automated. The practice of using software automation technologies for the design of electronic hardware is commonly referred to as Electronic Design Automation (EDA). EDA comprises a large set of tools, from languages that specify high-level hardware designs, to software that determines the layout of nanoscale devices on an integrated circuit. Within this collection, an important role is played by so-called logic synthesis algorithms. A substantial field of research onto itself, logic synthesis can be roughly thought of as the problem of finding good representations for Boolean functions. Such functions are the backbone of digital circuits, which can be thought of, to a first approximation, as devices that compute with Boolean values. In other words, circuits can be viewed simply as large Boolean functions. Logic synthesis, then, is assigned the important task of finding good structural representations for such circuits. Choosing th...
IEE Proceedings - Computers and Digital Techniques, 1996
An algorithm called XOF.GA is presented which minimises Boolean mult i-output logic functions as multilevel ANDEXOR networks of two-input logic gates. It carries out symbolic simplification, and works from tlhe bottom of a binary variable decision tree to tlhe top, with variable choice determined using a genetic algorithm. Since the algorithm is multilevel in nature, it delivers more compact circuits than two-level ESOP minimisation algorithrrts, such as EXMIN2. it also finds more economical representations than the fixed polarity Ree& Muller method.
1995
VLSI Design, 1995
This paper introduces several new families of decision diagrams for multi-output Boolean functions. The introduced families include several diagrams known from literature (BDDs, FDDs) as subsets. Due to this property, these diagrams can provide a more compact representation of functions than either of the two decision diagrams. Kronecker Decision Diagrams (KDDs) with negated edges are based on three orthogonal expansions (Shannon, Positive Davio, Negative Davio) and are created here for incompletely specified Boolean functions as well. An improved efficient algorithm for the construction of KDD is presented and applied in a mapping program to ATMEL 6000 fine-grain FPGAs. Four other new families of functional decision diagrams are also presented: Pseudo KDDs, Free KDDs, Boolean Ternary DDs, and Boolean Kronecker Ternary DDs. The last two families introduce nodes with three edges and require AND, OR and EXOR gates for circuit realization. There are two variants of each of the last two...
2017 Euromicro Conference on Digital System Design (DSD)
This paper presents a method for generating optimum multi-level implementations of Boolean functions. It is based on Satisfiability (SAT) problem solving, while different SAT techniques are employed to reach different targets. The method is able to generate one, or enumerate all optimum implementations, while any technology constraints can be applied. Results for 4-input functions implemented by XOR-AND-Inverter-Graphs (XAIGs) with different XOR nodes costs are presented. Scalability and feasibility of the method is presented. Finally, an experimental evaluation of XAIG-based rewriting algorithm with optimum replacement circuits is presented and compared with the previous solution.
1993
Abstract We present a new algorithm for exact two-level logic optimization. It di ers from the classical approach; rather than generating the set of all prime implicants of a function, and then deriving a covering problem, we derive the covering problem directly and implicitly, and then generate only those primes involved in the covering problem. We represent a set of primes by the cube of their intersection. We then derive some properties of the sets of primes which form this set covering problem.
Facta universitatis - series: Electronics and Energetics, 2018
Bi-Decomposition is a powerful approach for the synthesis of multi-level combinational circuits because it utilizes the properties of the given functions to find small circuits, with low power consumption and low delay. Compact bi-decompositions restrict the variables in the support of the decomposition functions as much as possible. Methods to find compact AND-, OR-, or XOR-bi-decompositions for a given completely specified function are well known. A lattice of Boolean functions represents all possible functions which are defined by an incompletely specified function. Lattices of Boolean Functions significantly increase the possibilities to synthesize a minimal circuit. However, so far only methods to find compact AND-or OR-bi-decompositions for lattices of Boolean functions are known. This gap, i.e., a method to find a compact XOR-bi-decomposition for a lattice of Boolean functions, has been closed by the approach suggested in this paper.
2017
Bi-Decomposition is a very powerful approach for the synthesis of multi-level combinational circuits because it utilizes the properties of the given functions to find small circuits, with low power consumption and low delay. Compact bi-decompositions restrict the variables in the support of the decomposition functions as much as possible. Methods to find compact AND-, OR-, or XOR-bi-decompositions for a given completely specified function are well known. Lattices of Boolean Functions significantly increase the possibilities to synthesize a minimal circuit. However, so far only methods to find compact ANDor OR-bi-decompositions for lattices of Boolean functions are known. This gap, i.e., a method to find a compact XOR-bi-decomposition for a lattice of Boolean functions, has been closed by the approach suggested in this paper. A lattice of Boolean functions represents all possible functions which are defined by an incompletely specified function. In the context of vectorial bi-decompo...
IEEE Transactions on Computers, 1969
A decomposition and reconstruction approach for syn- thesizing an arbitrary Boolean function with a minimum number of threshold logic elements connected by feedforward paths only is presented. Attention is mainly focused on cascade-type realizations. The approach has the advantage that near-minimal solutions are readily derived. An estimate of how closely the minimality has been approached is obtainable in this method. The method has been suc- cessfully applied by the authors to Boolean functions of 5 and 6 vari- ables.
Objective of this paper is to present historiography of logic switching circuits. The research mainly focuses on chronological development and application of logic in the field of electronic and computer applications. This paper briefly discussed on the basic needs of logic synthesis and also discuss few interesting facts and design consideration regarding logic synthesis. It also enhances student’s deep understanding of different logic function minimization technique during a lecture and practical implementation.
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