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Behavioral models are used for top-down design and for bottom-up verification. The efficient simulation of large-scale dynamical system needs a systematic procedure for order reduction of the original circuit. A method based on the moment matching for behavioral model generation of analog integrated circuits and by comparison some approaches to obtain an accurate approximation of the circuit function are presented. It is shown that we can handle the MIMO system using the semi-state method and Padé approximation. An illustrative example is given and some conclusions are pointed out.
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012
Large analog circuit models are very expensive to evaluate and verify. New techniques are needed to shorten timeto-market and to reduce the cost of producing a correct analog integrated circuit. Model order reduction is an approach used to reduce the computational complexity of the mathematical model of a dynamical system, while capturing its main features. This technique can be used to reduce an analog circuit model while retaining its realistic behavior. In this paper, we present an approach to model order reduction of nonlinear analog circuits. We model the circuit using fuzzy differential equations and use qualitative simulation and K-means clustering to discretion efficiently its state space. Moreover, we use a conformance checking approach to refine model order reduction steps and guarantee simulation acceleration and accuracy. In order to illustrate the effectiveness of our method, we applied it to a transmission line with nonlinear diodes and a large nonlinear ring oscillator circuit. Experimental results show that our reduced models are more than one order of magnitude faster and accurate when compared to existing methods.
International Journal of Modeling and Optimization, 2014
Electronics, 2021
For mixed-signal systems, identifying the analog and digital circuit blocks in the transistor-level netlist has many benefits for system analysis and verification. However, existing approaches still have difficulty handling large mixed-signal designs with millions of transistors, especially when multiple analog structure patterns are included. In this paper, we propose an efficient structure recognition methodology to support analyzing highly complex designs with various circuit structures and different devices. In order to tackle the complexity of real cases, a hierarchical partition-based analysis methodology and an encoding-based fast screening technique are proposed in this work. To correctly ascertain the boundary of analog and digital structures, we propose an enhanced direct current connection (DCC) partition method and combine it with the analog structure analysis flow. The non-transistor devices, such as resistors and capacitors, are also included in our recognition flow to...
A new method for automatic behavioral modeling of nonlinear analog circuits is proposed. It combines two different modeling approaches in order to use their respective advantages. At first, a structural analysis of the circuit to be modeled is performed. This leads to a substitution of defined circuit structures by predefined behavioral models. In the second step the resulting set of differential algebraic equations (DAEs) is simplified symbolically. Each substitution and each simplification step is checked concerning input/output behavior with respect to the behavior of the original net-list. For this purpose, a set of testbenches with diferent simulation parameters, including DC-Transfer, AC and transient simulations can be specified. The feasibility of the combined method is shown by example. .
International Journal of Advanced Manufacturing Technology, 2010
In the EU-project O-MOORE-NICE! 1 major achievements have been obtained in dedicated computational methods for integrated circuit (IC) design: Model Order Reduction (MOR) techniques for linear and nonlinear problems; behavioral modeling; and multi-objective optimization, and response surface modeling. On all these topics, not only a lot of publications have appeared in journals and conference proceedings, but also lectures were given at industry and at universities. Furthermore, prototype software is in use at both NXP and the academic partners. Among the successes are the development of nonlinear phase macromodeling techniques for analysis of oscillators, a new approach of nonlinear MOR via table interpolation and response surface modeling, and algorithms for the solution of large networks arising in Electro-Static Discharge analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000
A novel technique for the numerical extraction of equivalent circuits from physics-based device simulation is presented. The method is based on the partitioning of the device into functional regions, each corresponding to a circuit block. All the circuit elements have a clear physical interpretation. Element values are directly obtained from small-signal dc device simulation. The method generates equivalent circuits of a complexity similar to the traditional approach, with model generation times comparable with those of black-box and physics-based device models. Applications to one-dimensional junctions and bipolar transistors are presented, discussing the extraction algorithm in detail.
2008
The efficient simulation of large-scale dynamic systems needs a systematic procedure for order reduction of the original circuit. The paper combines the projection method with Krylov subspaces to obtain robust and accurate order reduction techniques. First of all, the algorithm finds a basis matrix onto Krylov subspaces, using a block Arnoldi process, and then constructs a reduced-order model via projection technique. It is shown that we can handle the MIMO systems using the semi-state method and Krylov projection method. An illustrative example is given and some conclusions are pointed out.
2010 12th International Conference on Optimization of Electrical and Electronic Equipment, 2010
The behavioral simulation of large-scale analog circuits is very expensive. Instead of the circuit complex model, reduction of the computing effort implies using a macromodel capable to capture the behaviors of the original circuit while preserving its essential properties. Building such a model is based on a simplified and unitary description of the circuit, by establishing a simple relationship between the input/output variables. In this paper, the model order reduction techniques based on method projection in Krylov subspace are presented in two implementation: on state equations and on semi-sate equations of the analog circuits. Illustrative simulations are performed that allow a comparison of the standard methods based on Padé approximation with Krylov subspace methods, and some important conclusions.
For analog and mixed-signal circuit design a modeling methodology is needed which is well suited to the requirements of a structured synthesis flow. It ensures that the intended specification is met without over-design. Behavioral models are able to provide circuit level knowledge on higher abstraction levels by including non-idealities and parasitics from the circuit realization, which allows realistic comparison of different architectures. At the same time these models are fast enough to explore design space and optimize specification translation with respect to system performance measures. This paper shows how numerical, analytical, and symbolic methods as part of an integrated modeling methodology are used for model generation, model parameterization, and model refinement in order to improve and accelerate analog circuit synthesis
International Journal of Foundations of Computer Science, 2010
Verification of analog/mixed-signal (AMS) circuits is complicated by the difficulty of obtaining circuit models at suitable levels of abstraction. We propose a method to automatically generate abstract models suitable for formal verification and system-level simulation from transistor-level simulation traces. This paper discusses the application of the proposed methodology to a switched capacitor integrator and PLL phase detector.
2007 Eighth International Workshop on Microprocessor Test and Verification, 2007
models of analog/mixed-signal (AMS) circuits can be used for formal verification and system-level simulation. The difficulty of creating these models precludes their widespread use. This paper presents an automated method to generate abstract models appropriate for system-level simulation and formal verification. This method uses simulation traces and thresholds on the design variables to generate a piecewise-linear representation of the system. This piecewise-linear representation can be converted to a Verilog-AMS model or a Labeled Hybrid Petri Net formal model. Results are presented for the model generation, simulation, and verification of a PLL phase detector circuit.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2004
Efficient algorithms are presented to generate approximate expressions for transfer functions and characteristics of large linear analog circuits. The algorithms are based on a compact determinant decision diagram (DDD) representation of exact transfer functions and characteristics. Several theoretical properties of DDDs are characterized, and three algorithms, namely, based on dynamic programming, based on consecutive k-shortest path based, and based on incremental k-shortest path, are presented in this paper. We show theoretically that all three algorithms have time complexity linearly proportional to |DDD|, the number of vertices of a DDD, and that the incremental kshortest path based algorithm is fastest and the most flexible one. Experimental results confirm that the proposed algorithms are the most efficient ones reported so far, and are capable of generating thousands of dominant terms for typical analog blocks in CPU seconds on a modern computer workstation.
2014
– This paper addresses the use of Analog Behav-ioral Models (ABMs) in an efficient strategy for designing analog emulation engines for large scale power system com-putation. Through discussion of historical development of analog computation in power system analysis and its present resurgence, we present the need for, and application of ABMs for model verification and validation prior to full structural design and implementation. Results of PSpice simulations of these emulation circuits are also presented and compared with industrial grade numerical simulations for validation.
Analog simulation methodologies for the generation of macromodels of analog functional blocks, as reported in literature, are of limited use in practical circuit simulation due to frequent accuracy and efficiency problems. In this paper, a new approach to model the behavior of nonlinear functional blocks is proposed. The approach is based upon the principles of systems theory. The outlined methodology supports the mapping of models from component into behavioral level. The nonlinearity of complex analog modules is reflected efficiently while the electrical signals are maintained.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991
The advantages of using macromodels of functional blocks in the simulation of large scale circuits have long been pointed out. However, all the methods for generating macromodels that have so far appeared in the literature make very stringent assumptions about either the type of circuits to be modeled or the shape of the waveforms involved. The models generated in this way are, therefore, of limited use in general circuit simulation. In this paper we propose a general purpose macromodeling algorithm applicable to any type of circuit without any restrictions on the waveforms. Starting from a user-supplied template, the algorithm modifies the values and the branch characteristics of macromodel elements with the goal of optimizing the macromodel's time-domain accuracy. Experimental results obtained so far indicate that the algorithm requires reasonable amounts of CPU time and that the models are accurate enough to be used for standard circuit simulation.
In this paper, analogue behavioural modelling (ABM) is applied to the synthesis of linear filters within the frequency-domain. The synthesis procedure splits into two main variants that are expound in the paper. In a first part, the modelling techniques are applied to the well-known Sallen & key structures by focussing on the modelling of the active component, i.e. the operational amplifier. In the second part, the ABM focusses directly on the transfer function to be synthesised. Final results of the presented ABM methodology are specified in the form of Verilog-A code and circuit simulations.
IEEE Circuits and Systems Magazine, 2014
circuit simulation is seen by some people as a well established discipline, where there remains little or no space for improvement. yet, no steady state and stability analysis methods are available for circuits described by a combination of analog, digital and behavioral parts. recently, the theory necessary for development of such simulators was proposed and a circuit simulator incorporating these theoretical developments has been presented. It manages analog, digital and behavioral components, while retaining all the classical "spice-like" features. this was possible by importing some mathematical concepts from the hybrid dynamical systems realm. such tools represent the interface between the conventional analog world and the more contemporary digital/behavioral one. the reviewed simulation framework is appealing not only for people interested in circuit analysis and design, but for all researches and engineers working in the wider field of system simulation where the analog mixed signal concept is absolutely pervasive.
IEEE Transactions on Components, Packaging and Manufacturing Technology, 2021
This paper proposes a black-box behavioral modeling framework for analog circuit blocks operating under smallsignal conditions around non-stationary operating points. Such variations may be induced either by changes in the loading conditions or by event-driven updates of the operating point for system performance optimization, e.g., to reduce power consumption. An extension of existing data-driven parameterized reduced-order modeling techniques is proposed that considers the time-varying bias components of the port signals as non-stationary parameters. These components are extracted at runtime by a lowpass filter and used to instantaneously update the matrices of the reducedorder state-space model realized as a SPICE netlist. Our main result is a formal proof of quadratic stability of such Linear Parameter Varying (LPV) models, enabled by imposing a specific model structure and representing the transfer function in a basis of positive functions whose elements constitute a partition of unity. The proposed quadratic stability conditions are easily enforced through a finite set of small-size Linear Matrix Inequalities (LMI), used as constraints during model construction. Numerical results on various circuit blocks including voltage regulators confirm that our approach not only ensures the model stability, but also provides speedup in runtime up to 2 orders of magnitude with respect to full transistor-level circuits.
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)
The paper presents a novel approach to behavioral modeling of analog circuits by dynamic semi-symbolic analysis, where some circuit parameters are kept as symbols and the others are given as numeric values. Our new method is based on the determinant decision diagram (DDD) representation of small-signal characteristics of linear analog circuits. The basic idea is to dynamically reorder DDD vertices such that all the DDD vertices corresponding to symbolic parameters are separated from DDD vertices for numerical parameters. In this way, DDD sizes of symbolic portion of DDD can be significantly reduced by suppressing numerical DDD nodes. Our new approach is different from the existing MTDDD based semi-symbolic analysis method where reordering is done before DDD is constructed and DDD-based graph operations are still valid in the new method. The proposed dynamic ordering algorithm, which is based on swap of adjacent variables, also improves the existing DDD-based vertex sifting algorithm as no special sign rule is required after DDD vertices are swapped. Experimental results have demonstrated that the proposed dynamic semi-symbolic method leads to up to 30% symbolic DDD node reduction compared MTDDD method on real analog circuits and can be performed very efficiently.
1993
Abstract In analog system design, final verification in the presence of parasitic loading effects is crucial to guarantee functionality of the entire circuit. In this paper, we present a methodology for analog system verification in the presence of parasitics using behavioral simulation. When applied to a synthesized 10 bit D/A, our approach is accurate to 0.005 LSB compared with SPICE, while being several orders of magnitude faster.
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