Structural FSM Traversal

2000

State space exploration is often used to prove properties about sequential behavior of Finite State Machines (FSMs). For example, equivalence of two machines is proved by analyzing the reachable state set of their product machine. Nevertheless, reachability analysis is infeasible on large practical examples. Combinational verification is far less expensive, but on the other hand its application is limited to combinational circuits, or particular design schemes. Finally, approximate techniques imply sufficient, not strictly necessary conditions. The purpose of this paper is to extend the applicability of purely combinational checks. This is generally achieved through state minimization, partitioning, and re-encoding the FSMs to factor out their differences. We focus on re-encoding. In particular, we present an incremental approach to re-encoding for verification that transforms the product machine traversal into a combinational verification in the best case, and into a computationally simpler product machine traversal in the general case. Experimental results demonstrate the effectiveness of this technique on medium-large circuits where other techniques may fail.

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051), 1999

The knowledge of the reachable states of a sequential circuit can dramatically speed up optimization and model checking. However, since exact reachability analysis may be intractable, approximate techniques are often preferable. Cho et al. presented the Machine-By-Machine (MBM) and Frame-By-Frame (FBF) methods to perform approximate FSM traversal. FBF produces tighter upper bounds than MBM; however, it usually takes much more time and it may have convergence problems. In this paper, we show that there exists a class of methods-Least Fixpoint Approximationsthat compute the same results as RFBF (Reached FBF, one of the FBF methods). We show that one member of this class, which we call Least fixpoint MBM (LMBM), is as efficient as MBM, but provably more accurate. Therefore, the trade-off that existed between MBM and RFBF has been eliminated. LMBM can compute RFBFquality approximations for all the large ISCAS-89 benchmark circuits in a total of less than 9000 seconds.

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002

We increase the reasoning power of the Record & Play algorithm for structural FSM traversal presented in [16] by incorporating a constraint-satisfying simulation technique. Combinational verification tools often use simulation to identify candidates for internally equivalent functions. This can significantly reduce the computational costs needed to prove the equivalence of two circuits. The key idea to improve Record & Play is to perform a random simulation in every time frame that satisfies stored equivalences and constants which are needed to represent the state set. Our experimental results show the benefit of the proposed approach.

Journal of Systems Architecture, 2000

Symbolic traversals are state-of-the-art techniques for proving the input/output equivalence of ®nite state machines. Due to state space explosion, they are currently limited to medium-small circuits. Starting from the limits of standard techniques, this paper presents a mix of approximate forward and exact backward traversals that results in an exact exploration of the state space of large machines. This is possible, thanks to ecient pruning that restricts the search space during backward traversal using the information coming from the approximate forward traversal step. Experimental results con®rm that we are able to explore for the ®rst time some of the larger ISCAS'89 and MCNC circuits, that have been until now outside the scope of exact symbolic techniques. We are also able to generate the test patterns for or to tag as undetectable stuck-at faults with few exceptions.

SSRN Electronic Journal, 1995

Computing the set of reachable states of a finite state machine, is an important component of many problems in the synthesis, and formal verification of digital systems. The process of design is usually iterative, and the designer may modify and recompute information many times, and reachability is called each time the designer modifies the system, because current methods for reachability analysis are not incremental. Unfortunately, the representation of the reachable states that is currently used [1] in synthesis and verification, is inherently non-updatable. We solve this problem by presenting alternate ways to represent the reachable set, and incremental algorithms that can update the new representation each time the designer changes the system. The incremental algorithms use the reachable set computed at a previous iteration, and information about the changes to the system to update it, rather than compute the reachable set from the beginning. This results in computational savings, as demonstrated by the results

Electronic Notes in Theoretical Computer Science, 2008

Binary Decision Diagrams (BDDs) and their multi-terminal extensions have shown to be very helpful for the quantitative verification of systems. Many different approaches have been proposed for deriving symbolic state graph (SG) representations from high-level model descriptions, where compositionality has shown to be crucial for the efficiency of the schemes. Since the symbolic composition schemes deliver the potential SG of a high-level model, one must execute a reachability analysis on the level of the symbolic structures. This step is the main resource of CPU-time and peak memory consumption when it comes to symbolic SG generation. In this work a new operator for zero-suppressed BDDs and their multi-terminal extensions for carrying out (partitioned) symbolic reachability analysis is presented. This algorithm not only replaces standard BDD-based schemes, it even makes symbolic composition as found in contemporary symbolic model checkers such as Prism and Caspa obsolete.

Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition

BDD{based symbolic traversals are the state-of-theart technique for reachability analysis of Finite State Machines. They are currently limited t o m e dium{small circuits for two reasons: BDD peak size during image computation and BDD explosion for state space r epresentation. Starting from these limits, this paper presents a technique that decomposes the search space d e creasing the BDD peak size and the number of page faults during image computation. Results of intermediate computations and large BDDs are eciently stored in the secondary memory. A decomposed t r aversal that allows exact explorations of state spaces is obtained. Experimental results show that this approach is particularly eective on the larger MCNC, ISCAS'89, and ISCAS'89{addendum circuits.

Lecture Notes in Computer Science, 2005

We propose a new saturation-based symbolic state-space generation algorithm for finite discrete-state systems. Based on the structure of the high-level model specification, we first disjunctively partition the transition relation of the system, then conjunctively partition each disjunct. Our new encoding recognizes identity transformations of state variables and exploits event locality, enabling us to apply a recursive fixed-point image computation strategy completely different from the standard breadth-first approach employing a global fix-point image computation. Compared to breadth-first symbolic methods, saturation has already been empirically shown to be several orders more efficient in terms of runtime and peak memory requirements for asynchronous concurrent systems. With the new partitioning, the saturation algorithm can now be applied to completely general asynchronous systems, while requiring similar or better run-times and peak memory than previous saturation algorithms.

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 2001

We present a new symbolic algorithm for reachability analysis in sequential circuits. Using don't cares from the computed reachable states, we introduce flexibility in choosing the transition relation, which can be used to minimize its Binary Decision Diagram (BDD). This can reduce the time-consuming image computation step. The technique is implemented and integrated in our equivalence checking system M-CHECK and its efficiency is shown on the ISCAS-89 benchmark circuits.