Initialization of Partially LBISTed Sequential Circuits

Proceedings Eighth Asian Test Symposium (ATS'99), 1999

As opposed to scan schemes, a non-scan DFT allows at-speed testing. This paper suggests three techniques on non-scan DFT of sequential circuits. The proposed techniques guarantee 100% fault efficiency by using combinational ATPG tool. In all techniques, an additional circuit called CRIS is proposed to reach unreachable states on the state register of a machine. The second and third techniques use an additional hardware called differentiating logic (DL), that uniquely identifies a state appearing in a state register. The design of DL is universal, i.e., not dependent on the circuit structure. Hardware overhead of DL and CRIS is lower than that of full scan. Test generation and application time are found to compare favorably with those of earlier designs. * The ratio of number of faults detected or proved redundant by a test algorithm to the total number of faults in a circuit is known as fault efficiency.

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

We present a procedure to determine initialization sequences for a sequential circuit optimizing sequence length and unknown values (Xes) in the flip-flops.

2005

High-level synthesis tools are very important for designing electronic circuits. A lower level logic gates are synthesized by optimization of the circuit’s combination part, which is then realized by mapping on programmable devices such as FPGAs. This synthesis process is a computation intensive task. In this paper, we propose an alternative method to synthesis a sequential logic circuit which reduces time consuming in synthesis process. First using a parallel partitioning algorithm partition the whole circuit into sub-circuits and then using parallel sub-circuit synthesis in order to reduce computation. The LGSynth’91 benchmark suite used for experiment is in net-list format. Our result shows that the number of partition is increasing whereas the synthesis time is reduced as the number of processor is increased.

IFAC Proceedings Volumes, 2004

In this paper effective method of FSM implementation in Embedded Memory Blocks of FPGAs structures is presented. Memory blocks allow implementation of sequential machines in a way that requires less logic cells than the traditional flip-flop based implementation. This may be used to implement sequential parts of the design, saving logic cell resources for more important sections. Unfortunately the size of the memory available in programmable devices is limited. In addition, these blocks can be arranged in limited number of configurations. These features require specific implementation approach to utilize the capacity of each EMB in highest possible degree. To reduce memory usage decomposition-based methods can be successfully applied. In order to effectively use available memory blocks one can build a logic network, where large logic encoding functions can be implemented in EMBs. An appropriately chosen decomposition strategy allows very effective utilization of available EMBs.

2009 Annual IEEE India Conference, 2009

Full scan based design technique is widely used to alleviate the complexity of test generation for sequential circuits. However, this approach leads to substantial increase in test application time, because of serial loading of vectors. Although BIST based approaches offer faster testing, they usually suffer from low fault coverage. In this paper, we propose a hybrid test architecture, which achieves significant reduction in test application time. The test suite consists of: (i) some external deterministic test vectors to be scanned in, and (ii) internally generated responses of the CUT to be re-applied as tests iteratively, in functional (non-scan) mode. The proposed architecture uses only combinational ATPG to hybridize deterministic testing and test per clock BIST, and thus makes good use of both scan based and non-scan testing. We also present a bipartite graph based heuristic to select the deterministic test vectors and sequential fault simulation technique is used to perform the exact analysis on detected faults during the re-application of internally generated responses of the CUT during testing. Experimental results on ISCAS-89 benchmark circuits show the efficacy of the heuristic and reveal a significant reduction of test application time.

2010 19th IEEE Asian Test Symposium, 2010

A globally-asynchronous and locally-synchronous (GALS) system has been known as a realistic hardware design solution for many difficulties such as global clock network that arise due to the continuous scaling of semiconductor technology. Although a full scan design method for synchronous circuits is applied to asynchronous circuits to achieve the same testability of their combinational parts, the overhead is extremely high. To reduce the overhead, several variation of scan-based approaches have been proposed but they cannot guarantee complete test. In this paper, we propose a bipartite full scan design as a new DFT method for asynchronous circuit where we guarantee complete test for both combinational and sequential parts of circuits with area and performance overhead comparable to the previous best method in terms of overhead.

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, 2007

Modern FPLD devices have a very complex structure. They combine PLA-like structures as well as FPGA's and even memory-based structures. However, the lack of an appropriate synthesis method does not allow the features of the modern FPLD's to be fully exploited. In this paper, an important problem of state assignment for an FSM as an extension of the previous research on ROM-based FSM implementation is presented. We pinpoint the sources of additional optimization of the functional decomposition and relate them to the state encoding conditions. The method is based on a reduction of a state assignment problem to a graph coloring problem. To this end, the so called multi-graph of incompatibility of memory T-words is applied. As a result, a new design technique for implementation of sequential circuits using embedded memory blocks of FPGA's has been developed. Preliminary experimental results are extremely encouraging.

1990

Abstract It is shown that optimal sequential logic synthesis can produce irredundant, fully testable finite-state machines. Synthesizing a sequential circuit from a state transition graph description involves the steps of state minimization, state assignment, and logic optimization. Previous approaches to producing fully and easily testable sequential circuits have involved the use of extra logic and constraints on state assignments and logic optimization.

1995

Representing finite state systems by means of finite state machines is a common approach in VLSI circuit design. BDD-based algorithms have made possible the manipulation of FSMs with very large state spaces; however, when the representation of the set of reachable states grows too much, the original FSM is no longer manageable as a whole, and it needs to be decomposed into smaller sub-machines. Structural analysis of the circuit from which the FSM has been extracted has shown to be very effective to determine good state variable partitions which induce FSM decomposition for logic synthesis and formal verification applications. In this paper we propose FSM analysis techniques based on connectivity and spectra1 characteristics of the state machine which take into account the mutual dependency of the state variables, but which are no longer dependent on the structure of the underlying circuit; therefore, they may be used in a context different from sequential logic optimization and FSM verification. Experimental results are presented and discussed for the Mc~c'91 FSM benchmarks and for the Isc~s'89 sequential circuits. 01656074/95/$09.50 0 1995 Elsevier Science B.V. All rights reserved SSDl 0 165-6074(95)00028-3

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1994

In this thesis, we address the problem of optimizing sequential logic circuits for low power. We present a powerful optimization method that selectively precomputes the outputs of the circuit one clock cycle before they are required and uses the precomputed values to reduce switching activity in the next clock cycle. We present different Although this work bears my name, it is a result of the efforts and contributions of several people. First and foremost, I would like to thank Professor Srinivas Devadas, my thesis supervisor, for his original contributions and help throughout this project. His patience, willingness to discuss ideas, and enthusiasm have made it a unique and enjoyable learning experience for me. I would also like to thank Dr. Abhijit Ghosh of Mitsubishi Electric Research Laboratories and Professor Marios Papaefthymiou of Yale University for their contributions to this work. Thanks to Jose Monteiro for his work in power estimation, his help in implementing this project, and all the interesting discussions on low power design. He has been a good friend and a source of inspiration. I am also grateful to Stan Liao and Amelia Shen for helping me learn the synthesis tools, and to Luis Miguel Silveira for his assistance in customizing this document. In addition, I thank all members of the 8 th floor VLSI group especially Xuejun Cai, Songmin Kim, and Ricardo Telichevesky for their encouragement. Finally, I would like to thank my parents and my two sisters, Ateka and Noren, for their unconditional love and support.