A novel methodology for transistor-level power estimation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000

In this paper, we present a new gate-level approach to power and current simulation. We propose a symbolic model of complementary metal-oxide-semiconductor (CMOS) gates to capture the dependence of power consumption and current flows on input patterns and fan-in/fan-out conditions. Library elements are characterized once for all and their models are used during event-driven logic simulation to provide power information and construct time-domain current waveforms. We provide both global and local pattern-dependent estimates of power consumption and current peaks (with accuracy of 6 and 10% from SPICE, respectively), while keeping performance comparable with traditional gate-level simulation with unit delay. We use VERILOG-XL as simulation engine to grant compatibility with design tools based on Verilog HDL. A Web-based user interface allows our simulator (PPP) to be accessed through the Internet using a standard web browser.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000

The estimation of average-power dissipation of a circuit through exhaustive simulation is impractical due to the large number of primary inputs and their combinations. In this brief, two algorithms based on least square estimation are proposed for determining the average power dissipation in complementary metal-oxide-semiconductor (CMOS) circuits. Least square estimation converges faster by attempting to minimize the mean square error value during each iteration. Two statistical approaches namely, the sequential least square (SLS) estimation and the recursive least square estimation are investigated. The proposed methods are distribution independent in terms of the input samples, unbiased and point estimation based. Experimental results presented for the MCNC'91 and the ISCAS'89 benchmark circuits show that the least square estimation algorithms converge faster than other statistical techniques such as the Monte Carlo method [4] and the DIPE [8].

IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1998

In this paper, we present a probabilistic simulation technique to estimate the power consumption of a CMOS circuit under a general delay model. This technique is based on the notion of a tagged (probability) waveform, which models the set of all possible events at the output of each circuit node. Tagged waveforms are obtained by partitioning the logic waveform space of a circuit node according to the initial and final values of each logic waveform and compacting all logic waveforms in each partition by a single tagged waveform. To improve the efficiency of tagged probabilistic simulation, only tagged waveforms at the circuit inputs are exactly computed. The tagged waveforms of the remaining nodes are computed using a compositional scheme that propagates the tagged waveforms from circuit inputs to circuit outputs. We obtain significant speed up over explicit simulation methods with an average error of only 6%. This also represents a factor of 2-32 improvement in accuracy of power estimates over previous probabilistic simulation approaches.

Proceedings of the 1995 international symposium on Low power design - ISLPED '95, 1995

When estimating the dynamic power dissipated by a circuit dierent methods ranging from numeric analog simulation to event-driven logic simulation have been proposed. However, as the technology reaches the deep sub-micron range, additional eects as the short circuit current, partial voltage swings, transient behavior between clock cycles and leak current are b e c oming more r elevant to achieve an accurate estimation of the consumption. In this paper we present Meiga, an event-driven simulation-based p ower estimator that accounts for power dissipation due to short circuit current, partial swings and transient behavior. Experiments have shown that circuits in the order of several thousands of transistors are simulated i n s e c onds of CPU per input vector.

2011

New and complex systems are being implemented using highly advanced Electronic Design Automation (EDA) tools. As the complexity increases day by day, the dissipation of power has emerged as one of the very important design constraints. Now low power designs are not only used in small size applications like cell phones and handheld devices but also in highperformance computing applications. Embedded memories have been used extensively in modern SOC designs. In order to

2000

Abstract In this paper, we develop a novel technique based on Markov chains to accurately estimate power sensitivities to primary inputs in CMOS sequential circuits. A key application of power sensitivities is to construct a complicated power surface in the specification-space so as to easily obtain the power dissipation under any distribution of primary inputs, thereby offering an effective power macromodel for high-level power estimation.

IEEE Journal of Solid-State Circuits, 1994

Power consumption from logic circuits, interconnections, dock distribution, on chip memories, and off chip driving in CMOS VLSI is estimated. Estimation methods are demonstrated and verified. An estimate tool is created. Power consumption distribution between ~I I~I T O M~C~~O I W , clock distribution, logic gates, memories, and off chip driving are analyzed by examples. Comparisons are done between cell library, gate array, and full custom design. Also comparisons between static and dynamic logic are given. Results show that the power consumption of all interconnections and off chip driving can be up to 20% and 65% of the total power consumption respectively. Compared to cell library design, gate array designed chips consume about 10% more power, and power reduction in full custom designed chips could be 15%.

Very Large Scale Integration (VLSI) …, 2000

In this paper, we propose a modeling approach that captures the dependence of the power dissipation of a combinational logic circuit on its input/output signal switching statistics. The resulting power macromodel, consisting of a single four-dimensional table, can be used to estimate the power consumed in the circuit for any given input/output signal statistics. Given a low-level (typically gate-level) description of the circuit, we describe a characterization process by which such a table model can be automatically built. The four dimensions of our table-based model are the average input signal probability, average input transition density, average spatial correlation coefficient and average output zero-delay transition density. This approach has been implemented and models have been built for many benchmark circuits. Over a wide range of input signal statistics, we show that this model gives very good accuracy, with an RMS error of about 4% and average error of about 6%. Except for one out of about 10,000 cases, the largest error observed was under 20%. If one ignores the glitching activity, then the RMS error becomes under 1%, the average error becomes under 5% and the largest error observed in all cases is under 18%.

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010

Dynamic power consumption in CMOS circuits is usually estimated based on the number of signal transitions. However, when considering glitches, this is not accurate because narrow glitches consume less power than wide glitches. Glitch width and transition density modeling is further complicated by the effect of process variation. This paper presents a fast and accurate dynamic power estimation method that considers the detailed effect of process variation. First, we extend the probabilistic modeling approach to handle timing variations. Then the power consumption of a logic gate is computed based on the transition waveforms of its inputs. Both mean values and standard deviations of the dynamic power are estimated with high confidence based on accurate device characterization data. Compared with SPICE-based Monte Carlo simulations for small circuits, our power estimator reports power results within 3% error for the mean and 5% error for the standard deviation with six orders of magnitude speedup. For medium and large benchmarks, it is impossible to run Monte Carlo simulations with enough samples due to very long runtime, while our estimator can finish within minutes.

This paper introduces a new approach to pattern dependent static power estimation in logic blocks, which are realized 'on-the-fly' in a library-free design environment. A static current model is first developed at the transistor level and then extended to the logic gate level and finally the logic block level. For varying transistors widths and input stimuli, the transistor level model has performed with good accuracy compared to SPICE for technologies ranging from 65nm down to 32nm. The gate level model is pattern dependent and deals with basic gates and complex gates. A transistor collapsing scheme was developed to achieve simpler structure leading to analytical models with high computational efficiency and good accuracy ranging from 0.1-5.4% for basic logic gates and 3.7-6.2% for complex gates. Using these static current estimation models, a methodology has been introduced to estimate static power dissipation of logic blocks in a library-free design environment, in which the cells are generated and sized 'on-the-fly' driven by specification and targeted technology. Across several MCNC benchmarks, the estimation methodology proposed exhibits a worst case mean percentage error of 1.1% compared to SPICE. It also exhibits runtime that is on average 43 times faster than SPICE.

Design, Automation and Test in Europe, 2005

As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperature makes the thermal profile estimation of highperformance ICs a key issue to compute the total power dissipated in next-generations. In this paper we present accurate and compact analytical models to estimate the static power dissipation and the temperature of operation of CMOS gates. The models are the fundamentals of a performance estimation tool in which numerical procedures are avoided for any computation to set a faster estimation and optimization. The models developed are compared to measurements and SPICE simulations for a 0.12µm technology showing excellent results.

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2018

While state-of-the-art system-level simulators can deliver swift estimation of power dissipation for microprocessor designs, they do so at the expense of reduced accuracy. On the other hand, RTL simulators are typically cycle-accurate but overwhelmingly time consuming for real-life workloads. Consequently, the design community often has to make a compromise between accuracy and speed. In this work, we propose a novel cross-layer approach that can enable accurate power estimation by carefully integrating components from system-level and RTL simulation of the target design. We first leverage the concept of simulation points to transform the workload application and isolate its most critical segments. We then profile the highest weighted simulation point (HWSP) with a RTL simulator (AnyCore) for maximum accuracy, while the rest are simulated with a system-level simulator (gem5) for ensuring fast evaluation. Finally, we combine the integrated set of profiling data as input to the power simulator (McPAT). Our evaluation results for three different SPEC2006 benchmark applications demonstrate that our proposed crosslayer framework can improve the power estimation accuracy by up to 15% for individual simulation points and by ∼9% for the full application, compared to that of a conventional system-level simulation scheme.

Circuits and Systems, 2013

In this research, a fast methodology to calculate the exact value of the average dynamic power consumption for CMOS combinational logic circuits is developed. The delay model used is the unit-delay model where all gates have the same propagation delay. The main advantages of this method over other techniques are its accuracy, as it is deterministic and it requires less computational effort compared to exhaustive simulation approaches. The methodology uses the Logic Pictures concept for obtaining the nodes' toggle rates. The proposed method is applied to well-known circuits and the results are compared to exhaustive simulation and Monte Carlo simulation methods.

Increasing demand for portable electronics for computing and communication, as well as other applications, has necessitated longer battery life, lower weight, and lower power consumption. In order to satisfy these requirements, research activities focusing on low power/low voltage design techniques are underway. Since 'power' is now one of the design decision variables, the expanded design space required for low power has further increased the complexity of an already non-trivial task. Low power design basically involves two concomitant tasks: power estimation and analysis and power minimization. These tasks need to be carried out at each of the levels in the design hierarchy, namely, the behavioral, architectural, logic, circuit and physical levels. In this survey of the current state of the field, many of the salient power estimation and minimization techniques proposed for low power VLSI design are reviewed. In this paper comparison of power estimation of various basic CMOS cell structures on various technologies (TSMC 0.35um, TSMC 0.2um and TSMC 0.18um) is carried out. The research issues in order to make the low power design are also discussed in the paper. The paper is organized as follows: First, the sources of power dissipation in CMOS circuits and degrees of freedom in the low power design space are described in section-2. In section-3 various power minimization techniques are discussed. Designing of various CMOS cells and Simulation results are shown in section-4&5.Athe end of the paper conclusion is given. We have used IC Design studio, HEP2 module from Mentor Graphics to obtain the simulation for various analysis of power estimation.

2002

Static power dissipation due to leakage current in transistors constitutes an increasing fraction of the total power in modern semiconductor technologies. Current technology trends indicate that the leakage contribution will increase rapidly. Developing power efficient products will require consideration of static power in early phases of design development. Design houses that use RTL synthesis based flow for designing ASICs require a quick and reasonably accurate estimate of static power dissipation. This is important for making early packaging decisions and planning the power grid. Keeping this in view, we propose a simple model which enables estimation of static power early in the design phase. Our model is based on the experimental data obtained from simulations at the design level: ln P leak lib = S lib ln Cells + C lib , where S lib and C lib are the technology-dependent slope and intercept parameters of the model and "Cells" is the number of cells in the design. The model is validated for a large benchmark circuit and the leakage power predicted by our model is within 2% of the actual leakage power predicted by a popular tool used in the industry.