Advanced Specialized Processor Architecture for Samrtphones

Mobile application processors are soon to replace desktop processors as the focus of innovation in microprocessor technology. Already, these processors have largely caught up to their more power hungry cousins, supporting out-of order execution and multicore processing. In the near future, the exponentially worsening problem of dark silicon is going to be the primary force that dictates the evolution of these designs. We have argued that the natural evolution of mobile application processors is to use this dark silicon to create hundreds of automatically generated energy-saving cores are called conservation cores, which can reduce energy consumption by an order of magnitude. Conservation cores(C-cores) try to solve utilization wall and consequently Dark Silicon issues.Greendroid is a development library for the android platform. It is intended to make UI developments easier and consistent through your applications. This paper describes Greendroid, a research prototype that demonstrates the use of such cores to save energy broadly across the hotspots in the android mobile phone software stack.

Smartphones provides us the capability of a typical computer with absolute mobility and small form factor. But the hardware, software architecture of smartphone is significantly different from the conventional hardware and software architectures. The feature and architecture of the processors is totally different the traditional processor as these processors are developed to cope-up with fewer energy availability with smartphones or any other ultra portable devices.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014

The emergence of dark silicon-a fundamental design constraint absent in past generations-brings intriguing challenges and opportunities to microprocessor design. In this brief, we demonstrate the challenges of comparing competing design styles across different technology generations in a dark silicon era. We provide a new metric to guide a dark silicon aware (DSA) system design and propose a stochastic optimization algorithm for DSA multicore system design. Our technique shows 11%-58% and 5.7-5.8 times improvement in energy efficiency for forthcoming technology generations with two multicore design styles: cores with various voltage-frequency domains and cores with heterogeneous microarchitectures.

2016

In battery operated devices, such as mobile phones, power consumption is an important constraint, as it has a direct impact on the battery lifetime. Trying to extend the battery lifetime as much as possible has been one of the major targets in device development for the past years. Together with advances in the battery technology, several techniques, usually referred as low-power design techniques, have been developed in order to reduce the power consumption of circuits. In this Master Thesis, two optimizations that aim to reduce the power consumption has been proposed. This techniques has aimed the reduction of the power consumption caused by the memories. The first proposal has been to reduce the size of the main memory. This technique is based on the fact that smaller memories consume less power. This desired size reduction can be achieved by compressing the contents in the memory. More concretely, the program code stored in the main memory unit has been compresed to reduce the o...

2019

Embedded processors are key building blocks for IoT platforms. Such processors should provide flexible computing and low-power consumption for the small form factor devices to have better battery life. This paper introduces an implementation of a new design for a 32-bit RISC embedded processor optimized for lowpower budget and targeting IoT applications. The proposed processor is capable to execute a small set of simple instructions in few cycles, and hence, efficient for low-power embedded applications. The instruction set is inspired by the state-of-the-art Thumb-2 ISA by ARM. The performance of the processor is analyzed in terms of delay and power. The design is described in VHDL, implemented and simulated on Vivado and tested using Nexys 4 DDR board featuring Xilinx’s Artix-7 FPGA. Keywords—Embedded Processor, FPGA, IoT, Low-Power, MAC, Multiplier, Vedic, VHDL.

EAI Endorsed Transactions on Industrial Networks and Intelligent Systems, 2018

Power consumption in Complementary Metal Oxide Semiconductor (CMOS) technology has escalated to a point that only a fractional part of many-core chips can be powered-on at a time. Fortunately, this fraction can be increased at the expense of performance through the dark-silicon solution. However, with manycore integration set to be heading towards its thousands, power consumption and temperature increases per time, meaning the number of active nodes must be reduced drastically. Therefore, optimized techniques are demanded for continuous advancement in technology. Existing efforts try to overcome this challenge by activating nodes from different parts of the chip at the expense of communication latency. Other efforts on the other hand employ run-time power management techniques to manage the power performance of the cores trading-off performance for power. We found out that, for a significant amount of power to saved and high temperature to be avoided, focus should be on reducing the power consumption of all the on-chip components. Especially, the memory hierarchy and the interconnect. Power consumption can be minimized by, reducing the size of high leakage power dissipating elements, turning-off idle resources and integrating power saving materials.

2017

This thesis presents a novel approach to alleviating Dark Silicon problem by reducing power density. Decreasing the size of transistor has generated an increasing on power consumption. To attempt to manage the power issue, processor design has shifted from one single core to many cores. Switching on fewer cores while the others are off helps the chip to cool down and spread power more evenly over the chip. This means that some transistors are always idle while others are working. Therefore, scaling down the size of the chip, and increasing the amount of power to be dissipated, increases the number of inactive transistors. As a result it generates Dark Silicon, which doubles every chip generation [63] One of the most effective techniques to deal with Dark Silicon is to implement accelerators that execute the most energy consumer software functions. In this way the CPU is able to dissipate more energy and reduce the dark silicon issue. This work explores a novel accelerator design mod...

2014

Given the accelerated growth in tablet devices, smartphones, and netbooks, designers are faced with serious challenges to meet the needs of mobility in terms of battery life and form factor. It is vital to investigate how to deliver the best mobile experience to users while ensuring adequate levels of performance. In this paper, we present a power management evaluation of multi-core processor systems by comparing thermal power, battery life, and performance when running different types of workloads under a limited number of cores. To show the potential gains from a system power management perspective, we have assessed a mobile platform featuring the Second Generation Intel Core i5 processor, and tested it on a wide selection of workloads and benchmarks. Experimental results show significant thermal power reduction (up to 40 %) in a variety of scenarios, while system performance was sustained in most cases but sacrificed in a few other uncommon situations.

Smart phones provides us the capability of a typical computer with absolute mobility and small form factor. But the hardware architecture of smart phone is significantly different from the conventional hardware architectures. The feature and architecture of the processors is totally different the traditional processor as these processors are developed to cope-up with fewer energy availability with smart phones or any other ultra portable devices.

Energies

There are many real-world applications that require high-performance mobile computing systems for onboard, real-time processing of gathered data due to latency, reliability, security, or other application constraints. Unfortunately, most existing high-performance mobile computing systems require a prohibitively high power consumption in the face of the limited power available from the batteries typically used in these applications. For high-performance mobile computing to be practical, alternative hardware designs are needed to increase the computing performance while minimizing the required power consumption. This article surveys the state-of-the-art in high-efficiency, high-performance onboard mobile computing, focusing on the latest developments. It was found that more research is needed to design high-performance mobile computing systems while minimizing the required power consumption to meet the needs of these applications.

The Dark Side of Silicon, 2017

ACM Transactions on Embedded Computing Systems, 2014

As users become increasingly conscious of their energy footprint—either to improve battery life or to respect the environment—improved energy efficiency of systems has gained in importance. This is especially important in the context of information appliances such as e-book readers that are meant to replace books, since their energy efficiency impacts how long the appliance can be used on a single charge of the battery. In this article, we present a new software and hardware architecture for information appliances that provides significant advantages in terms of device lifetime. The architecture combines a low-power microcontroller with a high-performance application processor, where the low-power microcontroller is used to handle simple user interactions (e.g., turning pages, inking, entering text) without waking up the main application processor. We demonstrate how this architecture is easily adapted to the traditional way of building user interfaces using a user interface markup ...

2019

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.

With the explosion of portable electronic devices, power efficient processors have become increasingly important. In this paper we present a set of circuit techniques to implement a 32-bit low-power ARM processor, found commonly in embedded systems, using a six metal layer 0.18 m TSMC process. Our methodology is based on Clustered Voltage Scaling (CVS) and dual-V th techniques aiming to reduce both dynamic power and static power simultaneously.

International Journal of Interactive Mobile Technologies (iJIM)

Mobile devices are playing an important role in our daily lives. Nowadays, mobile devices are not only phones to call and text, but they are also smart devices that enable users to do almost any task that could be done on a regular PC. At the heart of the design of smartphones, there lies the processor to which almost all the development in the smartphone arena is attributed. Recently, ARM processors are among the most prominent processors used in mobile devices, smartphones, and embedded systems. This paper conducts an experimental comparative study of ARM 64-bit processors in terms of performance and their effect on power consumption, CPU temperature, and battery temperature. We use a number of well-known benchmarks to evaluate those characteristics of three smartphones, namely, Snapdragon 778G+, Exynos 1280 and HiSilicon Kirin 980. Those smartphones are all equipped with ARM 64-bit processors. Our results reveal that none of the three-selected smartphones was the best in all ch...