A Degree-Based Clustering Technique for VLSI Placement
Laleh Behjat2009, Journal of Algorithms & Computational Technology
Sign up for access to the world's latest research
checkGet notified about relevant papers
checkSave papers to use in your research
checkJoin the discussion with peers
checkTrack your impact
Abstract
In this paper, clustering for the circuit placement problem is examined from the perspective of wire length contribution from groups of nets. First, the final wire length data of groups of nets with different degrees are extracted and studied. It is illustrated that nets with high-degree contribute a high percentage to the total wire length. To remedy this problem, a clustering algorithm for placement is proposed that focuses on clustering nets with high-degree. This new clustering algorithm is implemented as a preprocessing step in the placement stage. ICCAD04 benchmark circuits abstracted from IBM are used to validate the placement quality by using four academic placers with and without the proposed preprocessing step. Experiments show that the overall placement results can be improved by up to 5%.
Related papers
Perimeter Degree Technique for the Reduction of Routing Congestion during Placement in Physical Design of VLSI Circuits
Complexity
When used in conjunction with the current floorplan and the optimization technique in circuit design engineering, this research allows for the evaluation of design parameters that can be used to reduce congestion during integrated circuit fabrication. Testing the multiple alternative consequences of IC design will be extremely beneficial in this situation, as will be demonstrated further below. If the importance of placement and routing congestion concerns is underappreciated, the IC implementation may experience significant nonlinear problems throughout the process as a result of the underappreciation of placement and routing congestion concerns. The use of standard optimization techniques in integrated circuit design is not the most effective strategy when it comes to precisely estimating nonlinear aspects in the design of integrated circuits. To this end, advanced tools such as Xilinx VIVADO and the ICC2 have been developed, in addition to the ICC1 and VIRTUOSO, to explore for co...
Effective Clustering Algorithms for VLSI Circuit
Contemporary Engineering Sciences, 2014
In this article, the effective circuit partitioning techniques are employed by using the clustering algorithms.The technique uses the circuit netlist in order to cluster the circuit in partitioning steps and it also minimizes the interconnection distance with the required iteration level .The clustering algorithm like K-Mean, Y-Mean,K-Medoid are performed on the standard benchmark circuits.The results obtained shows that the proposed techniques improves the time and also minimize the area by reducing the interconnection distance.
An analytic net weighting approach for performance optimization in circuit placement
We propose an efficient circuit placement approach based on analytic net weighting controls for nonlinear performance constraints. We justify the popular net weighting heuristic by first showing that an appropriate net weighting is a natural result of the Kuhn-Tucker conditions of circuit placement optimization subject to the performance constraints. We further give a quantitative analysis of the effect of net weighting to wire length change. An effective net weighting control algorithm has been implemented and applied to real chip designs. The results are very promising. A performance-optimized result can be achieved in 13.2 seconds for a chip with 1,403 circuits. An experimental CMOS chip with 45,296 circuits has a complete placement result in 40 minutes while the wire length measure is 20.3 percent better than a simulated annealing approach.
Progress and Challenges in VLSI Placement Research
2012
ABSTRACT Given the significance of placement in IC physical design, extensive research studies performed over the last 50 years addressed numerous aspects of global and detailed placement. The objectives and the constraints dominant in placement have been revised many times over, and continue to evolve. Additionally, the increasing scale of placement instances affects the algorithms of choice for high-performance tools.
Partitioning-based Methods for VLSI Placement
2008
The technique of using balanced min-cut partitioning in placement was presented by Breuer in 1977 [7]. Such min-cut placers use scalable and extensible divide-and-conquer algorithmic framework and tend to produce routable placements [9]. Recent work offers extensions to block placement and large-scale mixed-size placement [15, 18, 31], and robust incremental placement [33].
GPSAT: A SAT based Global Placement for Large Scale Mixed-size Designs
2018 International Conference on Intelligent Autonomous Systems (ICoIAS), 2018
In this paper, a novel Boolean SAT based wirelength-driven global placement technique has been presented. Among the three conventional steps (global placement, legalization and detailed placement) for complete placement of VLSI circuits, we have done up to global placement. Global placement is the basis of other two phases in placement. Hence, importance of global placement is very high in the row of placement problem.To achieve good placement solutions, a new hierarchical cluster- ing technique has been introduced to divide the set of circuit components into clusters in order to reduce the complexity of the global placement problem based on fixed circuit blocks and their connections with other movable blocks. An area partitioning method is proposed to divide the placement area into hierarchical regions which helps to find wirelength-driven global placement for the circuit components considering pin offsets and pin directions using SAT. Different components of a given circuit are pl...
Towards Optimal Circuit Layout Using Advanced Search Techniques
1995
A VLSI chip can today contain millions of transistors and is expected to contain more than 100 million transistors in the next decade. This tremendous growth is made possible by the development of sophisticated design tools and software. To deal with the complexity of millions of components and to achieve a turn around time in terms of a couple of months, VLSI design tools must not only be computationally fast but also generate layouts close to optimal. The work in this thesis involves exploring algorithmic solutions to the problem of circuit layout in VLSI design. The exploration is an attempt to evaluate, design, improve and integrate the best combinatorial algorithms to solve the circuit layout problem. Advanced search heuristic techniques in the form of Tabu Search, GRASP and Genetic Algorithms are used extensively to solve most of the problems in circuit layout. We show in this thesis that new hybrid partitioning techniques based on the above mentioned heuristics outperform traditional heuristic methods. In fact, these novel approaches consistently find better solutions than other methods in a fraction of the time. A new placement algorithm that is suitable for standard cell layout is also presented. The initial placement is obtained using the partitioning algorithm. An efficient clustering based algorithm is developed to further reduce the complexity of circuit partitioning and placement and improve the performance of the design process in terms of quality and computation time. Finally, parallel implementations of the developed heuristics on a network of workstations are presented and significant speedups are reported. The ability of the hybrid heuristics to find near optimal solutions is assessed by comparing their performance with a general purpose mixed integer programming package. Experimental results indicate that our heuristics based on clustering and hybridization schemes give very good results and are suitable for VLSI circuits. v xv C.4 GRASP 2-Way partitioning .
Pre-layout physical connectivity prediction with application in clustering-based placement
2005 International Conference on Computer Design, 2005
In this paper, we introduce a structural metric, logic contraction, for pre-layout physical connectivity prediction. For a given set of nodes forming a cluster in a netlist, we can predict their proximity in the final layout. We demonstrate experimentally a very good correlation of our pre-layout measure with the post layout physical distances between those nodes. We show an application of the logic contraction to circuit clustering. We compare our Seed-Growth clustering algorithm with the existing efficient clustering techniques such as Edge-Coarsening [1][12], First-Choice [13] and Peak-Clustering . We apply our clustering technique to speed up a placement tool and sketch out our ideas on how to use it in technology mapping. Experimental results demonstrate the effectiveness of our new clustering method.
Optimization of an Integrated Circuit Placement Algorithm in a Parallel Environment
This paper presents an implementation of GORDIAN [1], a method for Global Placement of standard-cell based circuit designs, incorporating a number of algorithmic optimizations and parallelization in order to reduce the total runtime and memory requirements and improve the solution quality. Experimental results are presented, comparing GODRIAN to other state-of-the-art academic placers, which highlight the improved execution speed and the limited memory footprint which are GORDIAN’s main advantages. Thus, GORDIAN runs faster than any other proven placer while still producing acceptable results, enabling million-cell designs to be placed within a few minutes.
Ca & Sbo : A Novel Optimized Placement Algorithms for an Efficient Vlsi Design
Designing a simplest architecture involves appropriate placement, which is often, regarded as a critical concerns of physical design engineers. Placement and routing of chips in automated manner is been research since decades and provides better predictive performance than manual procedures. However, most of the automated models operating under meta-heuristic optimization fails in obtaining optimal solution due to premature convergence and non-optimal placement of solutions. In this paper, we develop a novel meta-heuristic optimization method namely Cellular Automata (CA) and Satin Bowerbird Optimization (SBO) that combines Primal-dual lagrangian technique (SimPL) and Complex Primal dual lagrangian (ComPL) for attaining optimal placement and routing of chips. The process of CA and SBO optimization approach operates on obtaining optimized placement solutions from the SimPL and ComPL solutions. The combination of CA-SimPL, SBO-SimPL, CA-ComPL and SBO-ComPL is implemented on electronic...
Related papers
Net Cluster: A Net-Reduction-Based Clustering Preprocessing Algorithm for Partitioning and Placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000
The complexity and size of digital circuits have grown exponentially, and today's circuits can contain millions of logic elements. Clustering algorithms have become popular due to their ability to reduce circuit sizes, so that the circuit layout can be performed faster and with higher quality. This paper presents a deterministic net-reduction-based clustering algorithm called Net Cluster. The basic idea of the proposed technique is to put the emphasis on reducing the number of nets versus the number of cells, thereby capturing the natural clusters of a circuit. The proposed algorithm has proven a linear-time complexity of O(p), where p is the number of pins in a circuit. To demonstrate the effectiveness of the proposed clustering technique, it has been applied to multilevel partitioning and wire length-driven placement.
Multi-Clustering Net Model for Placement Algorithms
IFIP International Conference …, 2008
Current placement algorithms aim at routable layouts with shortest wirelength and mostly minimize the total Half-Perimeter Wirelength (HPWL) of nets. A new clustering net model is proposed for better handling of high degree hyperedges, for which the HPWL can significantly underestimate wirelength. Splitting a net into several lower degree subnets, the total HPWL of the subnets estimates wirelength significantly better than HPWL of the original net. An efficient clustering approach is proposed with complexity linear on the number of pins. The final Steiner tree wirelength is improved with no or little penalty in runtime by transforming the circuit netlist between global and detailed placement stages accordingly to the new net model. The reduction in the wirelength also leads to shorter delays of circuits.
Optimality and Scalability Study of Existing Placement Algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2004
Placement is an important step in the overall IC design process in DSM technologies, as it defines the on-chip interconnects, which have become the bottleneck in determining circuit performance. The rapidly increasing design complexity, combined with the demand for the capability of handling nearly flattened designs for physical hierarchy generation, poses significant challenges to existing placement algorithms. There are very few studies on understanding the optimality and scalability of placement algorithms, due to the limited sizes of existing benchmarks and limited knowledge of optimal solutions. The contribution of this paper includes two parts: 1) We implemented an algorithm for generating synthetic benchmarks that have known optimal wirelengths and can match any given net distribution vector. 2) Using benchmarks of 10K to 2M placeable modules with known optimal solutions, we studied the optimality and scalability of three state-of-the-art placers, Dragon [4], Capo [1], mPL [24] from academia, and one leading edge industrial placer, QPlace [5] from Cadence. For the first time our study reveals the gap between the results produced by these tools versus true optimal solutions. The wirelengths produced by these tools are 1.66 to 2.53 times the optimal in the worst cases, and are 1.46 to 2.38 times the optimal on the average. As for scalability, the average solution quality of each tool deteriorates by an additional 4% to 25% when the problem size increases by a factor of 10. These results indicate significant room for improvement in existing placement algorithms.
On the superiority of modularity-based clustering for determining placement-relevant clusters
Integration, 2020
In advanced technology nodes, IC implementation faces increasing design complexity as well as ever-more demanding design schedule requirements. This raises the need for new decomposition approaches that can help reduce problem complexity, in conjunction with new predictive methodologies that can help avoid bottlenecks and loops in the physical implementation flow. Notably, with modern design methodologies it would be very valuable to better predict final placement of the gate-level netlist: this would enable more accurate early assessment of performance, congestion and floorplan viability in the SOC floorplanning/RTL planning stages of design. In this work, we study a new criterion for the classic challenge of VLSI netlist clustering: how well netlist clusters "stay together" through final implementation. We propose the use of several evaluators of this criterion. We also explore the use of modularity-driven clustering to identify natural clusters in a given graph without the tuning of parameters and size balance constraints typically required by VLSI CAD partitioning methods. We find that the netlist hypergraph-to-graph mapping can significantly affect quality of results, and we experimentally identify an effective recipe for weighting that also comprehends topological proximity to I/Os. Further, we empirically demonstrate that modularity-based clustering achieves better correlation to actual netlist placements than traditional VLSI CAD methods (our method is also 2× faster than use of hMetis for our largest testcases). Finally, we propose a flow with fast "blob placement" of clusters. The "blob placement" is used as a seed for a global placement tool that performs placement of the flat netlist. With this flow we achieve 20% speedup on the placement of a netlist with 4.9 M instances with less than 3% difference in routed wirelength.
Guided local search for final placement in VLSI design
Journal of Heuristics, 2003
A new heuristic is presented for the general cell placement problem where the objective is to minimize total bounding box netlength. The heuristic is based on the Guided Local Search (GLS) metaheuristic. GLS modifies the objective function in a constructive way to escape local minima. Previous attempts to use local search on final (or detailed) placement problems have often failed as the neighborhood quickly becomes too excessive for large circuits. Nevertheless, by combining GLS with Fast Local Search it is possible to focus the search on appropriate sub-neighborhoods, thus reducing the time complexity considerably.
Wire length prediction based clustering and its application in placement
2003
In this paper we introduce a metric to evaluate proximity of connected elements in a netlist. Compared to connectivity [8] and edge separability [4], our metric is capable of predicting short connections more accurately. We show that the proposed metric can also predict relative wire length in multi-pin nets. We develop a finegranularity clustering algorithm based on the new metric and embed it into the Fast Placer Implementation (FPI) framework . Experimental results show that the new clustering algorithm produces better global placement results than the net absorption [10] algorithm, connectivity [8], and edge separability [4] based algorithms. With the new clustering algorithm, FPI achieves up to 50% speedup compared to the latest version of Capo8.5 [19], without placement quality losses.
A connectivity based clustering algorithm with application to VLSI circuit partitioning
IEEE Transactions on Circuits and Systems Ii-express Briefs, 2006
Circuit partitioning is a fundamental problem in very large-scale integration (VLSI) physical design automation. In this brief, we present a new connectivity-based clustering algorithm for VLSI circuit partitioning. The proposed clustering method focuses on capturing natural clusters in a circuit, i.e., the groups of cells that are highly interconnected in a circuit. Therefore, the proposed clustering method can reduce the
Large-scale circuit placement
ACM Transactions on Design Automation of Electronic Systems, 2005
Placement is one of the most important steps in the RTL-to-GDSII synthesis process, as it directly defines the interconnects, which have become the bottleneck in circuit and system performance in deep submicron technologies. The placement problem has been studied extensively in the past 30 years. However, recent studies show that existing placement solutions are surprisingly far from optimal. The first part of this tutorial summarizes results from recent optimality and scalability studies of existing placement tools. These studies show that the results of leading placement tools from both industry and academia may be up to 50% to 150% away from optimal in total wirelength. If such a gap can be closed, the corresponding performance improvement will be equivalent to several technology-generation advancements. The second part of the tutorial highlights the recent progress on large-scale circuit placement, including techniques for wirelength minimization, routability optimization, and p...
An enhanced multilevel algorithm for circuit placement
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486), 2003
This paper presents several important enhancements to the recently published multilevel placement package mPL [12]. The improvements include (i) unconstrained quadratic relaxation on small, noncontiguous subproblems at every level of the hierarchy; (ii) improved interpolation (declustering) based on techniques from algebraic multigrid (AMG), and (iii) iterated V-cycles with additional geometric information for aggregation in subsequent V-cycles. The enhanced version of mPL, named mPL2, improves the total wirelength result by about 12% compared to the original version. The attractive scalability properties of the mPL run time have been largely retained, and the overall run time remains very competitive. Compared to gordian-l-domino [25] on uniformcell-size IBM/ISPD98 benchmarks, a speed-up of well over 8× on large circuits (≥ 100, 000 cells or nets) is obtained along with an average improvement in total wirelength of about 2%. Compared to Dragon [32] on the same benchmarks, a speed-up of about 5× is obtained at the cost of about 4% increased wirelength. On the recently published PEKO synthetic benchmarks, mPL2 generates surprisingly high-quality placements-roughly 60% closer to the optimal than those produced by Capo 8.5 and Dragon-in run time about twice as long as Capo's and about 1/10th of Dragon's.
Improving min-cut placement for VLSI using analytical techniques
2003
ABSTRACT Over the past few decades, several powerful placement algorithms have been used successfully in performing VLSI placement. With the increasing complexity of the VLSI chips, there is no clear dominant placement paradigm today. This work attempts to explore hybrid algorithms for large-scale VLSI placement. Our work aims to evaluate existing placement algorithms, estimate the ease of their reuse, and identify their sensitivities and limitations.
Loading Preview
Sorry, preview is currently unavailable. You can download the paper by clicking the button above.