Parallel fault backtracing for calculation of fault coverage

The paper presents a novel view on the Structurally Synthesized BDDs (SSBDD) as a model with inherent double topology for compact modeling of single faults and efficient reasoning of multiple faults. The nodes of SSBDDs represent lower level signal path topology in the original circuit, and the paths of SSBDD represent higher level topology of conditions to be processed during fault reasoning. The double topological view on SSBDDs allows to give easy explanation of the limitations of existing methods of multiple fault testing, and shows the ways how to avoid fault masking. A generalization of the test pair approach in a form of the concept of test groups is introduced for testing multiple faults.

1998

Abstract We present a fast, dynamic fault coverage estimation technique for sequential circuits that achieves high degrees of accuracy by significantly reducing the number of injected faults and faulty-event evaluations. Specficdy, we dynamically reduce injection of two types of faults:(1) hyperactive faults that never get detected, and (2) faults whose effects never propagate to a flip-flop or primary output. The cost of fault simulation is greatly reduced as injection of most of these two types of faults is prevented.

IEEE Design & Test of Computers, 2000

T here are three general methods for fault simulation: parallel, deductive, Critical path tracing and concurrent. Several other, specialized methods deal only with comdetermines fault detection binational circuits. l4 The widespread use of design for testability techniques, without explict .fault such as level-sensitive scan design, or LSSD, 5 that transform a sequential cirwimulathou. It appexplicitobea cuit into a combinational one for testing purposes, has lent increasing imporsimulation. It appears to be a tance to specialized methods for combinational circuits. Even for combinamore efficient alternative to tional circuits, the time spent in fault simulation alone is proportional to the conventional methods. square of the number of gates in the circuit.6 This problem becomes more acute in VLSI circuits. Clearly, more efficient methods for test evaluation and test generation are required. Critical path tracing is a more efficient alternative to fault simulation. It consists of simulating the fault-free cicuit (true-value simulation) and using the computed signal values for tracing paths from primary outputs, or POs, towards primary inputs, or PIs, to determine the detected faults. Compared with conventional fault simulation, the distinctive features of this technique are as follows: * It directly identifies the faults detected by a test, without simulating the set of all possible faults. Hence, it avoids all the work involved in propagating the effects of the faults that are not detected by a test. * It deals with faults only implicity. Therefore, we no longer need fault enumeration, fault collapsing, fault partitioning (for multipass simulation), fault insertion, or fault dropping. * It is based on a path-tracing algorithm that does not require computing values in the faulty circuits by gate evaluations or fault list processing. * It is an approximate method. However, the approximation occurs seldom and consists in not marking as detected some faults that are actually detected by the evaluated test. Critical path tracing can be extended to synchronous sequential circuits using an iterative array model.7 However, this discussion is confined to combinational circuits. Main concepts Wang8 defines the concept of a critial value as follows. Definition 1: A line / has a critical value v in the test (vector) t if t detects the fault / s-a-v. A line with a critical value in t is said to be critical in t. (Note that unlike the D notation of the D-Algorithm, a critical value always indicates the detection of a fault.) An earlier version of this article appeared in the ACM/IEEE 20th Design Automation Clearly, the POs are critical in any test. Our test evaluation method consists Conernc Pocedng, un 183 of determining paths of critical lines, called critical paths, by a backtracing

Proceedings. XI Brazilian Symposium on Integrated Circuit Design (Cat. No.98EX216), 1998

We propose a new approach to generate diagnostic tests and localize single gate design errors in combinational circuits. The method is based on using the stuck-at fault model with subsequent translation of the diagnosis into the design error area. This allows to exploit standard gate-level ATPGs for verification and design error diagnosis purposes. A powerful hierarchical approach is proposed for generating test patterns which, at first, localize the faulty macro (tree-like subcircuit), and then localize the erroneous gate in the faulty macro. Experimental data show the efficiency of the macro-level test generation and fault simulation compared to the plain gate-level approaches.

A method is presented for deterministic test pattern generation using a uniform functional fault model for combinational circuits. The fault model allows to represent the physical defects in components and defects in the communication network of components by the same technique. Physical defects are modeled as parameters in generic Boolean differential equations. Solutions of these equations give the conditions at which defects are locally activated. The defect activation conditions are used as functional fault models for logic level test generation purposes. A method is proposed which allows to find the types of faults that may occur in a real circuit and to determine their probabilities. A defect-oriented deterministic test generation tool was developed, and the experimental data obtained by the tool for ISCAS'85 benchmarks are presented. It was shown that for the majority of cases 100% stuck-at fault tests do not cover 100% of the physical defects. The main feature of the new...

IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1996

HOPE is an efficient parallel fault simulator for synchronous sequential circuits that employs the parallel version of the single fault propagation technique. HOPE is based on an earlier fault simulator called PROOFS, which employs several heuristics to efficiently drop faults and to avoid simulation of many inactive faults. In this paper, we propose three new techniques that substantially speed up parallel fault simulation: 1) reduction of faults simulated in parallel through mapping nonstem faults to stem faults, 2) a new fault injection method called functional fault injection, and 3) a combination of a static fault ordering method and a dynamic fault ordering method. Based on our experiments, our fault simulator, HOPE, which incorporates the proposed techniques, is about 1.6 times faster than PROOFS for 16 benchmark circuits.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1994

Abstruct-A method to estimate the coverage of path delay faults of a given test set, without enumerating paths, is proposed. The method is polynomial in the number of lines in the circuit, and thus allows circuits with large numbers of paths to be considered under the path delay fault model. Several levels of approximation, with increasing accuracy and increasing polynomial complexity, are proposed. Experimental results are presented to show the effectiveness and accuracy of the estimate in evaluating the path delay fault coverage. Combining this non-enumerative estimation method with a test generation method for path delay faults would yield a cost effective method to consider path delay faults in large circuits, which are beyond the capabilities of existing test generation and fault simulation procedures, that are based on enumeration of paths.

Information Sciences, 1986

The present paper describes some algorithms for generating complete test sets for bridging faults in combinational logic circuits. It is shown how the concept of Boolean difference, which is well understood in the case of stuck-type fault situations, can be employed to generate the complete test set for bridging faults in combinational networks. The cases of single bridging fault and multiple input bridging fault are dealt with. An algorithm is also described for generating the complete test set of a combinational logic circuit in which a single stuck-type fault occurs in the presence of a bridging fault.

Microelectronics Reliability, 1997

This paper presents a new method for fault modelling of MOS combinational circuits at the transistor level. Every transistor is replaced with a conductance controlled by the gate logic value. The specific advantage of the method is use of a symbolic simulator for circuit function extraction. This function is referred as Transistor Logic Conductance Function (TLCF). Starting from a known TLCF, a simple set of rules is used for output state determination. The method is suitable for multiple fault model generation thanks to the fact that only one symbolic analysis of a circuit is sufficient for modelling different stuck-open, stuck-short and stuck-at faults of a logic gate, Moreover, the method can deal also with bridging and cut faults.

2012

Abstract—FALCON (FAst fauLt COverage estimatioN) is a scalable method for fault grading which uses local fault simulations to estimate the fault coverage of a large system. The generality of this method makes it applicable for any modular design. Our analysis shows that the run time of our algorithm is related to the number of gates and the number of IOs in a module, while fault simulation run time is related to the total number of gates in the system. We have measured fault coverage for OR1200 and IVM processors and compared the results with fault simulation performed by a commercial tool. We have also compared our results with fault sampling. Our results show that for large designs FALCON works faster (one order of magnitude) compared to fault simulation. It also has smaller error rate compared to fault sampling when the size of design under test grows. I.

Computers & Mathematics with Applications, 1993

2003

Reducing test data size is one of the major challenges in testing systems-on-a-chip. This can be achieved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of compaction and compression techniques. In this paper, we propose a novel and efficient test relaxation technique for combinational circuits. It is based on critical path tracing and hence it may result in a reduction in the fault coverage. However, based on experimental results on ISCAS benchmark circuits, the drop in the fault coverage (if any) after relaxation is small for most of the circuits. The technique is faster than the brute-force test relaxation method by several orders of magnitude.

In this paper we introduce a spectral method of register transfer level (RTL) test generation for sequential circuits. We define RTL faults as stuck-at faults on all primary inputs, primary outputs, and flip-flop terminals. Test vectors generated to cover the RTL faults are analyzed using Hadamard matrices. The analysis determines the amplitudes of prominent Walsh functions and the random noise level for each primary input. That information is then used to generate vectors for any gate-level implementation. At the gate-level, a fault simulator and an integer linear program (ILP) are used to compact the test sequence. We give results for three ITC'99 and four ISCAS'89 benchmark circuits. Each ITC'99 circuit was synthesized two ways, separately for area and delay optimization. The RTL spectral vectors performed equally well on both implementations. When compared to a gatelevel ATPG, the coverages of RTL vectors were similar and in many cases RTL vectors produced equal or higher coverage in shorter CPU time.

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), 2010

In this paper, a new very fast fault simulation method to handle the X-fault model is proposed. The method is based on a two-phase procedure. In the first phase, a parallel exact critical path fault tracing is used to determine all the detected stuck-at faults in the circuit, and in the second phase a postprocess is launched which will determine the detectability of X-faults.

Proceedings., International Test Conference, 1994

The paper assesses the effectiveness of the Circular Self-Test Path BIST technique from an experimental point of view and proposes an algorithm to overcome the low fault coverage that often arises when real circuits are examined. Several fault simulation experiments have been performed on the ISCAS89 benchmark set, as well as on a set of industrial circuits: in contrast to the theoretical analysis proposed in [PKKa92], a very high Fault Coverage is attained with a limited number of clock cycles, but this happens only when the circuit does not enter a loop. This danger can not be avoided even if clever strategies for Flip-Flops ordering, aimed at reducing the functional adjacency, are adopted. Instead, we suggest that loops can be avoided and fault coverage increased by carefully choosing the initial state, and we present an approach based on Binary Decision Diagrams and Symbolic Techniques to solve the problem.