Lab Report

This paper deals with the testable design of conservative logic based sequential circuits by using two test vectors. The conservative logic based sequential circuits are built from the reversible gates. ThisReversible or information lossless circuits have extensive applications in quantum computing, optical computing, as well as ultra-low power VLSI circuits.Theoptimized designs of reversible D Latch,Reversible negative enable D latch,Master slave Flip-Flop,Double edge triggered Flip-Flops and its application circuits like reversible universal shift registers, four bit binary counter are proposed.This proposed design can identify any stuck-at-fault in the circuits and this proposed circuit is efficient than the conventional circuit designed using classical gate in terms of number of gate count,delay in the circuit,garbageoutput, power dissipation and testability.Thisproposeddesign canidentify any stuck-at-fault in the circuits.

2015 4th International Conference on Reliability, Infocom Technologies and Optimization (ICRITO) (Trends and Future Directions), 2015

There is vast variation encountered in present circuits because of aggressive scaling and process imperfections. So this paper deals with various D flip-flop circuits in terms of robustness and propagation delay. This work compares various known D flip-flop circuits and then identifies the circuit which is fastest as compared to others taken into consideration. Further, delay variability exhibited by circuits has been analyzed to test the immunity against PVT variations i.e. process, voltage and temperature. In this paper, we have investigated the output levels of various D flip-flop circuits. Push-pull isolation D flip-flop proves to be more efficient as compared to other circuits in terms of delay variability. The circuits have been simulated using 32nm technology node on SPICE. The designs offering minimum delay and its variability are reported, to aid the designer in selecting the best design depending on specific requirements.

2014

Reversible logic circuit is receiving attention of researchers for low power design. Flip Flop is the basic element for the sequential circuits, most of the part of the IC is built from sequential circuit, and hence it is needed to design low power flip-flop. The work is done on designing a reversible Dflip flop from a reversible Fredkin gate using GDI technique in 0.180um TSMC process, which can be used for low power design, and fault preventing circuit.

This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH without affecting the outputs as long as the data setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.

International Journal of Innovative Research in Computer and Communication Engineering, 2015

The field of digital electronics has been directly towards to the low power digital system. The use of very large scale integration technology in high performance computing, wireless communication, consumer electronics has been rising at a very fast rate. The challenge for VLSI technology is growing in leakage power consumption. Wide utilizations of memory storage systems in modern electronics triggers a demand for high performance and low area implementation of basic memory component and one of the most state holding element is D Flip Flop. In this paper analysis of power, delay, area and power delay product is done for D flip flop using different technologies like static CMOS, C 2 MOS, POWER PC, GDI MUX, TSPC, etc. Low power Flip flops are useful for the design of low power digital system. The analysis and the comparison is done using TANNER EDA Tool at 130nm Technology.

This paper presents an efficient explicit pulsed static dual edge triggered flip flop with an improved performance. The proposed design overcomes the drawbacks of the dynamic logic family and uses explicit clock pulse generator approach to achieve dual edge triggering. The proposed flip-flop is compared with existing explicit pulsed dual edge triggered flip-flops. Based on the simulation results overall improvements of 7.45%, 13.68% and 20.03% are observed in delay, power consumption and power delay product respectively.

Microprocessors and Microsystems, 2018

Quantum Dot Cellular Automata (QCA) provides a new structure for designing digital circuits with smaller size and less power consumption. This technology is a new method to implement digital circuits in the future. This paper presents a new rising edge triggered D flip-flop structure with reset capability. Simulation of the circuit in QCADesigner software confirms the correct operation of the circuit. Finally, several common structures without reset ability are compared with the proposed structure and the results are indicated in the comparison table. The designed D flip-flop uses 95 cells for implementation and will function properly in one period of time.

In cmos design goals ,cmos technology provides better results than TTL(Transistor Transistor Logic).but today due to increasing prominence of portable systems ,speed and low power designs are major issues in high performance digital systems .flip-flops are basic storage elements used in all kind of digital systems. Flip flops are widely used in memory elements, counters and registers also. And these circuits are used to implementation of vlsi chips. So power consumption is the major concern in this which should be improved. This paper proposes a a Design of single edge triggered low power d Flip Flop using GDI(Gate Diffusion Input Technique).As a result using GDI power consumption is Reduced and features the best power delay product. The operation of the D flip flop is analyzed and simulated using Tanner EDA .

IEEE Journal of Solid-State Circuits, 1990

CMOS implementation of a D-type double-edgetriggered flip-flop (DET-FF) is presented. A DET-FF changes its state at both the positive and the negative clock edge transitions. It has advantages with respect to both system speed and power dissipation. The design presented requires little overhead in circuit complexity. This CMOS D-type DET-FF is capable of operating at more than 50 MHz, which gives an equivalent system frequency of 100 MHz.

This paper enumerates new architecture of low power dual-edge triggered Flip-Flop (DETFF) designed at 180nm CMOS technology. In DETFF same data throughput can be achieved with half of the clock frequency as compared to single edge triggered Flip-Flop (SETFF). In this paper conventional and proposed DETFF are presented and compared at same simulation conditions. The post layout experimental results comparison shows that the average power dissipation is improved by 48. 17%, 41.29% and 36.84% when compared with SCDFF, DEPFF and SEDNIFF respectively and improvement in PDP is 42.44%, 33.88% and 24.69% as compared to SCDFF, DEPFF and SEDNIFF respectively. Therefore the proposed DETFF design is suitable for low power and small area applications.

International Journal of Electrical and Computer Engineering (IJECE), 2013

This paper enumerates new architecture of low power dual-edge triggered Flip-Flop (DETFF) designed at 180nm CMOS technology. In DETFF same data throughput can be achieved with half of the clock frequency as compared to single edge triggered Flip-Flop (SETFF). In this paper conventional and proposed DETFF are presented and compared at same simulation conditions. The post layout experimental results comparison shows that the average power dissipation is improved by 48.17%, 41.29% and 36.84% when compared with SCDFF, DEPFF and SEDNIFF respectively and improvement in PDP is 42.44%, 33.88% and 24.69% as compared to SCDFF, DEPFF and SEDNIFF respectively. Therefore the proposed DETFF design is suitable for low power and small area applications.

2015

This is to certify that the work in the thesis entitled "A novel design of low power and high speed dual edge triggered flip-flop" by Chandan Maurya is a record of an original research work carried out by him during 2014 -2015 under my supervision and guidance in partial fulfilment of the requirements for the award of the degree of Master of Technology in Electronics and Communication Engineering (VLSI Design & Embedded System), National Institute of Technology, Rourkela. Neither this thesis nor any part of it, to the best of my knowledge, has been submitted for any degree or diploma elsewhere.

2009

In this paper, a single edge-triggered, static D flip-flop design suitable, for low power and low area requirements is proposed. Advantageously, the flip-flop is realized using only ten transistors. The flip-flop is implemented using Master-Slave configuration and can be used for lower cost memory and microprocessor chips. The 0.6-micron technology is used to implement the design and the area and power results were compared with existing SET D FFs. Simulation results indicated that the circuit is capable of significant power savings.

This Paper explains the performance analysis of D-Flip Flop using three different techniques. They are D-Flip Flop using CMOS technology, Gate-Diffusion-Input(GDI) and DSTC technique. D flip-flop has been designed and layout simulated using 45nm technology in the first technique. The Gate diffusion technique is utilized directly following exploring different flip flop circuits since it is found to give the most minimal power delay when contrasted with other CMOS designs. The dynamic single-transistor-clocked (DSTC) flip-flop that experiences significant voltage drop at the result due to the capacitive coupling impact between the common node of the slave latch and the drifting result driving node of the master latch. The performance has been Analysed in terms of power dissipation and Propagation delay.

A Delay (D) flip-flop is an edge triggering device. A high speed, low power consumption, positive edge triggered conventional Delay (D) flip-flop can be designed for increasing the speed of counter in Phase locked loop, using 32nm CMOS technology. The conventional D flip-flop has higher operating frequencies but it features static power dissipation. The designed counter can be used in the divider chip of the phase locked loop. A divide counter is required in the feedback loop to increase the VCO frequency above the input reference frequency. The propose circuit will be faster than conventional circuit as it will be a fast reset operation. The circuit will be consuming less power as it prevents short circuit power consumption. The circuit operates at low voltage power supply.