Inverter Based Gain-Boosting Fully Differential Cmos Amplifier

IEEE Transactions on Circuits and Systems I: Regular Papers, 2011

A two-stage fully differential CMOS amplifier comprising inverters as input structures and employing self-biasing techniques is presented. The proposed amplifier benefits from an optimum compensation through time-domain optimization which permits achieving high energy efficiency. Moreover, it achieves the highest efficiency of its class and although it relies on a quasi-class-A topology, it is comparable to class-AB amplifiers. Detailed circuit analyses such as differential-mode, common-mode feedback, noise, slew rate, and input/output range are carried out. Based on these analyses, a manual design methodology and a genetic algorithm based optimization are presented. Finally, the most relevant experimental results for an integrated circuit prototype designed in a 0.13 m 1.2 V standard CMOS technology are shown. Index Terms-Amplifier, CMOS analog integrated circuits, fully differential, inverter, operational transconductance amplifier, selfbiased. I. INTRODUCTION T HERE HAS BEEN an ongoing tendency in lowering the operating supply voltages in mixed signal circuits, mainly due to reliability reasons (e.g., to prevent gate oxide breakdown) in the continuous downscaling of transistors' feature size in nanoscale CMOS technologies. This tendency is equally justified by the need of low power dissipation circuits for longer lasting battery-powered systems. These systems usually integrate complex building blocks such as analog-to-digital converters and continuous or discrete-time Manuscript

Microelectronics International, 2020

Purpose The purpose of this paper is to demonstrate the acceptable performance by using the limited input range towards lower open-loop DC gain operational amplifier (op-amp) of an 8-bit pipelined analog-to-digital converter (ADC) for mobile communication application. Design/methodology/approach An op-amp with folded cascode configuration is designed to provide the maximum open-loop DC gain without any gain-boosting technique. The impact of low open-loop DC gain is observed and analysed through the results of pre-, post-layout simulations and measurement of the ADC. The fabrication process technology used is Silterra 0.18-µm CMOS process. The silicon area by the ADC is 1.08 mm2. Findings Measured results show the differential non-linearity (DNL) error, integral non-linearity (INL) error, signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) are within −0.2 to +0.2 LSB, −0.55 LSB for 0.4 Vpp input range, 22 and 27 dB, respectively, with 2 MHz input signal at the rate of ...

2011

This paper presents the analysis and design of high speed, high gain fully differential operational amplifier (opamp). Both the main op-amp and the boosting op-amp are fully differential folded-cascode. The main op-amp has a switched capacitor common mode feedback circuit. Two fully differential folded-cascode op amps with continuoustime CMFBs are used as auxiliary op amps to increase the open-loop gain of the main op amp. Common mode feedback (CMFB) is used to stable the designed op-amp against temperature. This design has been implemented in 0.18μm UMC mixed signal CMOS Technology using Cadence. Spectre simulation shows that the op-amp has the DC gain of 112dB and the unity gain bandwidth of 1.15GHz.

International Journal of Circuit Theory and Applications, 2009

The body-driven variant of the gain-boosting technique is here exploited to design a CMOS transconductance amplifier with minimum supply below 1 V. When compared with the conventional gain-boosting technique, the proposed body-driven approach reduces the minimum supply requirement by two thresholds in a rail-to-rail amplifier exploiting two complementary input stage topologies. Simulations using a 130-nm process show that a 0.9-V power supply is adequate for a single-stage rail-to-rail amplifier providing a 56-dB gain, which is 18 dB higher than that achieved by the same architecture but using the traditional cascoding approach. The main drawbacks are that the solution requires a twin-tub process and an additional bias section. Figure 7. Step response in unity gain of the three amplifiers: (a) standard; (b) gain-boosted; and (c) body-driven gain-boosted cascoded.

2013

A single-output CMOS differential amplifier is one of useful analog building blocks for signal-processing applications in mixed-signal circuits. One of advantages of using a differential amplifier instead of other transistor amplifiers is its simple biasing and high amplifier gain. In this paper, in order to improve the differential mode gain, we propose a design for a single-output CMOS differential amplifier with an active load. This circuit can reach a differential-mode gain of 165 while consuming power of 195 µw.

In this paper design and implementation of a two stage fully differential, RC Miller compensated CMOS operational amplifier is presented. High gain enables this circuit to operate efficiently in a closed loop feedback system, whereas high bandwidth makes it suitable for high speed applications. The design is also able to address any fluctuation in supply or dc input voltages and stabilizes the operation by nullifying the effects due to perturbations. Implementation has been done in 0.18 um technology using libraries from tsmc with the help of tools from Mentor Graphics and Cadence. Op-amp designed here exhibits >95 dB DC differential gain, ~135 MHz unity gain bandwidth, phase margin of ~53 o , and ~132 V/uS slew rate for typical 1 pF differential capacitive load.

2018

In this paper, an adaptive fully differential OPAMP using Self Cascode MOSFET Transistors giving a maximum differential gain 75.31 dB with slew rate of 14.58 V/μS has been presented. In comparison to conventional 2 stage operational amplifier design, proposed design with adaptive bias has slew rate increased by 7× for a capacitive load of 3 pF. An adaptive bias circuit with current reference circuit is also designed using Self Cascode MOSFET Transistors to get reference current varying by only 20 nA when temperature varies from 25oC to 100oC. A Common Mode Feedback circuit designed using Self Cascode MOSFET Transistors shows only 0.01 % variation in Vocm as Vicm varies by 1 V. The proposed OPAMP has been developed in a standard TSMC 0.18 μm CMOS technology and the simulations are done using Cadence software.

2006

In this paper we present a three-stage fully differential operational amplifier in 120nm digital CMOS. To reach high gain gain-boosted cascodes in the first stage are used. The gain-boost amplifiers are realized as two-stage amplifiers with self cascodes. A DC gain of 108dB and an unity-gain frequency of 1.06GHz are achieved at 1.2V supply. The operational amplifier is appropriate for supply voltages from 1.5V down to 1.0V.

A two-stage CMOS operational amplifier with both, gainboosting and indirect current feedback frequency compensation performed by means of regulated cascode amplifiers, is presented. By using quasi-floating-gate transistors (QFGT) the supply requirements, the number of capacitors and the size of the compensation capacitors respect to other Miller schemes are reduced. A prototype was fabricated using a 0.5 µm technology, resulting, for a load of 45 pF and supply voltage of ±1.65 V, an open-loop-gain of 129 dB, 23 MHz of gain-bandwidth product, 60 o phase margin, 675 µW power consumption and 1% settling time of 28 ns.

IEEE Access

A fully differential Miller op-amp with a composite input stage using resistive local common-mode feedback and regulated cascode transistors is presented here. High gain pseudo-differential auxiliary amplifiers are used to implement the regulated cascode transistors in order to boost the output impedance of the composite input stage and the open-loop gain of the op-amp. Both input and output stages operate in class AB mode. The proposed op-amp has been simulated in a 130nm commercial CMOS process technology. It operates from a 1.2V supply and has a close to rail-to-rail differential output swing. It has 156dB DC open-loop gain and 63MHz gain-bandwidth product with a 30pF capacitive load. The op-amp has a DC open-loop gain figure of merit FOM AOLDC of 174 (MV/V) MHz pF/µW and large-signal figure of merit FOM LS of 3(V/µs) pF/µW. INDEX TERMS Class-AB op-amp, fully differential amplifier, Miller-compensation, regulated cascode, resistive local common-mode feedback, voltage follower.