Exact Synthesis of Boolean Functions in Majority-of-Five Forms

2021

Quantum dot cellular automata is the recent trend in the field of technology for the designing of any digital circuit involving inverters and majority gates that has the potential to substitute the age old technology of CMOS at the order of Nano level. Herein a full adder and full subtractor circuit is proposed using 5-input majority gate. The new full adder and subtractor reduced the requirement of occupied area, number of cells and energy dissipation. A N-bit ripple carry adder is also designed by one bit full adder. KeywordsQuantum-dot cellular automata (QCA) , VLSI, Logic Gates,

In this paper, we consider the problem of logic simplification for a special class of logic functions, namely complementary Boolean functions (CBF), targeting low power implementation using static CMOS logic style. The functions are uniquely characterized by the presence of terms, where for a canonical binary 2-tuple, D(m j ) ∪ D(m k ) = { } and therefore, we have | D(m j ) ∪ D(m k ) | = 0 [19]. Similarly, D(M j ) ∪ D(M k ) = { } and hence | D(M j ) ∪ D(M k ) | = 0. Here, 'm k ' and 'M k ' represent a minterm and maxterm respectively. We compare the circuits minimized with our proposed method with those corresponding to factored Reed-Muller (f-RM) form, factored Pseudo Kronecker Reed-Muller (f-PKRM) form, and factored Generalized Reed-Muller (f-GRM) form.

2016

A Majority-Inverter Graph (MIG) is a directed acyclic graph in which every vertex represents a three-input majority operation and edges may be complemented to indicate operand inversion. MIGs have algebraic and Boolean properties that enable efficient logic optimization. They have been shown to obtain superior synthesis results as compared to state-of-theart And-Inverter Graph (AIG) based algorithms. In this paper, we extend MIGs to Functionally Reduced MIGs (FRMIGs), analogous to the extension of AIGs to Functionally Reduced AIGs (FRAIGs). This enables the use of MIGs in a lossless synthesis design flow. We present an FRMIG based technology mapper for lookup tables (LUTs). Any MIG may be mapped to a k-LUT network. Using exact synthesis we may decompose the k-LUT network back into an equivalent MIG. We show how LUT mapping and exact k-LUT decomposition can be used to create an MIG optimization method. Finally, we present the results of applying our new optimization method and LUT mapper to both logic optimization and technology mapping.

2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021

Emerging reconfigurable nanotechnologies allow the implementation of self-dual functions with a fewer number of transistors as compared to traditional CMOS technologies. To achieve better area results for Reconfigurable Field-Effect Transistors (RFET)-based circuits, a large portion of a logic representation must be mapped to self-dual logic gates. This, in turn, depends upon how self-duality is preserved in the logic representation during logic optimization and technology mapping. In the present work, we develop Boolean size-optimization methods-a rewriting and a resubstitution algorithm using Xor-Majority Graphs (XMGs) as a logic representation aiming at better preserving self-duality during logic optimization. XMGs are more compact for both unate and binate logic functions as compared to conventional logic representations such as And-Inverter Graphs (AIGs) or Majority-Inverter Graphs (MIGs). We evaluate the proposed algorithm over crafted benchmarks (with various levels of self-duality) and cryptographic benchmarks. For cryptographic benchmarks with a high self-duality ratio, the XMG-based logic optimisation flow can achieve an area reduction of up to 17% when compared to AIG-based optimization flows implemented in the academic logic synthesis tool ABC.

2001

Decomposition of any Boolean Function BF_n of n binary inputs into an optimal inverter coupled network of Symmetric Boolean functions SF_k (k \leq n) is described. Each SF component is implemented by Threshold Logic Cells, forming a complete and compact T-Cell Library. Optimal phase assignment of input polarities maximizes local symmetries. The "rank spectrum" is a new BF_n description independent of input ordering, obtained by mapping its minterms onto an othogonal n \times n grid of (transistor-) switched conductive paths, minimizing crossings in the silicon plane. Using this ortho-grid structure for the layout of SF_k cells, without mapping to T-cells, yields better area efficiency, exploiting the maximal logic path sharing in SF's. Results obtained with an optimization tool "Ortolog" based on these concepts, for very fast O(n^2) detecting and enhancing local symmetries of a BF_n, are reported. Relaxing symmetric- to planar- Boolean functions is sketched, to improve low- symmetry BF decomposition.

2001

The main result of this paper is the development of a systematic paper-and-pencil design methodology for implementing Boolean functions of up to 4 variables using threshold logic (TL) gates, which does not require linear programming, for the first time. The methodology is similar in operation to the Karnaugh map logic minimization technique, and is based on determining the minimum threshold cover of a Boolean function. The paper also reviews aspects of TL and illustrates the application of the proposed design methodology to VLSI design using the neuron-MOS technique.

2007 International Conference on Electrical Engineering, 2007

In this paper we propose a novel and efficient method for majority gate-based design. The basic Boolean primitive in quantum cellular automata (QCA) is the majority gate. Method for reducing the number of majority gates required for computing Boolean functions is developed to facilitate the conversion of Sum Of Products (SOP) expression into QCA majority logic. This method is based on genetic algorithm and can reduce the hardware requirements for a QCA design. We will show that the proposed approach is very efficient in deriving the simplified majority expression in QCA design.

2021

Four terminal switching network is an alternative structure to realize the logic functions in electronic circuit modeling. This network can be used to implement a Boolean function with less number of switches than the two terminal based CMOS switch. Each switch of the network is driven by a Boolean literal. Any switch is connected to its four neighbors if a literal takes the value 1 , else it is disconnected. In our work, we aimed to develop a technique by which we can find out if any Boolean function can be implemented with a given four-terminal network. It is done using the path of any given lattice network. First, we developed a synthesis tool by which we can create a library of Boolean functions with a given four-terminal switching network and random Boolean literals. This tool can be used to check the output of any lattice network which can also function as a lattice network solver. In the next step, we used the library functions to develop and test our MAPPING tool where the f...

Intelligent Computing and …, 2009

The majority-gate and the inverter-gate together make a universal set of Boolean primitives in Quantum-dot Cellular Automata (QCA) circuits. An important step in designing QCA circuits is reducing the number of required primitives to implement a given Boolean function. This paper presents a method to reduce the number of primitive gates in a multi-output Boolean circuit. It extends the previous methodology based on genetic algorithm for converting sum of product expressions into a reduced number of QCA primitive gates in a single-output Boolean circuit. Simulation results show that the proposed method is able to reduce the number of primitive gates.

Objective of this paper is to present historiography of logic switching circuits. The research mainly focuses on chronological development and application of logic in the field of electronic and computer applications. This paper briefly discussed on the basic needs of logic synthesis and also discuss few interesting facts and design consideration regarding logic synthesis. It also enhances student’s deep understanding of different logic function minimization technique during a lecture and practical implementation.

We introduce a Reversible Programmable Gate Array (RPGA) based on regular structure to realize binary functions in reversible logic. This structure, called a 2 * 2 Net Structure, allows for more efficient realization of symmetric functions than the methods shown by previous authors. In addition, it realizes many non-symmetric functions even without variable repetition. Our synthesis method to RPGAs allows to realize arbitrary symmetric function in a completely regular structure of reversible gates with smaller "garbage" than the previously presented papers. Because every Boolean function is symmetrizable by repeating input variables, our method is applicable to arbitrary multi-input, multi-output Boolean functions and realizes such arbitrary function in a circuit with a relatively small number of garbage gate outputs. The method can be also used in classical logic. Its advantages in terms of numbers of gates and inputs/outputs are especially seen for symmetric or incompletely specified functions with many outputs.

The paper presents a family of new expansions of Boolean functions called Function-driven Linearly Independent (fLI) expansions. On the basis of this expansion a new kind of a canonical representation of Boolean functions is constructed: Function-driven Linearly Independent Binary Decision Diagrams (fLIBDDs). They generalize both Function-driven Shannon Binary Decision Diagrams (fShBDDs) and Linearly Independent Binary Decision Diagram (LIBDDs). The diagrams introduced in the paper, can provide significantly smaller representations of Boolean functions than standard Ordered Binary Decision Diagrams (OBDDs), Ordered Functional Decision Diagrams (OFDDs) and Ordered (Pseudo-) Kronecker Functional Decision Diagrams (OKFDDs) and can be applied to synthesis of reversible circuits.

Microprocessors and Microsystems, 2018

In this paper we propose a novel approach to the synthesis of minimal-sized lattices, based on the decomposition of logic functions. Since the decomposition allows to obtain circuits with a smaller area, our idea is to decompose the Boolean functions according to generalizations of the classical Shannon decomposition, then generate the lattices for each component function, and finally implement the original function by a single composed lattice obtained by glueing together appropriately the lattices of the component functions. In particular we study the two decomposition schemes defining the bounded-level logic networks called Pcircuits and EXOR-Projected Sums of Products (EP-SOPs). Experimental results show that about 34% of our benchmarks achieve a smaller area when implemented using the P-circuit decomposition for switching lattices, with an average gain of at least 25%, and about 27% of our benchmarks achieve a smaller area when implemented using the EP-SOP decomposition, with an average gain of at least 22%.

IEEE Access

Due to the physical restriction of current CMOS technology, the study of majority based nanotechnologies has been progressing steadily. In this paper, we present a new exact synthesis algorithm for majority-of-three and majority-of-five boolean functions. Key in our approach is the formulation of constraints that encodes majority logic problems into linear optimization models. The proposed algorithm is able to generate optimal results for both depth and size minimization, while also minimizing the number of inverters and literals in the output function. With this new approach, we can decrease the total production cost of a circuit in technologies where inverters and literals are expensive to build, without losing optimal results for depth and size minimization. To evaluate our method, a comparison was made with two exact synthesis algorithms that can generate optimal results when considering depth and size as cost criteria, for majorityof-three and majority-of-five boolean functions. Since our method considers two additional cost criteria, the goal is to generate functions that are also optimal in relation to depth and size, but with less inverters and literals. The obtained results have shown that the proposed algorithm was able to further optimize 64% of all 220,376 compared functions, while also achieving equal cost results for the remaining 36%.

Lecture Notes in Computer Science

Logic Programming languages and combinational circuit synthesis tools share a common "combinatorial search over logic formulae" background. This paper attempts to reconnect the two fields with a fresh look at Prolog encodings for the combinatorial objects involved in circuit synthesis. While benefiting from Prolog's fast unification algorithm and built-in backtracking mechanism, efficiency of our search algorithm is ensured by using parallel bitstring operations together with logic variable equality propagation, as a mapping mechanism from primary inputs to the leaves of candidate Leaf-DAGs implementing a combinational circuit specification. After an exhaustive expressiveness comparison of various minimal libraries, a surprising first-runner, Strict Boolean Inequality "<" together with constant function "1" also turns out to have small transistor-count implementations, competitive to NAND-only or NORonly libraries. As a practical outcome, a more realistic circuit synthesizer is implemented that combines rewriting-based simplification of (<, 1) circuits with exhaustive Leaf-DAG circuit search.