Pulse Ring Oscillator Tuning via Pulse Dynamics

International Journal of Electrical and Computer Engineering (IJECE), 2019

A common voltage-controlled oscillator (VCO) architecture used in the phase locked loop (PLL) is the ring oscillator (RO). RO consist of number of inverters cascaded together as the input of the first stage connected to the output of the last stage. It is important to design the RO to be work at desired frequency depend on application with low power consumption. This paper presents a review the performance evaluation of different delay cell topologies the implemented in the ring oscillator. The various topologies analyzed includes current starved delay cell, differential delay cell and current follower cell. Performance evaluation includes frequency range, frequency stability, phase noise and power consumption had been reviewed and comparison of different topologies has been discussed. It is observed that starved current delay cell have lower power consumption and the different of the frequency range is small as compared to other type of delay cell. 1. INTRODUCTION Basically, oscillator is a frequency translation that translate information signal with time reference. There is variation of oscillator with different principle operation, frequency oscillation and its noise performance. For instant, voltage-controlled oscillator (VCO) is one type of oscillator that output oscillation frequency can be varied by varying the amplitude of its input signal. There are two architectures of VCO namely; the ring oscillator and the LC oscillator. Ring oscillator is widely used in the communication system design especially in the wireless ssystem [1]-[5] and FPGA application [6], [7] because of its wide tuning range, making them more robust over process and temperature variations. It also use used to study the degradation of logic CMOS circuit [8], [9]. Many trade-offs in terms of speed, power, area and application domain need to be considered in designing a ring oscillator. Thus, it is important to determine accurate frequency oscillation of the ring oscillator so that the designer able to make informed decisions regarding these trade-offs. This paper is organized as follows. Section 2 discuss the basic concept of ring oscillator and the equations related to oscillation frequency that have been derived in previous works. In Section 3 investigates the available delay topologies used ring oscillator. Section 4 compares the performance and discuss the advantage and disadvantages of each topology. Section 5 presents our conclusions.

IEEE Transactions on Semiconductor Manufacturing, 2006

Test structures utilizing ring oscillators to monitor MOSFET ac characteristics for digital CMOS circuit applications are described. The measurements provide information on the average behavior of sets of a few hundred MOSFETs under high speed switching conditions. The design of the ring oscillators is specifically tailored for process centering and monitoring of variability in circuit performance in the manufacturing line as well as in the product. The delay sensitivity to key MOSFET parameter variations in a variety of ring oscillator designs is studied using a compact model for partially depleted silicon on insulator (PD-SOI) technology, but the analysis is equally valid for conventional bulk Si technology. Examples of hardware data illustrating the use of this methodology are taken primarily from experimental hardware in the 90-nm CMOS technology node in PD-SOI. The design and data analysis techniques described here allow very rapid investigation of the sources of variations in circuit delays.

2012

This paper presents a new technique to improve frequency performance of CMOS ring oscillator. It is based on the addition of MOS transistor to boost switching speed of the oscillator delay cell. The method can be used for simple and differential oscillator and offers a simple way to implement frequency tuning without introduction of any additional phase noise. Using 0.35 μm CMOS technology, simulation results show that applying the technique to the simple ring oscillator allows a frequency oscillation improvement of 80%. Also, simulations show that frequency improvement can reach 300 % if the technique is associated to a positive feedback.

2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS), 2014

Self-timed rings are promising for designing highspeed serial links and system clock generators. Indeed, their architecture is well-suited to digitally control their frequency and to easily adapt their phase noise by design. Self-timed ring oscillation frequency does not only depend on the number of stages as the usual inverter ring oscillators but also on their initial state. This feature is extremely important to make them programmable. Moreover, with such ring oscillators, it is easy to control the phase noise by design. Indeed, 3dB phase noise reduction is obtained at the cost of higher power consumption when the number of stages is doubled while keeping the same oscillation frequency, thanks to the oscillator programmability. In this paper, we completely describe the method to design selftimed rings in order to make them programmable and to generate a phase noise in accordance with the specifications. Test chips have been designed and fabricated in AMS 0.35 µm and in STMicroelectonics CMOS 65 nm technology to verify our models and theoretical claims. I.

Indian Journal of Pure and Applied …, 2010

The structure and operating principle of ring oscillators (RO) have been described. The expression for the frequency of oscillation of a complementary metal oxide semiconductor (CMOS) delay cell based conventional ring oscillator is presented and propagation delay of the delay stages is calculated. The limitations of a conventional RO have been studied and a few techniques to overcome these limitations have been mentioned. In this context, some modified structures of ring oscillators such as negative skewed delay RO, multi feedback RO, coupled RO are described for high frequency oscillation. The effect of noise sources on the output of ring oscillators has also been studied. Some potential applications of such ring oscillator based on its voltage tuning characteristics and multiphase outputs are also mentioned.

2005 IEEE International Symposium on Circuits and Systems

A novel and effective test circuit to measure cell-tocell delay mismatch due to process variations is presented. A fully digital control circuit that efficiently realizes the technique is also described. The proposed test structure is realized by a series of modified ring oscillators that minimize factors of inaccuracy. The results of a simulation using 0.18µm CMOS technology show the feasibility of the technique. This test structure can be beneficial in thoroughly characterizing the effects of systematical process variations inside the chip. I.

2017

This Paper reports on design and analysis of CMOS Voltage Controlled Ring Oscillator (VCRO) based on the delay cells proposed by Changzhi Li and Jenshan Lin. The two stage CMOS VCRO exhibits very low power consumption and wide tuning range when realized using GPDK 45 nm CMOS process. The oscillator has a very wide tuning range from 6 GHz to 17 GHz. Because of its wide tuning range, it can be used for electronic warfare applications. It has also very low power consumption of about 3µW with a supply voltage of 1 V. The phase noise of this ring oscillator is found to be-78 dBC/Hz @10 MHz offset which can be improved by adding more number of stages.

This project deals with the design and performance analysis of a ring oscillator using CMOS 180 nm technology process in Cadence virtuoso environment. The design of optimal Analog and Mixed Signal (AMS) very large scale integrated circuits (VLSI) is a challenging task for the integrated circuit(IC)designer. A Ring Oscillator is an active device which is made up of odd number of NOT gates and whose output oscillates between two voltage levels representing high and low. There are a number of challenges ahead while designing the CMOS Ring Oscillator which are delay, noise and glitches. CMOS is the technology of choice for many applications, CMOS oscillators with low power, phase noise and timing jitter are highly desired. In this project, we have designed a CMOS ring oscillator with nine stages. The researchers were unable to reduce the phase noise in ring oscillators substantially with nine stages. We have successfully reduced the phase noise to -6.4kdBc/Hz at 2GHz centre frequency of oscillation.

IEEE Transactions on Circuits and Systems II: Express Briefs, 2014

In this brief, a new technique to measure the on-chip rise/fall delay of an individual gate is presented. In the proposed technique, the rise/fall gate delay is measured using the duty cycle of a reconfigurable ring oscillator (RRO). A set of linear equations is formed with the different configuration settings of the RRO, relating the rise/fall delay of all the gates in the path of the RRO to the positive/negative duty cycle of the undivided RRO. The high-frequency undivided RRO signal is needed for this type of measurement as it preserves the rise/fall delay of an individual gate. However, it is difficult to bring the high-frequency undivided RRO signal outside the chip due to the frequency limitation of the output pad. The high-frequency RRO signal is subsampled by a clock that is generated from an on-chip phase-locked loop to make it low frequency. The rise and fall delays of an individual gate can be calculated from the difference of the duty cycle of the subsampled RRO signal at two different configurations of the RRO. The proposed concept is validated in a test chip that is fabricated in an industrial 65-nm technology node. Index Terms-Duty cycle, on-chip measurement of rise/fall gate delay, reconfigurable ring oscillator (RRO), subsampling technique.