Dynamic SMP clusters with communication on the fly

Efficient architectural solutions for systems based on shared memory processor clusters are presented in the paper. In the proposed architecture, processors can be dynamically switched between bus-based SMP clusters at program run-time. A switched processor can bring data in its cache that can be read on the fly by processors in the cluster when written into the cluster memory. This new inter-cluster data transfer paradigm is called communication on the fly. For execution in the proposed architecture, programs are structured accordingly to macro-data flow graphs in which task composition and communication are so defined, as to eliminate reloading of data caches during task execution. An extended macro-data flow graph representation is presented in the paper. It enables modeling of program execution control in the system including parallel task execution, data cache functioning, data bus arbiters, switching processors between clusters and multiple parallel reads of data on the fly. Simulation results for a very fine-grained parallel numerical example are presented.