On the design of pseudoexhaustive testable PLAs
Dong Ha1988, IEEE Transactions on Computers
Sign up for access to the world's latest research
checkGet notified about relevant papers
checkSave papers to use in your research
checkJoin the discussion with peers
checkTrack your impact
Abstract
AI
AI
The design of a Cluster-Proof scheme to enhance the reliability and yield of large area binary tree architectures is presented. This scheme allows for a higher level of flexibility in global sparing, mitigating faults in various components while maintaining performance. The research indicates that achieving an optimal balance of redundancy in links and switches contributes significantly to the reliability of the system. Future research directions are suggested to explore the implications of defect clustering and more effective measures of redundancy.
Related papers
Hardware approach for generating spanning trees in reliability studies
Microelectronics Reliability, 1981
The paper presents an algorithm to determine all the spanning trees of a given graph through a search technique. The algorithm has been proposed with the specific aim of developing a special purpose equipment, to achieve the objective. The paper describes the block diagram of such an equipment which can be realized by commercially available components.
Reliability and performance evaluation of four tree multistage interconnection network
Microelectronics Reliability, 1996
Reliability and performance of a multiprocessor system depend heavily upon the design of its interconnection network. This paper presents a comprehensive treatment to analyse a four tree network, a new class of irregular multistage interconnection networks (MIN), for reliability and performance. The results obtained are compared with the augmented shuffle exchange network (ASEN), a network with low link and switch complexity and having significantly improved reliability and performance amongst the regular type of MINs. The reliability results, both optimistic and pessimistic, are better than for the ASEN as well as for most of the other networks. The performance analysis in the circuit switched environment shows that the probability of accepting the requests is significantly improved and there is negligible degradation in performance with increasing network size.
An efficient parallel strategy for computing K-terminal reliability and finding most vital edge in 2-trees and partial 2-trees
2002
In this paper, we first develop a parallel algorithm for computing K-terminal reliability, denoted by R(G K), in 2-trees. Based on this result, we can also compute R(G K) in partial 2-trees using a method that transforms, in parallel, a given partial 2-tree into a 2-tree. Finally, we solve the problem of finding most vital edges with respect to K-terminal reliability in partial 2-trees. Our algorithms take O(log n) time with C(m, n) processors on a CRCW PRAM, where C(m, n) is the number of processors required to find the connected components of a graph with m edges and n vertices in logarithmic time.
Evaluation of Two Terminal Reliability of Fault-tolerant Multistage Interconnection Networks
International Journal of Communication Networks and Security, 2013
This paper iOntroduces a new method based on multi-decomposition for predicting the two terminal reliability of fault-tolerant multistage interconnection networks. The method is well supported by an efficient algorithm which runs polynomially. The method is well illustrated by taking a network consists of eight nodes and twelve links as an example. The proposed method is found to be simple, general and efficient and thus is as such applicable to all types of fault-tolerant multistage interconnection networks. The results show this method provides a greater accurate probability when applied on fault-tolerant multistage interconnection networks. Reliability of two important MINs are evaluated by using the proposed method.
An Approach to Investigating Reliability Indices for Tree Topology Network
Cybernetics and Systems, 2016
Due to advance technology, rapidly emergent complexity of networks and perseverance on network quality, reliability, and maintainability are progressively significant issues, and hence, the job of reliability analysts is becoming more challenging. A network's optimum design is required for maintaining the reliability of a sophisticated network at a high level. Reliability of tree topology plays a key role in the measurement of quality of a network and in the performance of a network. Large-scale distributed networks are subject to frequent interruptions due to resource contention and failure. Failure of any component or subsystem affects the performance of the network. This research work has two significant goals: to design a mathematical model of a tree network using the Markov process and supplementary variable technique, and to determine the reliability characteristics such as availability, reliability, and mean time to failure (MTTF). The authors also seek the sensitivity analysis for reliability measures along with the precise values of the input parameters which is very helpful and necessary for attaining a highly reliable network.
Assessing reliability of multistage interconnection networks
1993
Efficient methods for determining the lower and upper bounds on the probabilities of source-to-terminal communication in a multistage interconnection network are developed. A novel lower bounding strategy (shifting) and a novel upper bounding strategy (renormalization) are presented; both can be computed in polynomial time. These strategies can be combined with existing methods based on coherence, and on consecutive cuts, to obtain an improvement on previously known efficiently computable bounds. A second efficient upper bound (averaging) is developed. An empirical evaluation of the bounds is discussed. Finally, the value of these bounding strategies in assessing the reliability of interconnection networks is examined.
Fault-tolerant analysis and algorithms for a proposed augmented binary tree architecture
[1989] Proceedings. The 9th International Conference on Distributed Computing Systems
In this paper an "Augmented Binary Tree" architecture is proposed with a view to provide faulttolerance. This architecture is an augmentation of an n-level full binary tree with n redundant nodes and 2 n +3n-6 redundant links. The AB-tree can be configured into a full binary tree even when one node is faulty at each level. While functionally equivalent to the RAE-tree [13], the proposed AB-tree has a regular topology, reduced number of maximum input-output channels per processor, and fewer number of wire crossovers in VLSI layout. A reconfiguration algorithm, which constructs an nlevel full binary tree from an n-level faulty ABtree, is given. A distributed fault diagnosis algorithm, that runs concurrently on each nonfaulty processor, enables each nonfaulty processor to identify all faulty processors, is also given.
Fault tolerance of decomposed PLAs
2010
Abstract The paper deals with the fault tolerance of finite state machines (FSMs) implemented by nanoelectronic programmable logic arrays (PLAs). The paper studies a fault tolerant nano-PLA structure, which is based on implementing an initial FSM in a form of three interacting dense PLAs. The paper provides experimental benchmarks results for estimation of fault tolerance properties of the proposed solution. The results indicate a high efficiency of the proposed decomposition approach.
Transactions on Reliability Circular Layout Cutsets : an Approach for Improving the Consecutive Cutsets Bound for Network Reliability
2005
In this paper we introduce a new type of parametrized class of cutsets for the 2-terminal network reliability problem, called the circular layout (CL) cutsets with parameterk, and devise a polynomial time algorithm for computing upper bounds from such structures. The CL cutsets and the devised bounding method are characterized by the following aspects. 1. CL cutsets include the well known class of consecutive minimal cutsets, introduced by Shanthikumar, as a proper subset. Thus, bounds obtained by our main algorithm yield strict improvements on the basic consecutive cutsets algorithm. We note that extensive empirical studies done to date have shown that the consecutive cutsets method, when empowered by heuristics for choosing suitable cutsets, yields competitive bounds. 2. CL cutsets satisfy the semilattice structure required by Shier’s algorithm for computing upper bounds in time polynomial in the number of cuts in a given cutset. Thus, CL cutsets define a new class of efficiently ...
Allocation and mapping based reliability analysis of multistage interconnection networks
IEEE Transactions on Computers, 1996
Task allocation using cubic partitioning of multistage interconnection networks (MINs) offers several advantages over random allocation of resources. The objective of this paper is to analyze MIN reliability considering the cubic allocation algorithm. A comprehensive analytical model is derived for predicting reliability of MIN-based systems where tasks are allocated using the buddy strategy. System reliability with the free list allocation policy is computed via simulation. It is shown that the system reliability is dependent on the allocation algorithm and the free list policy is superior to the buddy scheme in this respect. Two types of mapping algorithms known as conventional and bit reversal are used on a baseline MIN to show that the same allocation algorithm can result in different reliability and performance. A performance-related reliability measure is analyzed using probability of acceptance as the performance measure to demonstrate the trade-offs between performance and reliability.
Related papers
An effective algorithm for computing all-terminal reliability bounds
Networks, 2015
The exact calculation of all-terminal reliability is not feasible in large networks. Hence estimation techniques and lower and upper bounds for all-terminal reliability have been utilized. Here, we propose using an ordered subset of the mincuts and an ordered subset of the minpaths to calculate an all-terminal reliability upper and lower bound, respectively. The advantage of the proposed new approach results from the fact that it does not require the enumeration of all mincuts or all minpaths as re-1
On Design, Cost and Reliability Analysis of a Fault-Tolerant Multistage Interconnection Network Layout with Six Disjoint Paths
Research Square (Research Square), 2023
Multistage interconnection networks (MINs) provide an e cient solution for communication between one or more processors and memory modules. These networks are suitable for computationally extensive applications. Although there exist a wide variety of faulttolerant MIN designs, however there is always a scope of improvement in the design of MINs, which comes with challenges and tradeoffs. More speci cally there is always a need for fault-tolerant, reliable, and cost-effective designs of MINs, which can tolerate multiple switches and link failures. This always motivates a researcher to focus on various design options and architectural models to enhance performance of the MINs.Designing fault-tolerant MINs requires more disjoint paths from each source-destination (S-D) node pair capability to use all available paths effectively. This paper proposes a new MIN layout viz; 6DP-MIN, which provides six disjoint paths and 14/12 redundant paths for different S-D node pairs. This proposed 6DP-MIN is a modi cation of gamma interconnection network (GIN). Performance of the proposed design layout (6-Disjoint Path MIN) has been evaluated in terms of fault-tolerance capability, all available paths, reliability (two-terminal, broadcast, and network), and cost per unit. The results have been compared with other variants of GINs such as SEGIN, SEGLNIN, 3-Disjoint gamma interconnection network, 3-disjoint path multistage interconnection networks, and 4-DGINs. The results suggests that the proposed 6DP-MIN is highly fault-tolerant and reliable with regards to other MINs used for comparison.
An Efficient Parallel Strategy for ComputingK-Terminal Reliability and Finding Most Vital Edges in 2-Trees and Partial 2-Trees
1998
We develop a parallel strategy to compute K-terminal reliability in 2-trees and partial 2-trees. We also solve the problem of finding the most vital edge with respect to Kterminal reliability in partial 2-trees. Our algorithms take Olog n time with Cm; n processors on a CRCW PRAM, where Cm; n is the number of processors required to find connected components of a graph with m edges and n vertices in logarithmic time.
ESTA: An Efficient Method for Reliability Enhancement of RT-Level Designs
Test, Asian Symposium, 2006
This paper proposes a novel and efficient method for RT level online testing. Our method makes every RT-level resource online-testable, and guarantees high single stuck-at fault detection (i.e., high reliability) with low area/latency overhead. This method uses available resources in their dead intervals (the intervals during which a resource is not being used) to test active resources. The area and/or
An algorithm for computing all-terminal reliability bounds
2014 6th International Workshop on Reliable Networks Design and Modeling (RNDM), 2014
The exact calculation of all-terminal reliability is not feasible in large networks. Hence estimation techniques and lower and upper bounds for all-terminal reliability have been utilized. We propose using an ordered subset of the mincuts and an ordered subset of minpaths to calculate an all-terminal reliability upper and lower bound, respectively. The advantage of the proposed approach results from the fact that it does not require the enumeration of all mincuts or all minpaths as required by other bounds. The performance of the algorithm is compared with the first two Bonferroni bounds, for networks where all mincuts could be calculated. The results show that the proposed approach is computationally feasible and reasonably accurate. Thus allowing one to obtain bounds when it not possible to enumerate all mincuts or all minpaths.
Multi-tiered approach to improving the reliability of multi-level cell PRAM
2012
Phase change RAM (PRAM) is a promising memory technology because of its fast read access time, high storage density and very low standby power. Multi-level Cell (MLC) PRAM which has been introduced to further improve the storage density, comes at a price of lower reliability. This paper focuses on a cost-effective solution for improving the reliability of MLC-PRAM. As the first step, we study in detail the causes of hard and soft errors and develop error models to capture these effects. Next we propose a multi-tiered approach that spans architecture, circuit and system levels to increase the reliability. At the architecture level, we use a combination of Gray code encoding and 2-bit interleaving to partition the errors so that a lower strength error correction coding (ECC) can be used for half of the bits that are in the odd block. We use subblock flipping and threshold resistance tuning to reduce the number of errors in the even block. For even higher reliability, we use a simple BCH based ECC on top of these techniques. We show that the propose multi-tiered approach enables us to use a low cost ECC with 2-error correction capability (t=2) instead of one with t=8 to achieve a block failure rate of 10-8 .
A Low Cost Multi-Tiered Approach to Improving the Reliability of Multi-Level Cell Pram
Journal of Signal Processing Systems, 2013
Phase change RAM (PRAM) is a promising memory technology because of its fast read access time, high storage density and very low standby power. Multi-level Cell (MLC) PRAM which has been introduced to further improve the storage density, comes at a price of lower reliability. This paper focuses on a cost-effective solution for improving the reliability of MLC-PRAM. As the first step, we study in detail the causes of hard and soft errors and develop error models to capture these effects. Next we propose a multi-tiered approach that spans architecture, circuit and system levels to increase the reliability. At the architecture level, we use a combination of Gray code encoding and 2-bit interleaving to partition the errors so that a lower strength error correction coding (ECC) can be used for half of the bits that are in the odd block. We use subblock flipping and threshold resistance tuning to reduce the number of errors in the even block. For even higher reliability, we use a simple BCH based ECC on top of these techniques. We show that the propose multi-tiered approach enables us to use a low cost ECC with 2-error correction capability (t=2) instead of one with t=8 to achieve a block failure rate of 10-8 .
Structural reliability of centralised tree network
Electronics Letters, 1973
Studies on rectapgular wave modulation and related asynchronous modulation systems," Ph.D. dissertation, Indian Inst. TechEol., Kharagpur., India, 1966. [9] M. N. Faruoui. Studies on unidinit PCM svstems." Ph.D. dis-[lo1 a 2 2 0 -In ' + --2 L O O P A D M S Y S T E M [32 K b / g . ~ : l o -(REF. 3)[32Kb/S] 0 -I I I I I I I 1 I 1 I -5 0 -4 0 -3 0 -20 -I 0 0 I N P U T L E V E L d b + Fig. 7. Comparison of the 32-kbits/s two loop A D M system with the DCDM and the continuous delta modulation systems. 4 0 r '("/ (aj-2 LOOP ADM x(d) (b)-FLAT SPECTRUM ADM ( c ) -A D M ( J A Y A N T ) 0 2 0 (d)-L o g P C M I I I 1 I I 10 20 3 0 .40 50 60 70 O U T P U T B I T R A T E K b / S e Fig. 8. Comparison of the SNR of the various systems for different bit rates. The log PCM curve is for the standard 8-kbits/s sampling rate.
A Memory-efficient Bounding Algorithm for the Two-terminal Reliability Problem
Electronic Notes in Theoretical Computer Science, 2013
The terminal-pair reliability problem, i.e. the problem of determining the probability that there exists at least one path of working edges connecting the terminal nodes, is known to be NP-hard. Thus, bounding algorithms are used to cope with large graph sizes. However, they still have huge demands in terms of memory. We propose a memory-efficient implementation of an extension of the Gobien-Dotson bounding algorithm. Without increasing runtime, compression of relevant data structures allows us to use low-bandwidth highcapacity storage. In this way, available hard disk space becomes the limiting factor. Depending on the input structures, graphs with several hundreds of edges (i.e. system components) can be handled.
Reliability modeling of SCI ring-based topologies
Proceedings 25th Annual IEEE Conference on Local Computer Networks. LCN 2000, 2000
Performance evaluation and reliability prediction are two important factors in the study of multiprocessor and cluster interconnects. One such interconnect is the Scalable Coherent Interface (SCI). SCI is a point-to-point, ringbased interconnect that can be configured in various switched-ring topologies such as counter-rotating rings and tori. While performance analyses of SCI-based interconnects have been discussed in the literature, reliability evaluation has not received much attention. In addition, the reliability of SCI interconnects configured in many of today's popular topologies cannot be deduced from earlier work on network reliability as link failures within an SCI interconnect are not independent of one another. A single link failure within the topology results in the failure of the entire ringlet to which the link belongs. This paper presents the results of a reliability study on 1D and 2D k-ary ncube switching fabrics for the Scalable Coherent Interface based on ring elimination rather than link elimination. The study is conducted using reliability models created in UltraSAN, a tool based on Stochastic Activity Networks. The models are verified using both combinatorial and Markov modeling. The results demonstrate the inherent reliability characteristics of a single-ring system can be greatly enhanced by the addition of a second redundant ring. By contrast, the results show that the reliability of a torus does not increase significantly with the addition of redundant rings. Hence, the cost of adding redundant rings to certain topologies may or may not be justified, depending upon the degree of reliability sought.
Loading Preview
Sorry, preview is currently unavailable. You can download the paper by clicking the button above.