InterPRET: a Time-predictable Multicore Processor
Marten Lohstroh2023
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Abstract
With the end of Moore's law and the breakdown of Dennard scaling, multicore processors are the standard way to continue improving performance while reducing Size, Weight and Power (SWaP). However, this performance is typically achieved at the cost of repeatability and predictability. Precision-timed (PRET) architectures have been shown to deliver high performance without sacrificing predictability. In this paper, we introduce InterPRET: an architecture consisting of FlexPRET cores interconnected via the S4NOC network-on-chip. Both the processor cores and the network-onchip are time-predictable, yielding an end-to-end time-predictable architecture suitable for real-time systems. CCS CONCEPTS • Computer systems organization → Multicore architectures; Real-time system architecture.
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