Design and Implementation of 8X8 Truncated Multiplier on FPGA

Array (FPGA) implementation of standard and truncated multipliers using Very High Speed Integrated Circuit Hardware Description Language (VHDL). Truncated multiplier is a good candidate for digital signal processing (DSP) applications such as finite impulse response (FIR) and discrete cosine transform (DCT) etc. Significant reduction in FPGA resources, delay, and power can be achieved using truncated multipliers instead of standard parallel multipliers when the full precision of the standard multiplier is not required.

Truncated multiplier is a good candidate for digital signal processing (DSP) applications including finite impulse response (FIR) and discrete cosine transform (DCT). Through truncated multiplier a significant reduction in Field Programmable Gate Array (FPGA) resources can be achieved. This paper presents for the first time a comparison of resource utilization of Spartan-3AN and Virtex-5 implementation of standard and truncated multipliers using Very High Speed Integrated Circuit Hardware Description Language (VHDL). The Virtex-5 FPGA shows significant improvement as compared to Spartan-3AN FPGA device. The Virtex-5 FPGA device shows better performance with a percentage ratio of number of occupied slices for standard to truncated multipliers is increased from 40% to 73.86% as compared to Spartan-3AN is decreased from 68.75% to 58.78%. Results show that the anomaly in Spartan-3AN FPGA device average connection and maximum pin delay have been efficiently reduced in Virtex-5 FPGA device.

In the recent decade, decimal arithmetic has received a lot of attention. In existing research on decimal multiplication, latency and area are two key factors.In any case, today's computerized frameworks and DSP applications; energy/power utilization is a pivotal thought.For quick DSP, low power and high speed multipliers are required. Because of its regular structure and ease of design, the array multiplier is one of the fastest multipliers. To boost multiplier speed and improve power dissipation with the least amount of delay, adders and CMOS power gating based CLA are employed. In the paired number framework, the significant issue in numbercrunching relates to convey. A higher rad-ix number framework, Quaternary Signed Digit (QSD), is utilized to perform number juggling tasks without convey.

International Journal of Engineering Research and, 2016

Multiplication is crucial building block of Image Processing, Digital Signal Processing (DSP) applications like Fast Fourier Transform (FFT), Digital Filters etc. To achieve High Execution Speed or to meet the performance demands in DSP applications Parallel Array Multiplier are used to perform Multiplication. In this paper, an Advanced Array Multiplier using different types of compressors was designed and implemented on FPGA. The area consumed by Braun's Multiplier was reduced by using the different order compressors. The comparison of device utilization summary for conventional and proposed array design is presented.

Periodicals of Engineering and Natural Sciences (PEN), 2021

Multiplier is one of the most inevitable arithmetic circuit in digital signal design. Multipliers dissipate high power and occupy significant amount of the die area. In this paper, a low-error architecture design of the pretruncated parallel multiplier is presented. The coefficients word length has been truncated to reduce the multiplier size. This truncation scaled down the gate count and shortened the critical paths of partial product array. The statistical errors of the designed multiplier are calculated for different pre-truncate values and compared. The multiplier is implemented using Stratix III, FPGA device. The post fitting report is presented in this paper, which shows a saving of 36.9 % in resources usage, and a reduction of 17 % in propagation time delay.

—This paper proposes a design method for an 8-bit multiplication with reduced delay time. Normally, two numeric data can be multiplied by repeated addition. In case of binary multiplication, combinational circuit can be designed using manual multiplication method which requires binary addition. Carry generated because of addition affects the speed of multiplication since the present addition depends on the value of previous carry. To overcome this problem, addition with the help of multiplexer is introduced and the result is an increased speed in multiplication. Even though the proposed design is mainly for FPGA implementation, it can also be implemented in ASIC as the logical delay is reduced when compared the result in Xilinx device.

International Journal of Computer Applications, 2016

Many of the today"s real time signal processing algorithm included multiplication as its processing heart. In case of signal and image processing, it mostly used functional unit. In this paper we are simulating different multiplication algorithm with their effective architecture. Also paper introducing new multiplication technique using barrel shifter which gives some sort of modification in previously described shift and add multiplication algorithm. Research targeting mainly four algorithms as Vedic vertical crosswise multiplication algorithm, Array multiplier, Shift and add multiplier, Wallace tree multiplier. Further work will carried comparative study of different multiplier with respect to some parameters like logical resources used, delay, power consumption and area. For implementation and parametric analysis, experimental setup uses sparten-3 XC3S400 FPGA as a hardware platform, VHDL coding language for hardware description. Xilinx ISEsimulation tool has many inbuilt compatible facility for parameter analysis like XPE for power analysis. Finally Paper comprises simulation results for 8-bit, 16-bits and 32-bits each of above mentioned multiplier.

2014

The main theme of the paper is to design Compressor Based Low Power high speed and Area Efficient Multipliers on FPGA. In order to perform higher order multiplications more number of adders are required for the partial product addition. Special kind of adders are introduced which are capable of adding five/six/seven/eight/nine bits per decade with which we can reduce the number of adders and these special kind of adders are called as compressors. In order to develop higher order compressors, the combination of XOR gates and MUX circuits along with the binary counter property is contrasted with the conventional design. By using these compressors we can reduce the vertical critical paths. In this paper we present efficient implementation of multipliers with compressors on FPGA. When compared to carry propagate adders (CPA), high speed compressors provide fast critical path, independent of bit width with practically no area overhead. Design of such compressors will reduce the stage del...

In this paper 2 different multiplier architectures are implemented in Xilink FPGA and compared for their performance. Here these architectures are implemented for 4,8,16 bit Based on various speed-up schemes for binary multiplication, a comprehensive overview of different multiplier architectures are given in this report. In addition , it is found that booth multiplier is faster than array multiplier.

International Journal of Computer and Electrical Engineering, 2013