Degradation and Breakdown of Sub-1nm EOT HfO2/Metal Gate Stacks

2004

Both trap generation and Stress-Induced Leakage Current (SILC) are measured as a function of the stress voltage on a I n d 4 n m Si02/Hfoz stack. The S E C firstly rises proportionally with the bulk trap density in the HfOz but close to breakdown this relation becomes quadratic, indicating that first single-trap conduction paths are causing the SILC, later followed by two-trap conduction paths. At stress conditions, the S E C adds up to two decades to the initial leakage current. At elevated temperature, the leakage current increase is even higher. At room temperature, however, the S E C poses no reliability restriction for logic CMOS applications.

Microelectronic …, 2007

In this work, standard device level and nanoscale electrical tests have been carried out to evaluate the influence of the high-k and interfacial SiO 2 layers on the degradation of HfO 2 /SiO 2 gate stacks. At device level, the effect of static and dynamic electrical stresses has been investigated to evaluate the influence of the voltage polarity in the degradation of the gate stack. At nanoscale level, a Conductive Atomic Force Microscope (C-AFM) has allowed to separately investigate the effect of the electrical stress on the SiO 2 and HfO 2 layers.

IEEE Transactions on Electron Devices, 2014

Theoretical and experimental methods are applied to investigate the degradation of SiO 2 /HfO 2 gate-stacks in stateof-the-art MOSFETs. A combination of density functional theory and nonequilibrium Green's function formalism has been applied to the atomic scale calculation of the leakage current through SiO 2 /HfO 2 dielectrics. Samples with different dielectric stacks have been taken into account to study the thickness dependence of SiO 2 and HfO 2 on the leakage current. The calculated results show a good agreement with the leakage current and constant voltage stress measurements. The current influenced by oxygen vacancies, particularly in the high-k dielectric close to the SiO 2 /HfO 2 interface has been analyzed. Comparison between the measurement and simulation results show that oxygen vacancy defects in the HfO 2 are a likely cause for progressive stressinduced leakage current in MOSFETs with ultrathin high-k gate-stack.

2008 IEEE International Reliability Physics Symposium, 2008

The technique of combining the low frequency drain current noise and the frequency-dependent charge pumping techniques has been employed to extract the trap densities in both the interfacial SiO 2 layer and high-k layer in the n-type MOSFETs with HfO 2 /SiO 2 stacks. It is found that positive bias stress creates more traps in the gate dielectric stack near the gate electrode while negative stress increases the density of traps generated in the proximity of the Si substrate. The results show that under electrical stress new traps are predominantly created close to the anode side and the degree of asymmetry is surprisingly large.

Microelectronics Reliability, 2010

We compare charge carrier generation/trapping related degradation in control oxide (SiO 2) and HfO 2 /SiO 2 stack of an identical equivalent-oxide-thickness (EOT) during constant gate voltage stress of n-type metal-oxide-semiconductor (nMOS) capacitors. Irrespective of these two dielectrics, the kinetics of generation of both surface states and oxide-trapped positive charges are found to be similar. Our analysis shows that the positive oxide charge buildup during CVS is due to trapping of protons by the strained SiAOASi bonds in either of the devices. We demonstrate that compared to SiO 2 devices, HfO 2 devices with an equal EOT better perform in CMOS logic applications. On the other hand, our results indicate that the control oxide is better in charge trapping memory devices. Furthermore, the lifetime of the control oxide devices is observed longer than that of HfO 2 devices at a given operating voltage.

physica status solidi (a), 2015

An important source of degradation in thin dielectric material layers is the generation and migration of oxygen vacancies. We investigated the formation of Frenkel pairs (FPs) in HfO 2 as the first structural step for the creation of new defects as well as the migration of preexisting and newly built oxygen vacancies by nudged elastic band (NEB) calculations and stress induced leakage current (SILC) experiments. The analysis indicates, that for neutral systems no stable intimate FPs are built, whereas for the charge states q ¼ � 2 FPs are formed at threefold and at fourfold coordinated oxygen lattice sites. Their generation and annihilation rate are in equilibrium according to the Boltzmann statistics. Distant FPs (stable defects) are unlikely to build due to high formation energies and therefore cannot be accounted for the measured gate leakage current increase of nMOSFETs under constant voltage stress. The negatively charged oxygen vacancies were found to be very immobile in contrast to positively charged V 0 's with a low migration barrier that coincides well with the experimentally obtained activation energy. We show that rather the activation of preexisting defects and migration towards the interface than the defect generation are the cause for the gate oxide degradation.

IEEE Electron Device Letters, 2006

Replacing SiON by high-κ layers is a pressing issue for CMOS technologies. The presence of as-grown electron traps in HfO 2 is a major obstacle, since they can induce thresholdvoltage instability, reduce electron mobility, and result in early breakdown. Their location has not been clarified and is addressed in this letter. By selecting test conditions carefully and using samples with a progressive reduction of HfO 2 thickness, the authors are able to rule out that traps are piled up near the HfO 2 /HfSiO interface. A uniform distribution throughout HfO 2 does not agree with the test data, either. Results support that trapping is negligible near to one or both ends of the HfO 2 layer when compared with trapping in the central region.

Microelectronic Engineering, 2007

We have investigated electrical stress-induced charge carrier generation/trapping in a 4.2 nm thick (physical thickness T phy) hafnium oxide (HfO 2)/silicon dioxide (SiO 2) dielectric stack in metal-oxide-semiconductor (MOS) capacitor structures with negative bias on the gate. It is found that electron trapping is suppressed in our devices having an equivalent oxide thickness (EOT) as low as 2.4 nm. Our measurement results indicate that proton-induced defect generation is the dominant mechanism of generation of bulk, border and interface traps during stress. In addition, we have shown that constant voltage stress (CVS) degrades the dielectric quality more than constant current stress (CCS).

IEEE Transactions on Electron Devices, 2000

Transient relaxation, which has been addressed as an undesirable issue in high-k alternate gate dielectrics, has been studied systematically. In Hf-based dielectrics, it follows a universal line irrespective of stress times and stress voltages if stressed (static/dynamic) up to certain limits. The results presented here reveal that bulk charge trapping shows a fast transient relaxation (TR) for a very short time (∼ ms) after stress (substrate injection) followed by a slow relaxation (> 1 s), while interface passivation/ relaxation follows a slow trend. Bulk trappings, which play a major role in causing device instabilities in high-k gate oxides, are mostly relaxable, while interface degradation cannot be passivated completely. Moreover, an interface-passivation mechanism seems to be independent of stress histories. Devices with stronger bulktrapping immunity showed faster TR. The experimental results show good agreement with the simplified mathematical model presented for HfO 2 gate oxides. The temperature showed a negligible effect in TR.

ECS Transactions, 2008

Dielectric breakdown (BD) of nFETs with TiN metal gates and HfO 2 / interfacial layer with 1.09 nm EOT is studied. Occurrence of progressive BD at low current levels is demonstrated. A new measurement methodology for the characteristic growth time and its dependence on gate voltage are reported.