QBf-based boolean function bi-decomposition

Proceedings of the 38th …, 2001

We propose a new BDD-based method for decomposition of multi-output incompletely specified logic functions into netlists of two-input logic gates. The algorithm uses the internal don't-cares during the decomposition to produce compact well-balanced netlists with short delay. The resulting netlists are provably nonredundant and facilitate test pattern generation. Experimental results over MCNC benchmarks show that our approach outperforms SIS and other BDD-based decomposition methods in terms of area and delay of the resulting circuits with comparable CPU time.

2008

Boolean function bi-decomposition is a fundamental operation in logic synthesis. A function f (X) is bi-decomposable under a variable partition XA, XB, XC on X if it can be written as h(f A (X A , X C ), f B (X B , X C )) for some functions h, f A , and f B . The quality of a bi-decomposition is mainly determined by its variable partition. A preferred decomposition is disjoint, i.e. XC = ∅, and balanced, i.e. |XA| ≈ |XB|. Finding such a good decomposition reduces communication and circuit complexity, and yields simple physical design solutions. Prior BDD-based methods may not be scalable to decompose large functions due to the memory explosion problem. Also as decomposability is checked under a fixed variable partition, searching a good or feasible partition may run through costly enumeration that requires separate and independent decomposability checkings. This paper proposes a solution to these difficulties using interpolation and incremental SAT solving. Preliminary experimental results show that the capacity of bi-decomposition can be scaled up substantially to handle large designs.

VLSI Design, 1995

An effective logic synthesis procedure based on parallel and serial decomposition of a Boolean function is presented in this paper. The decomposition, carried out as the very first step of the .synthesis process, is based on an original representation of the function by a set of r-partitions over the set of minterms. Two different decomposition strategies, namely serial and parallel, are exploited by striking a balance between the two ideas. The presented procedure can be applied to completely or incompletely specified, singleor multiple-output functions and is suitable for different types of FPGAs including XILINX, ACTEL and ALGOTRONIX devices. The results of the benchmark experiments presented in the paper show that, in several cases, our method produces circuits of significantly reduced complexity compared to the solutions reported in the literature.

The bi-decomposition is a very powerful method to find an optimal multiple-level circuit structure that realizes a logic function. So far, the required simplification of the decomposition functions was realized in the strong bi-decomposition by reducing the number of variables. The completeness of this decomposition method was reached by the weak bi-decomposition. The drawback of the weak bi-decomposition is that different path lengths occur because the number of variables is only decreased for one of the two decomposition functions. In this paper, the method of bi-decomposition is extended by the vectorial bi-decomposition which utilized for the first time simpler decomposition functions which depend on all variables as the given function. It will be shown that vectorial bi-decompositions exist for functions for which no strong bi-decomposition is possible. Using the vectorial bi-decomposition together with the strong bi-decomposition, circuit structures can be found which have sho...

Lecture Notes in Computer Science, 2005

This paper describes a novel Field Programmable Gate Array (FPGA) logic synthesis technique which determines if a logic function can be implemented in a given programmable circuit and describes how this problem can be formalized and solved using Quantified Boolean Satisfiability. This technique is general enough to be applied to any type of logic function and programmable circuit; thus, it has many applications to FPGAs. The applications demonstrated in this paper include FPGA technology mapping and resynthesis where their results show significant FPGA performance improvements.

International Journal of Electronics and Telecommunications, 2011

Functional decomposition of Boolean functions specified by cubes proved to be very efficient. Most popular decomposition methods are based on blanket calculus. However computation complexity of blanket manipulations strongly depends on number of function's variables, which prevents them from being used for large functions of many input and output variables. In this paper a new concept of indexed partition is proposed and basic operations on indexed partitions are defined. Application of this concept to logic synthesis based on functional decomposition is also discussed. The experimental results show that algorithms based on new concept are able to deliver good quality solutions even for large functions and does it many times faster than the algorithms based on blanket calculus.

1995

One of the crucial problems multi-level logic synthesis techniques for multi-output boolean functions f = (f1; . . . ; fm) : f0; 1g n ! f0;1g m have to deal with is nding sublogic which can be shared by di erent outputs, i.e., nding boolean functions = ( 1; . . . ; h) : f0;1g p ! f0; 1g h which can be used as common sublogic of good realizations of f1; . . . ; fm. In this paper we present an e cient robdd based implementation of this Common Decomposition Functions Problem (cdf). The key concept of our method is the exploitation of equivalences of the functions f1; . . . ; fm which considerably reduces the running time of the tool. Formally, cdf is de ned as follows: Given m boolean functions f1; . . . ; fm : f0;1g n ! f0;1g, and two natural numbers p and h, nd h boolean functions 1; . . . ; h : f0;1g p ! f0;1g such that 81 k m there is a decomposition of fk of the form fk(x1; . . . ; xn) = g (k) ( 1(x1; . . . ; xp); . . . ; h(x1; . . . ; xp); (k) h+1 (x1; . . . ; xp); . . . ; (k) r k (x1; . . . ; xp); xp+1; . . . ; xn) using a minimal number rk of single-output boolean decomposition functions.

arXiv (Cornell University), 2023

The minimization of propositional formulae is a classical problem in logic, whose first algorithms date back at least to the 1950s with the works of Quine and Karnaugh. Most previous work in the area has focused on obtaining minimal, or quasi-minimal, formulae in conjunctive normal form (CNF) or disjunctive normal form (DNF), with applications in hardware design. In this paper, we are interested in the problem of obtaining an equivalent formula in any format, also allowing connectives that are not present in the original formula. We are primarily motivated in applying minimization algorithms to generate natural language translations of the original formula, where using shorter equivalents as input may result in better translations. Recently, Buchfuhrer and Umans have proved that the (decisional version of the) problem is Σ p 2-complete. We analyze three possible (practical) approaches to solving the problem. First, using brute force, generating all possible formulae in increasing size and checking if they are equivalent to the original formula by testing all possible variable assignments. Second, generating the Tseitin coding of all the formulae and checking equivalence with the original using a SAT solver. Third, encoding the problem as a Quantified Boolean Formula (QBF), and using a QBF solver. Our results show that the QBF approach largely outperforms the other two.

Progress in Artificial Intelligence, 2019

This paper proposes to study the synthesis of unordered binary decision diagrams (BDDs) using solvers for Quantified Boolean Formulas (QBF). The synthesis of a BDD falls naturally in the realm of quantified formulas as we are typically looking for a BDD satisfying a certain specification. This means that we ask whether there exists a BDD such that for all inputs the specification is satisfied. We show that this query can be encoded naturally into QBF and experimentally evaluate these queries for the minority function. The short paper should be seen as a challenge for further research on QBF solving.

In previous work ), a fast systematic method for minimization of the Boolean functions was presented. Such method is a simple because there is no need for any visual representation such as Karnough map or arrangement technique such as Tabulation method. Furthermore, it is suitable for boolean function with large number of variables (more than 4 variable). Moreover, it is very simple to understand and use. In this paper, the simplified functions are implemented with minimum amount of components. A powerful solution for realization of more complex functions is given. This is done by using modular neural nets (MNNs) that divide the input space into several homogenous regions. Such approach is applied to implement XOR functions, 16 logic function on one bit level, and 2-bit digital multiplier. Compared to previous non-modular designs, a clear reduction in the order of computations and hardware requirements is achieved.