Coping with latency in SOC design

arco.esi.uclm.es

In this work, we present an integrated approach to the SoC design problem based on a mixed (HW and SW) implementation of a system-level middleware specifically designed for SoCs: the Object-Oriented Communication Engine (OOCE). OOCE provides a high-level and homogeneous view of the SoC components based on the Distributed Object paradigm.

IEEE Design & Test of Computers, 2001

THE ADOPTION OF SYSTEM-ON-A-CHIP (SOC) architectures in future embedded-system designs will bring many advantages in terms of performance, cost, reliability, power consumption, and system size. However, to fully benefit from those advantages, designers must fine-tune the SOC architecture to suit application-specific characteristics and requirements. An application-specific multiprocessor SOC architecture (ASMSA) constitutes an ideal hardware platform since, in theory, it can be configured to fit the application's needs exactly. Such architectures allow many customizations. One of the most important design decisions is the topology and protocols chosen for communication between processors, memories, and peripherals. Achieving optimal ASMSA customization for complex applications is an overwhelming task because customizations are interdependent. Most researchers agree that independently refining communication and system behavior is a good strategy to reduce system design complexity and to achieve solutions that are sufficiently close to optimal. 1 This strategy leads naturally to a design flow in which the communication infrastructure and application code customizations follow independent paths during mapping of the system specification into an ASMSA. 2 The designer can perform these customizations concurrently if the design model separates communication and computation. A design representation for automating the ASMSA design flow must take these issues into account. The choices we have mentioned imply many trade-offs between design complexity, system performance, degree of automation, verification, and design reuse. A design model targeted at efficient ASMSA synthesis must support three main features: I Flexible communication modeling. The intrachip communication network must be modeled flexibly because application-specific optimizations might lead to a very complex architecture in which multiple topologies and protocols coexist. Furthermore, for flexibility's sake, communication models must not

2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012

Systems-on-chip (SoCs) contain multiple interconnected and interacting components. In this paper, we present a compositional approach for the integration of multiple components with a wide range of protocol mismatches into a single SoC. We show how SoC construction can be done in single-step when all components are integrated at once or it can also be performed incrementally by adding components to an already integrated design. Using a number of AMBA IPs, we show that the proposed framework is able to perform protocol conversion in many cases where existing approaches fail.

Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324), 2002

This paper presents a high-level component-based methodology and design environment for application-specific multicore SoC architectures. Component-based design provides primitives to build complex architectures from basic components. This bottomup approach allows design-architects to explore efficient custom solutions with best performances. This paper presents a high-level component-based methodology and design environment for application-specific multicore SoC architectures. The system specifications are represented as a virtual architecture described in a SystemC-like model and annotated with a set of configuration parameters. Our component-based design environment provides automatic wrapper-generation tools able to synthesize hardware interfaces, device drivers, and operating systems that implement a high-level interconnect API. This approach, experimented over a VDSL system, shows a drastic design time reduction without any significant efficiency loss in the final circuit.

ETRI Journal, 2005

2016

In this chapter we consider the issues related to integrating microarchitectural IP blocks into complex SoCs while satisfying performance, power, thermal, and reliability constraints. We first review different abstraction levels for SoC design that promote IP reuse, and which enable fast simulation for early functional validation of the SoC platform. Since SoCs must satisfy a multitude of interrelated constraints, we then present high-level power, thermal, and reliability models for predicting these constraints. These constraints are not unrelated and their interactions must be considered, modeled and evaluated. Once constraints are modeled, we must explore the design space trading off performance, power and reliability. Several case studies are presented illustrating how the design space can be explored across layers, and what modifications could be applied at design time and/or runtime to deal with reliability issues that may arise.

Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748)

In the system-on-chip (SOC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity under control. Intellectual property reuse has been commonly employed as a technique to address this problem, but a new system-level approach is needed to integrate IP-Reuse methodology in the designpow, in order to speed up the designer's productivity In this papec a SOC design plarform is proposed as a solution to this problem, pmviding a library ofIP reusable blocks and a high level tool for SOC design development. An IP library based on AMBA bus architecture was built, featuring a collection of devices with homogeneous interfaces described with VHDL language constructs that enable hardware configurabiliiy A system-level assembler (SL4) was then developed to provide a hardware con$guration tool and a suite of utilities to support the designer work. Once defrned the system structure, the SL4 allows automatic generation of the environments used for software development, simulation. synthesis and verification tasks.

2006 International Conference on Computer Engineering and Systems, 2006

Designing component-based SoC (System On Chip) has become a communication design problem. The reuse of Intellectual Property (IP) cores in Multiprocessor SoC is facilitated by the concept of packaging and wrapping. In this paper, we present an approach to automate the integration process of hardware accelerators/ coprocessors. This approach gives an interface modelling considering communication adaptation concepts/context throughout the integration steps. Graph formalism has been established to specify the interface considering the IP execution cycle accurate behaviour. This allows for automatic generation of interface architecture for simulation towards its synthesis. We illustrate the utility of the proposed framework that enables faster simulation times compared to existing methodologies which allow the designer to quickly evaluate alternative system implementations.

ACM Transactions on Design Automation of Electronic Systems, 2006

Continuous advancements in semiconductor technology enable the design of complex systems-on-chips (SoCs) composed of tens or hundreds of IP cores. At the same time, the applications that need to run on such platforms have become increasingly complex and have tight power and performance requirements. Achieving a satisfactory design quality under these circumstances is only possible when both computation and communication refinement are performed efficiently, in an automated and synergistic manner. Consequently, formal and disciplined system-level design methodologies are in great demand for future multiprocessor design. This article provides a broad overview of some fundamental research issues and state-of-the-art solutions concerning both computation and communication aspects of system-level design. The methodology we advocate consists of developing abstract application and platform models, followed by application mapping onto the target platform, and then optimizing the overall sys...

Proceedings of the ninth international symposium on Hardware/software codesign - CODES '01, 2001

In communication refinement with multiple communication protocols and abstraction levels, the system specification is described by heterogeneous components in terms of communication protocols and abstraction levels. To adapt each heterogeneous component to the other part of system, we present a generic wrapper architecture that can adapt different protocols or different abstraction levels, or both. In this paper, we give a detailed explanation of applying the generic wrapper architecture to mixed-level cosimulation. As preliminary experiments, we applied it to mixed-level cosimulation of an IS-95 CDMA cellular phone system. 1 Introduction In designing embedded multi-processor SoCs (systems-on-chip), communication refinement is one of crucial tasks since the communication implementation can have significant impact on system performance in terms of runtime, area, power consumption, etc. [1][2][3]. It is also a challenging task since complex functional and communication requirements of current embedded SoCs require application-specific processors (e.g. CPU's, DSP's, IP's, etc.) and high-performance/complex communication networks (e.g. giga bytelevel communication bandwidth, multi-point master/slave communication, etc.). To ease the complexity of communication refinement, most of current system design methods adopt design reuse and usage of multiple abstraction levels of communication [4][5][6][7][8][9]. In such design methods, during communication refinement, the system specification consists of heterogeneous components in terms of communication protocols and abstraction levels. For instance, since reused components such as IP's can have their own communication protocols that have already been fixed, the system specification, where IP's are connected with each other via a common communication resource (e.g. on-chip bus), has multiple communication protocols. System refinement with multiple abstraction levels can give an intermediate system specification that consists of subsystems or components at different abstraction levels. To integrate heterogeneous components within a system, wrappers have been widely used for simulation and synthesis [4][8][9] [10][11][12][13][14]. In simulation, for instance, BFM (bus functional model) encapsulates a functional model with a cycle-accurate interface [10][11]. BCASH (bus-cycle accurate shell) adapts RPC (remote procedural call) and cycle-accurate communication [8][9]. In [13] and [14], interfaces of mixed-level cosimulation are presented between protocol-fixed communication and cycle-accurate communication [13] and protocol-neutral and protocol-fixed communication [14]. In system synthesis, a bus wrapper, a processor template, or a protocol transducer is used to adapt a communication protocol of reused component to that of on-chip bus [4][6][7]. In [12], COSY communication IP's use a set of specific wrappers depending on the combinations of HW-SW mapping. Previous approaches to the usage of wrappers have limitations in that their application is limited (1) to either of simulation (e.g. BFM, BCASH, [13], and [14]) or synthesis (e.g. on-chip bus wrapper, [15], [16]), (2) to a specific pair of abstraction levels: e.g. BFM (between functional and cycle-accurate) and BCASH (between RPC and cycle-accurate), or (3) to a set of specific wrappers [12]. Compared to them, our contribution is to present a single generic wrapper architecture that is applicable (1) to both simulation and synthesis and (2) to various combinations of abstraction levels/ communication protocols. In this paper, we present a generic wrapper architecture and explain the details of applying the architecture to mixed-abstraction-level (in short, mixed-level) cosimulation. Its application to synthesis is presented in [17]. This paper is organized as follows. In Section 2, we introduce the generic wrapper architecture. In Section 3, we present our design flow. We explain the application of generic wrapper architecture to mixed-level cosimulation in Section 4. In Section 5, we give experimental results. We conclude this paper in Section 6.