Delay and Slew Metrics for On-Chip VLSI Interconnect

2010

Moments of the impulse response are widely used for interconnect delay analysis, from the explicit Elmore delay (the first moment of the impulse response) expression, to moment matching methods which creates reduced order trans-impedance and transfer function approximations. However, the Elmore delay is fast becoming ineffective for deep submicron technologies, and reduced order transfer function delays are impractical for use as early-phase design metrics or as design optimization cost functions. This paper describes an approach for fitting moments of the impulse response to probability density functions so that delay can be estimated accurately at an early physical design stage. For RC trees it is demonstrated that the incomplete gamma function provides a provably stable approximation. The accuracy of our model is justified with the results compared with that of SPICE simulations.

This paper describes an efficient threshold-based filtering algorithm (TFA) for calculating the interconnect delay and slew (transition time) in high-speed VLSI circuits. The key idea is to divide the circuit nets into three groups of low, medium and high complexity nets, whereby for low and medium complexity nets either the first moment of the impulse response or the first and second moments are used. For the high-complexity nets, which are encountered infrequently, TFA resorts to the AWE method. The key contribution of the paper is to come up with very effective and efficient way of classifying the nets into these three groups. Experimental results show that on a large industrial circuit using a state-of-the-art commercial timing analysis that incorporates TFA, we were able to achieve delay and slew estimation accuracies that are quite comparable with the full-blown AWE-based calculators at runtimes that were only 14% higher than those of a simple Elmore-delay calculator.

2004

This paper describes an efficient threshold-based filtering algorithm (TFA) for calculating the interconnect delay and slew (transition time) in high-speed VLSI circuits. The key idea is to divide the circuit nets into three groups of low, medium and high complexity nets, whereby for low and medium complexity nets either the first moment of the impulse response or the first and second moments are used. For the high-complexity nets, which are encountered infrequently, TFA resorts to the AWE method. The key contribution of the paper is to come up with very effective and efficient way of classifying the nets into these three groups. Experimental results show that on a large industrial circuit using a state-of-the-art commercial timing analysis that incorporates TFA, we were able to achieve delay and slew estimation accuracies that are quite comparable with the fullblown AWE-based calculators at runtimes that were only 14% higher than those of a simple Elmore-delay calculator.

Abstract This work presents an accurate and efficient model to compute the delay and slew metric of on-chip interconnect of high speed CMOS circuits foe ramp input. Our metric assumption is based on the Burr's Distribution function. The Burr's distribution is used to characterize the normalized homogeneous portion of the step response.

2004

In this paper we develop an approach to model interconnect delay under process variability for timing analysis and physical design optimization. The technique allows for closed-form computation of interconnect delay probability density functions (PDFs) given variations in relevant process parameters such as linewidth, metal thickness, and dielectric thickness. We express the resistance and capacitance of a line as a linear function of random variables and then use these to compute circuit moments. Finally, these variability-aware moments are used in known closedform delay metrics to compute interconnect delay PDFs. We compare the approach to SPICE based Monte Carlo simulations and report an error in mean and standard deviation of delay of 1% and 4% on average, respectively.

2012

Abstract—The Elmore delay is fast becoming ineffective for deep submicron technologies, and reduced order transfer function delays are impractical for use as early-phase design metrics or as design optimization cost functions. This paper describes an accurate approach for fitting moments of the impulse response to probability density functions so that delay and slew metric can be estimated accurately at an early physical design stage.

2006 IEEE/ACM International Conference on Computer Aided Design, 2006

Interconnects constitute a dominant source of circuit delay for modern chip designs. The variations of critical dimensions in modern VLSI technologies lead to variability in interconnect performance that must be fully accounted for in timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performance can dramatically complicate the timing analysis. In this paper, a practical interconnect delay and slew analysis technique is presented to facilitate efficient evaluation of wire performance variability. By harnessing a collection of computationally efficient procedures and closed-form formulas, process and input signal variations are directly mapped into the variability of the output delay and slew. Since our approach produces delay and slew expressions parameterized in the underlying process variations, it can be harnessed to enable statistical timing analysis while considering important statistical correlations. Our experimental results have indicated that the presented analysis is accurate regardless of location of sink nodes and it is also robust over a wide range of process variations.

Innovative Systems Design and Engineering, 2013

In high speed digital integrated circuits, interconnects delay can be significant and should be included for accurate analysis. Delay analysis for interconnect has been done widely by using moments of the impulse response, from the explicit Elmore delay (the first moment of the impulse response) expression, to moment matching methods which creates reduced order trans impedance and transfer function approximations. However, the Elmore delay is fast becoming ineffective for deep submicron technologies, and reduced order transfer function delays are impractical for use as early-phase design metrics or as design optimization cost functions. This paper describes an approach for fitting moments of the impulse response to probability density functions so that delay can be estimated accurately at an early physical design stage. For RC trees it is demonstrated that the inverse gamma function provides a provably stable approximation. We used the PERI [13] (Probability distribution function Extension for Ramp Inputs) technique that extends delay metrics for ramp inputs to the more general and realistic non-step inputs. The accuracy of our model is justified with the results compared with that of SPICE simulations.

2010

As technology scales down, timing verification of digital integrated circuits becomes an extremely difficult task due to statistical variations in the gate and wire delays. Statistical timing analysis techniques are being developed to tackle this problem. The variations of critical dimensions in modern VLSI technologies lead to variability in interconnect performance that must be fully accounted for the timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performances can dramatically complicate the timing analysis. For optimizations like physical synthesis and static timing analysis, efficient interconnect delay and slew computation is critical. Slew indicates the rate of change of input/output signals. Slew rate determines the ability of a device to handle the varying signals. Determination of slew rate to a good proximity is thus very much essential for efficient design of high speed CMOS integrated circuits as the increase in waveform slew directly enhances the delay of the interconnections. This work presents an accurate and efficient model to compute the slew metric of on-chip interconnect of high speed CMOS circuits. Our slew metric assumption is based on the Gamma Distribution Function. The gamma distribution is used to characterize the normalized homogeneous portion of the step response. For a generalized RC interconnect model, the stability of the Gamma Distribution model is guaranteed. The better accuracy is proved by comparing our approach with the established methods and SPICE results. It is shown that our approach could result in the error in slew calculation as low as 2% with lower value of driver resistance when compared with the SPICE results.

2019

Abstract: In recent days there is huge demand for highspeed VLSI networks. In order to judge the behavior ofon-chip interconnects the coupling capacitances andinterconnect delays plays a major role. As we switch tolower technology there is on-chip inductance effect thatleads to interconnect delay. In this paper we try to applysecond order transfer function designed with finitedifference equation and Laplace transform at the sourceand load termination ends. Analysis shows that currentmode signaling in VLSI interconnects provides timesbetter delay performance than voltage mode