Improving testability and soft-error resilience through retiming

IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016

With drastic device shrinking, low operating voltages , increasing complexities, and high speed operations, radiation-induced soft errors have posed an ever increasing reliability challenge to both combinational and sequential circuits in advanced CMOS technologies. Therefore, it is imperative to devise efficient soft error rate (SER) estimation methods, in order to evaluate the soft error vulnerabilities for cost-effective robust circuit design. Previous works either analyze only SER in combinational circuits or evaluate soft error vulnerabilities in sequential elements. In this paper, a joint SER estimation framework is proposed, which considers single-event transients (SETs) in combinational logic and multiple cell upsets (MCUs) in sequential components. Various masking effects are considered in the combinational SER estimation process, and several typical radiation-hardened and non-hardened flip-flop structures are analyzed and compared as the sequential elements. A schematic and layout co-simulation approach is proposed to model the MCUs for redundant sequential storage structures. Experimental results of a variety of ISCAS benchmark circuits using the Nangate 45nm CMOS standard cell library demonstrate the difference in soft error resilience among designs using different sequential elements and the importance of modeling MCUs in redundant structures. Keywords—Soft error, hardened flip-flop, single-event upset, multiple cell upset.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993

We address the problems of test generation and synthesis aimed at producing VLSI sequential circuits that are delay-fault testable under a standard scan design methodology. We begin with theoretical results regarding the standard-scan delay testability of finite state machines (FSM's) described at the state transition graph (STG) level. We show that a one-hot coded and optimized FSM whose STG satis6es a certain property is guaranteed to be fully gate-delay-fault testable under standard scan. We extend this result to arbitrary-length encodings and develop a heuristic state assignment algorithm that results in highly gate-delay-fault testable sequential FSMs, which are also area-efficient, as evinced by results obtained on benchmark FSM circuits.

Journal of Systems Architecture, 2001

We propose a testability enhancement technique for delay faults in standard scan circuits that does not involve modi®cations to the scan chain. Extra logic is placed on next-state variables, and if necessary, on primary inputs, and can be resynthesized with the circuit to minimize its hardware and performance overheads. The proposed technique allows us to achieve complete coverage of detectable delay faults by allowing any two-pattern test to be applied to the circuit through its functional path. In addition to the basic approach, we study the proposed procedure in the presence of a constraint that requires that extra logic would not be placed on the critical paths of the circuit. Ó

IPSJ Digital Courier, 2006

We propose a non-scan design-for-testability (DFT) method at register-transfer level (RTL) based on hierarchical test generation: the DFT method makes paths in a data path singleport-change (SPC) two-pattern testable. For combinational logic in an RTL circuit, an SPC two-pattern test launches transitions at the starting points of paths corresponding to only one input port (an input, which has some bits, of an RTL module) and sets the other ports stable. Hence, during test application, the original hold function of a register can be used for stable inputs if the hold function exists. Our DFT method can reduce area overhead compared to methods that support arbitrary two-pattern tests without losing the quality of robust test and non-robust test. Experimental results show that our method can reduce area overhead without losing the quality of test. Furthermore, we propose a method of reducing over-test by removing a subset of sequentially untestable paths from the target of test.

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 2002

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005

Sequential elements, flip-flops, latches, and memory cells, are the most vulnerable components to soft errors. Since state-of-the-art designs contain millions of bistables, it is not feasible to protect all system bistables using hardening techniques that impose area, performance, and power overhead. A practical approach is to rank system bistables based on their contribution to the overall system vulnerability and protect the most problematic bistables. This analysis is traditionally performed by fault injection and simulation methods which are intractable for large designs and multi-cycle analysis. In this paper, we present an analytical framework to analyze multi-cycle error propagation behavior and then rank system bistables based on their effects on system-level soft error rate. The number of clock cycles required for an error in a bistable to be propagated to system outputs is used to measure the vulnerability of bistables to soft errors.

2004 International Conferce on Test, 2004

This paper presents ~ a novel technique io identi& functionally untestable transition faults in latch based designs wiih multiple clock domains. bringing to light unaddressed issues related to untestable fault identification in such design enviranmenis. We also introduce and provide a solution to a new variant of un-testabili@ analysis wherein "archiieciural consfrainis '' are absorbed during the analysis. We give our tool the capability of handling transition faults resulting from defcts of varying sizes, and evaluate our tool for various industrial circuits. The proposed algorithm is compared with a state-of-the-art sequential ATPG tool, and our method has shown much better perfonnance bath in the context of scan ATPG and functional test development. Results indicate that the proposed technique identijes considerably more untestable transition faults than those that can be deduced from the knowledge of untestable stuck-at faults. Additional insights from our results point to a greaier need to eliminate untestable transition faults as compared la stuck-at faults, for more efficient iesi patiem generation and accurate coverage compuiation. Paper 36.2 1034 ITC INTERNATIONAL TEST CONFERENCE 0-78058580-2/04 520.00 Copyright XI04 IEEE Authorized licensed use limited to: IEEE Xplore. Downloaded on January 14, 2009 at 09:42 from IEEE Xplore. Restrictions apply.

2008

Abstract Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking mechanisms: logic, timing and electrical. Most previous papers focus on logic and electrical masking. Here, we develop static and statistical analysis techniques to estimate timing masking through the error-latching window of each gate.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991

It is known that circuit delays and timing skews in input vector changes influence choice of tests to detect delay faults. Tests for stuck-open faults in CMOS logic circuits can also be invalidated by circuit delays and timing skews in input vector changes. Tests that detect modeled faults independent of the delays in the circuit under test are called robust tests. In this paper we propose an integrated approach to the design of combinational logic circuits in which all path delay faults and multiple line stuck-at, transistor stuck-open faults are detectable by robust tests. We also demonstrate that the proposed method guarantees the design of CMOS logic circuits in which all path delay faults are locatable.

Proceedings of the 2003 IEEE/ACM …, 2003

Design-for-testability (DFT ) for synchronous sequential circuits causes redundant faults in the original circuit to be detectable in the circuit with DFT logic. It has been argued that such faults should not be detected in order to avoid reducing the yield unnecessarily. One way to deal with such faults is to mask (or ignore) their fault effects when they appear on the circuit outputs, without masking the detection of faults that need to be detected. To investigate the extent to which this can be accomplished, we describe a procedure for masking the effects of redundant faults of the original circuit under a given test set generated for the circuit with DFT logic. The procedure attempts to maximize the number of redundant faults that are masked while minimizing (or holding to zero) the number of other masked faults.

1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

In this paper, we consider the problem of generating small (compact) test sets for single transition and CMOS stuck-open faults in combinational logic circuits. In addition, we propose that to generate test sets that cover a wide range of physical defects, a test set to detect faults of different models should be derived. Specifically, we address the problem of generating small and comprehensive test sets by considering the CMOS stuck-open and the single transition fault models together. We propose a dynamic test compaction technique for two-pattern tests, which exploits the test compaction strategies developed for stuck-at faults, and performs dynamic test vector overlap to derive small test sets. We present experimental results for ISCAS-85 combinational circuits and fully scanned versions of ISCAS-89 sequential circuits to illustrate the efficacy of the proposed test compaction technique.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1997

Recently, it has been shown that retiming has a very strong impact on the run time required for sequential, structural automatic test pattern generators (ATPG's), as well as the levels of fault coverage and fault efficiency attained. In this paper, we show that, for circuits with no hardware reset or a global reset state, retiming preserves testability with respect to a single stuckat fault test set by adding a prefix sequence of a predetermined number of arbitrary input vectors. We show that this result holds for test sets derived based on structural and functional methods, and based on the conventional and multiple observation time testing strategies. Furthermore, we derive the conditions under which synchronizing sequences are preserved under retiming. We show that a structural synchronizing sequence for a circuit drives any of its corresponding retimed circuits to an equivalent state. In addition, we show that functional synchronizing sequences are preserved under retiming by adding a prefix sequence of a predetermined number of arbitrary input vectors. The impact of retiming on ATPG complexity and test-set preservation under retiming suggest a new approach for enhancing the performance of structural, sequential ATPG's. Experimental results show that high fault coverages can be achieved on high-performance circuits optimized by retiming with much less CPU time (a reduction of two orders of magnitude in several instances) than if ATPG is attempted directly on those circuits.

IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings., 2000

Abstracr-Sofi the critical charge hy increasing the gate capacitance while errors are gaining importance as technology scales. Flip-flops, an important component of pipelined architectures, are becoming more susceptible to soft errors. This work analyzes soft error rates on a variety of flip-flops. The analysis was performed hy implementing and simulating the various designs in 70 nm, 1V CMOS technology. First, we evaluate the critical charge for the snsceptihle nodes in each design. Further, we implement two hardening techniques and present the results. One attempts to increase the other improves the overall robustness of the circuit by replicating the master stage of the master slave nip-flops, which leads to reduced power and area overhead. 0-7803-8182-3/03/$17.00 02003 IEEE

Proceedings European Design and Test Conference. ED & TC 97

Microelectronics Journal, 2003

We propose a possible modification to the internal structure of scan flip-flops, which allows the online detection of delay and crosstalk faults affecting their input. Our solution allows to obtain, together with the flip-flop output datum, an indication denoting whether or not the provided datum is incorrect, because of an input crosstalk or delay fault. The proposed solution features self-checking ability with respect to a wide set of possible internal faults, including node stuck-ats, transistor stuck-ons and stuck-opens, resistive bridgings, delays, transient and crosstalk faults. q