Robust SRAM Design via BIST-Assisted Timing-Tracking (BATT)

2014 Annual IEEE India Conference (INDICON), 2014

This work proposed an on-chip architectural design, validation and feasibility of a BIST for 8x8 SRAM using 0.18 µm UMC technology in Cadence Virtuoso and Spectre Tool for storage and retrieval faults detection. As, the technology shrinks and share of memories in complex systems increases, memories become susceptible to faults. Storage and retrieval faults are genuinely faced by SRAM. This type of fault occurs due to improper storage or retrieval of data i.e. breakage in the word line or in bit line. Thus, it become a major issue for test engineers, as area overhead is a constraint. From the results obtained, it has been observed that the proposed architecture, for detecting the storage and retrieval faults is working properly but the area and power due to BIST is increased with comparison to the circuit under test alone. The feasibility of proposed BIST architecture is checked by calculating the area and power overhead of BIST for large size memories.

SRAM design is very crucial since it takes a large fraction of total power and die area in high-performance processors. The performance of embedded memory and its peripheral circuits can adversely affect the speed and power of the overall system. This paper explores the design of SRAM focusing on optimizing delay, reducing power and layout area. A full-custom layout is drawn to achieve minimum area and power. The key to low power operation of the design is self-timed architecture, multi stage decodingand full custom layout. The robustness of this design is verified by analysing the memory at wide PVT range. This memory is verified at a temperature range of -40ºC to 125ºC.A 1024x16 SRAM is designed at UMC 180 nm technology. The post-layout behavior of this SRAM is analyzed at different PVT conditions. The dynamic power achieved is 19.74uW at 1MHz frequency at TT_1v_25C. The leakage current of single 6T bit-cell is 4.02pA at TT_1v_25C. The leakage power is 53.57nW at TT_1v_25C. The access time obtained is 5ns at TT_1v_25C.

2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017

Static Random Access Memories (SRAMs) are considered a major bottleneck in high performance System-on-Chip (SoC) design and there is a large demand for high performance SRAMs with minimal energy consumption. Time speculation techniques such as Razor ease timing guardbands to improve performance or reduce energy consumption. The state-of-the-art approach has high area and energy overheads due to the error detection logic. This study proposes a timing speculative SRAM that extends the existing Replica Bitline Column to detect read timing failures. We also extend the SRAM decode logic to protect from incorrect write operations. We demonstrate our Replica-based Timing Speculative SRAM (RTS) is an energy and area efficient design alternative to prior techniques such as Razor. Our proposed design is 22% to 58% more energy efficient in reading operations and it has an error detection mechanism which is 35% to 73% more area efficient that Razor-enabled SRAM.

2012

Abstract—Memories are one of the most universal cores. On average embedded RAMs occupy 90 % area in system-on-chip (SOC), so embedded memory test design has become an essential part of the SOC development infrastructure. Here we designed reusable memory built in self test (MBIST) engine for memory test, which also gives useful information for fault diagnosis. A simple architecture for built in self repair is implemented. Integrating BISR in MBIST improves the chip yield. SOC consists of many memory models. Like, SRAM, FLASH, ROM etc, we consider here only SRAM type of memory core.Here we will see what the functional model of SRAM is and what types of Functional Faults, Fault Models and Defects exist in SRAM cores due to process variation and manufacturing. xilinx spartan3E tool used for synthesise and simulation.

Built-in self-test (BIST) refers to those testing techniques where additional hardware is added to a design so that testing is accomplished without the aid of external hardware. Usually, a pseudo-random generator is used to apply test vectors to the circuit under test and a data compactor is used to produce a signature.

IAEME PUBLICATION

Memory arrays are an essential building block in any digital system. Static random-access memory (SRAM or static RAM) is a type of semiconductor memory that uses bistable latching circuitry to store each bit. The term static differentiates it from dynamic RAM (DRAM) which must be periodically refreshed. SRAM exhibits data remanence, but it is still volatile in the conventional sense that data is eventually lost when the memory is not powered. The aspects of designing an SRAM are very vital to designing other digital circuits as well. The majority of space taken in an integrated circuit is the memory. SRAM design consists of key considerations, such as increased speed and reduced layout area. This paper is aimed at creating an efficient SRAM design using Cadence. The focus was on developing simplified design by reducing the transistor count and replacing some of the conventional circuit designs.

2009

As the memory enters submicron technology, new test algorithm that will be able to give a better fault coverage such as to detect all intra-word coupling fault (CF) has been widely developed. In order to implement this algorithm to the memory, test technique such as BIST is utilized. Common types of memory built-in-self test (MBIST); microcode-based MBIST and FSM-based MBIST. The popular approach of designing various kind of MBIST architectures are either by targeting to reach specific testing requirement such as on full speed and at speed or by considering the cost-constraint and area overhead such low-cost or low-area design. In this paper, FSM-based BIST is designed to be able detecting all intra-word coupling fault (CF) in a synchronous SRAM under low-area constraint of test requirement.

2012 IEEE International SOC Conference, 2012

This paper describes an area-efficient variation-tolerant data-aware dynamic supply Write-assist scheme for a cross-point 8T SRAM. A 128Kb test chip implemented in 55nm Standard Performance CMOS technology achieves error free full functionality without redundancy from 1.5V down to 0.5V, with area overhead of only 0.834% for the Data-Aware Write-Assist (DAWA). The superiority of the proposed scheme in area overhead and improvement in Write V MIN and Write bit failure rate are demonstrated via comparison of measurement results with that from a base 128Kb design with Negative Bit-Line (NBL) Write-assist scheme. The maximum operating frequency is 494MHz (271 MHz) at 0.6V (0.5V).

International Journal of Engineering Research and Technology (IJERT), 2013

Fpga implementation of efficient built in self repair strategy for embedded sram IJERTV2IS https://www.ijert.org/research/fpga-implementation-of-efficient-built-in-self-repair-strategy-for-embedded-sram-IJERTV2IS100330.pdf Built-In Self-Repair (BISR) with Redundancy is an effective yield-enhancement strategy for embedded memories. This paper proposes an efficient BISR strategy which consists of a Built-In Self-Test (BIST) module, a Built-In Address-Analysis (BIAA) module and a Multiplexer (MUX) module. The BISR is designed flexible that it can provide four operation modes to SRAM users. Each fault address can be saved only once is the feature of the proposed BISR strategy. In BIAA module, fault addresses and redundant ones form a one-to-one mapping to achieve a high repair speed. Besides, instead of adding spare words, rows, columns or blocks in the SRAMs, users can select normal words as redundancy. The selectable redundancy brings no penalty of area and complexity and is suitable for compiler design. A practical 4K × 32 SRAM IP with BISR circuitry is designed and implemented based on a 55nm CMOS process. Experimental results show that the BISR occupies 20% area and can work at up to 150MHz.