{"title":"Cryptech Project - misc","link":[{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/","rel":"alternate"}},{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/feeds\/misc.atom.xml","rel":"self"}}],"id":"https:\/\/wiki.cryptech.is\/","updated":"2021-10-07T18:55:00+00:00","entry":[{"title":"Trac Wiki converted to Pelican Markdown","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/Pelican","rel":"alternate"}},"published":"2021-10-07T18:55:00+00:00","updated":"2021-10-07T18:55:00+00:00","author":{"name":"Cryptech Core Team"},"id":"tag:wiki.cryptech.is,2021-10-07:\/Pelican","summary":"<p>The Trac Wiki that used to hold this site has been converted to a\nwiki-like setup using git, Markdown, Pelican, and m.css.<\/p>\n<ul>\n<li><a href=\"https:\/\/git.cryptech.is\/wiki\">git repository behind this Wiki<\/a>.<\/li>\n<li><a href=\"https:\/\/docs.getpelican.com\/en\/stable\/\">Pelican documentation<\/a>.<\/li>\n<li><a href=\"https:\/\/mcss.mosra.cz\/themes\/pelican\/\">m.css documentation<\/a>.<\/li>\n<\/ul>\n<p>The git repository is configured to generate the web content from the\nMarkdown automatically upon receiving a \u2026<\/p>","content":"<p>The Trac Wiki that used to hold this site has been converted to a\nwiki-like setup using git, Markdown, Pelican, and m.css.<\/p>\n<ul>\n<li><a href=\"https:\/\/git.cryptech.is\/wiki\">git repository behind this Wiki<\/a>.<\/li>\n<li><a href=\"https:\/\/docs.getpelican.com\/en\/stable\/\">Pelican documentation<\/a>.<\/li>\n<li><a href=\"https:\/\/mcss.mosra.cz\/themes\/pelican\/\">m.css documentation<\/a>.<\/li>\n<\/ul>\n<p>The git repository is configured to generate the web content from the\nMarkdown automatically upon receiving a <code>git push<\/code>. <\/p>\n<p><a href=\"https:\/\/linkcheck.github.io\/linkchecker\/\">linkchecker<\/a> may also be\nuseful in validating the generated content.<\/p>","category":{"@attributes":{"term":"misc"}}},{"title":"External Project Tor HSM","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/ExternalProjectsTorHSM","rel":"alternate"}},"published":"2018-09-17T10:26:00+00:00","updated":"2018-10-01T14:38:00+00:00","author":{"name":"Linus Nordberg"},"id":"tag:wiki.cryptech.is,2018-09-17:\/ExternalProjectsTorHSM","summary":"<h2>Problem<\/h2>\n<p>The <a href=\"https:\/\/www.torproject.org\/about\/overview.html.en\">Tor network<\/a> is defined by a small number, about ten, of special relays called Directory Authorities (DAs).<\/p>\n<p>Directory Authorities sign the critical <code>status votes<\/code> and <code>consensus status<\/code> documents using SHA-1 and SHA-256 together with RSA-2048 or RSA-3072 once per hour, using medium-term on-line <code>authority signing keys<\/code> signed by \u2026<\/p>","content":"<h2>Problem<\/h2>\n<p>The <a href=\"https:\/\/www.torproject.org\/about\/overview.html.en\">Tor network<\/a> is defined by a small number, about ten, of special relays called Directory Authorities (DAs).<\/p>\n<p>Directory Authorities sign the critical <code>status votes<\/code> and <code>consensus status<\/code> documents using SHA-1 and SHA-256 together with RSA-2048 or RSA-3072 once per hour, using medium-term on-line <code>authority signing keys<\/code> signed by their individual off-line long-term <code>authority identity keys<\/code>. Authority signing keys typically have a lifetime of three to twelve months.<\/p>\n<p>Authority signing keys are currently kept on the same general purpose computer that runs the Directory Authority and are thus subject to a large number of network threats.<\/p>\n<h2>Proposed solution<\/h2>\n<p>Move <code>authority signing keys<\/code> away from the general purpose computer onto an external device which can sign the consensus document without exposing key material to the networked computer system.<\/p>\n<p>The CrypTech project has created an open source (BSD licensed) <code>Alpha<\/code> hardware which would be especially suitable, because the open software and hardware offers unprecedented transparency while also enabling a simple, efficient and legacy-free solution.<\/p>\n<h3>Current typical key roll-over procedure<\/h3>\n<ul>\n<li>Generate new <code>authority signing key<\/code> on offline system<\/li>\n<li>Sign new key using <code>authority identity key<\/code> on offline system<\/li>\n<li>Save new <code>authority signing key<\/code> and <code>key certificate<\/code> on USB stick<\/li>\n<li>Transfer new <code>authority signing key<\/code> and <code>key certificate<\/code> to DA system via network<\/li>\n<\/ul>\n<h3>The key roll-over procedure becomes<\/h3>\n<ul>\n<li>Use administrative tool from this project on DA system to generate new <code>authority signing key<\/code> on HSM<ul>\n<li>The new <code>authority signing key<\/code> initially remains inactive and unavailable for use<\/li>\n<li>The public part of new <code>authority signing key<\/code> is exported from HSM onto the DA system<\/li>\n<\/ul>\n<\/li>\n<li>Transfer new public part of <code>authority signing key<\/code> to USB stick<\/li>\n<li>Sign new public key using <code>authority identity key<\/code> on offline system<\/li>\n<li>Save <code>key certificate<\/code> on USB stick<\/li>\n<li>Transfer <code>key certificate<\/code> to DA system via network and make available to DA<\/li>\n<li>(Optional?) Use administrative tool from this project on DA to present <code>key certificate<\/code> to HSM<\/li>\n<li>Activate key (automatic on verified <code>key certificate<\/code>, manual without <code>key certificate<\/code> verification)<\/li>\n<\/ul>\n<h2>Milestones<\/h2>\n<p>The minimum viable product (MVP) at MS3 is a system where the authority signing key is no longer accessible by the DA system while not making any part of the process worse from a security perspective.<\/p>\n<p>The system at MS6 (to MS8) does not make any part of the process worse from a \/\/usability\/\/ perspective (subjective) and also adds rate limiting.<\/p>\n<h3>MS1 -- PoC using OpenSSL <code>PKCS#11<\/code> engine<\/h3>\n<ul>\n<li>tor using openssl p11 engine; no key management or rate-limiting<\/li>\n<li>useful for test and verification<\/li>\n<\/ul>\n<h3>MS2 -- Using CrypTech RPC instead of OpenSSL<\/h3>\n<ul>\n<li>function declarations in <code>sw\/libhal\/hal.h<\/code>, definitions in <code>sw\/libhal\/rpc_*.c<\/code><\/li>\n<li>TODO: daemon<\/li>\n<\/ul>\n<h3>MS3 (MVP) -- HSM configuration I<\/h3>\n<ul>\n<li>\"HSM configuration\" is aka \"key management\"<\/li>\n<li>administrator connected to MGMT can make HSM<ul>\n<li>generate a MK based on passphrase<\/li>\n<li>print public part of MK<\/li>\n<\/ul>\n<\/li>\n<li>administrator connected to USER can make HSM<ul>\n<li>generate a new authority signing key pair, wrap the secret part in MK, store both parts in flash memory and export the public part<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<h3>MS4 -- HSM configuration II<\/h3>\n<ul>\n<li>rate limiting<\/li>\n<li>enforcing key validity<\/li>\n<\/ul>\n<h3>MS5 -- Enforcing key validity HSM side<\/h3>\n<h3>MS6 -- Rate limiting of signatures<\/h3>\n<h3>MS7 -- New Shiny Crypto Hardware API using CrypTech RPC<\/h3>\n<h3>MS8 -- Getting entropy from HSM<\/h3>\n<h3>MS9 -- Support for more protocols in New Shiny Crypto Hardware API<\/h3>\n<h2>References<\/h2>\n<ul>\n<li><a href=\"https:\/\/gitweb.torproject.org\/torspec.git\/tree\/dir-spec.txt\">Tor directory protocol, version 3<\/a><\/li>\n<li><a href=\"https:\/\/www.crowdsupply.com\/cryptech\/open-hardware-security-module\">CrypTech Alpha system<\/a><\/li>\n<\/ul>","category":{"@attributes":{"term":"misc"}}},{"title":"External Projects","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/ExternalProjects","rel":"alternate"}},"published":"2018-09-17T10:12:00+00:00","updated":"2018-09-17T10:27:00+00:00","author":{"name":"Cryptech Core Team"},"id":"tag:wiki.cryptech.is,2018-09-17:\/ExternalProjects","content":"<p>External projects using <a href=\"https:\/\/cryptech.is\/\">CrypTech<\/a> technology.<\/p>\n<ul>\n<li><a href=\"https:\/\/wiki.cryptech.is\/ExternalProjectsTorHSM\">TorHSM<\/a><\/li>\n<\/ul>","category":{"@attributes":{"term":"misc"}}},{"title":"Project Status Dashboard","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/Dashboard","rel":"alternate"}},"published":"2016-12-15T22:44:00+00:00","updated":"2016-12-15T22:44:00+00:00","author":{"name":"Cryptech Core Team"},"id":"tag:wiki.cryptech.is,2016-12-15:\/Dashboard","summary":"<h2>Product Component Requirements<\/h2>\n<table>\n<thead>\n<tr>\n<th>State<\/th>\n<th>Component<\/th>\n<th>DNSsec Signing<\/th>\n<th>Let's Encrypt<\/th>\n<th>Tor Consensus<\/th>\n<th>Internal<\/th>\n<th>Ticket<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>Done<\/td>\n<td>AES \/ KEY WRAP<\/td>\n<td><\/td>\n<td><\/td>\n<td><\/td>\n<td>Wrap\/Bkup<\/td>\n<td>#17<\/td>\n<\/tr>\n<tr>\n<td><\/td>\n<td>ECDSA p256<\/td>\n<td>secondary<\/td>\n<td>Yes<\/td>\n<td><\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td><\/td>\n<td>ECDSA p384<\/td>\n<td>secondary<\/td>\n<td>?<\/td>\n<td><\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>Testing<\/td>\n<td>PKCS#11<\/td>\n<td>Yes<\/td>\n<td>Yes<\/td>\n<td>Yes<\/td>\n<td>Yes<\/td>\n<td>#14<\/td>\n<\/tr>\n<tr>\n<td>Done<\/td>\n<td>RSA<\/td>\n<td>Yes<\/td>\n<td>Yes<\/td>\n<td>Yes<\/td>\n<td><\/td>\n<td>#16<\/td>\n<\/tr>\n<tr>\n<td>Done<\/td>\n<td>SHA-1<\/td>\n<td><\/td>\n<td><\/td>\n<td>Yes<\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>Done<\/td>\n<td>SHA-256<\/td>\n<td>Yes<\/td>\n<td>Yes<\/td>\n<td>Yes<\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>Done \u2026<\/td><\/tr><\/tbody><\/table>","content":"<h2>Product Component Requirements<\/h2>\n<table>\n<thead>\n<tr>\n<th>State<\/th>\n<th>Component<\/th>\n<th>DNSsec Signing<\/th>\n<th>Let's Encrypt<\/th>\n<th>Tor Consensus<\/th>\n<th>Internal<\/th>\n<th>Ticket<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>Done<\/td>\n<td>AES \/ KEY WRAP<\/td>\n<td><\/td>\n<td><\/td>\n<td><\/td>\n<td>Wrap\/Bkup<\/td>\n<td>#17<\/td>\n<\/tr>\n<tr>\n<td><\/td>\n<td>ECDSA p256<\/td>\n<td>secondary<\/td>\n<td>Yes<\/td>\n<td><\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td><\/td>\n<td>ECDSA p384<\/td>\n<td>secondary<\/td>\n<td>?<\/td>\n<td><\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>Testing<\/td>\n<td>PKCS#11<\/td>\n<td>Yes<\/td>\n<td>Yes<\/td>\n<td>Yes<\/td>\n<td>Yes<\/td>\n<td>#14<\/td>\n<\/tr>\n<tr>\n<td>Done<\/td>\n<td>RSA<\/td>\n<td>Yes<\/td>\n<td>Yes<\/td>\n<td>Yes<\/td>\n<td><\/td>\n<td>#16<\/td>\n<\/tr>\n<tr>\n<td>Done<\/td>\n<td>SHA-1<\/td>\n<td><\/td>\n<td><\/td>\n<td>Yes<\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>Done<\/td>\n<td>SHA-256<\/td>\n<td>Yes<\/td>\n<td>Yes<\/td>\n<td>Yes<\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>Done<\/td>\n<td>SHA-384<\/td>\n<td>Yes<\/td>\n<td>?<\/td>\n<td><\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>Done<\/td>\n<td>TRNG<\/td>\n<td>padding<\/td>\n<td>padding<\/td>\n<td>padding<\/td>\n<td>KeyGen<\/td>\n<td>#15<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2>Novena Alpha - DNSsec Only<\/h2>\n<table>\n<thead>\n<tr>\n<th>Component<\/th>\n<th>Who<\/th>\n<th>About When<\/th>\n<th>Ticket<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>RSA<\/td>\n<td>Pavel, Rob<\/td>\n<td>Done<\/td>\n<td>#16<\/td>\n<\/tr>\n<tr>\n<td>AES\/KEY WRAP<\/td>\n<td>Rob<\/td>\n<td>Done<\/td>\n<td>#17<\/td>\n<\/tr>\n<tr>\n<td>SHA-256<\/td>\n<td>Joachim<\/td>\n<td>Done<\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>TRNG<\/td>\n<td>FT<\/td>\n<td>Done<\/td>\n<td>#15<\/td>\n<\/tr>\n<tr>\n<td>PKCS#11<\/td>\n<td>Rob<\/td>\n<td>Late May<\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>PKCS#11 PIN<\/td>\n<td>Rob<\/td>\n<td>Mid June<\/td>\n<td>#14<\/td>\n<\/tr>\n<tr>\n<td>Packaging<\/td>\n<td>Paul, Rob<\/td>\n<td>Done<\/td>\n<td><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2>Hardware cores<\/h2>\n<h3>Hash Functions<\/h3>\n<table>\n<thead>\n<tr>\n<th>Component<\/th>\n<th>Status<\/th>\n<th>Repository<\/th>\n<th>Comment<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>SHA-1<\/td>\n<td>Done<\/td>\n<td><a href=\"https:\/\/git.cryptech.is\/core\/hash\/sha1\/about\">core\/hash\/sha1<\/a><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>SHA-256<\/td>\n<td>Done<\/td>\n<td><a href=\"https:\/\/git.cryptech.is\/core\/hash\/sha256\/about\">core\/hash\/sha256<\/a><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>SHA-512<\/td>\n<td>Done<\/td>\n<td><a href=\"https:\/\/git.cryptech.is\/core\/hash\/sha512\/about\">core\/hash\/sha512<\/a><\/td>\n<td>Support all four SHA-512\/x modes defined in FIPS 180-4.<\/td>\n<\/tr>\n<tr>\n<td>SHA-3 (Keccak )<\/td>\n<td>Started<\/td>\n<td><a href=\"https:\/\/git.cryptech.is\/core\/hash\/sha3\/about\">core\/hash\/sha3<\/a><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>GOST R 34.11-2012<\/td>\n<td>Started<\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h3>Symmetric Crypto<\/h3>\n<table>\n<thead>\n<tr>\n<th>Component<\/th>\n<th>Status<\/th>\n<th>Repository<\/th>\n<th>Comment<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>AES<\/td>\n<td>Done<\/td>\n<td><a href=\"https:\/\/git.cryptech.is\/core\/cipher\/aes\/about\">core\/cipher\/aes<\/a><\/td>\n<td>AES cipher core with support for 128 and 256 bit keys.<\/td>\n<\/tr>\n<tr>\n<td>ChaCha<\/td>\n<td>Done<\/td>\n<td><a href=\"https:\/\/git.cryptech.is\/core\/cipher\/chacha\/about\">core\/cipher\/chacha<\/a><\/td>\n<td>High speed stream cipher. Based on the Salsa20 stream cipher.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h3>Asymmetric Crypto<\/h3>\n<table>\n<thead>\n<tr>\n<th>Component<\/th>\n<th>Status<\/th>\n<th>Repository<\/th>\n<th>Comment<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>ModExp -8192 (RSA)<\/td>\n<td>Done<\/td>\n<td><a href=\"https:\/\/git.cryptech.is\/core\/math\/modexps6\/about\">core\/math\/modexps6<\/a><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>Curve25519<\/td>\n<td>Started<\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>Ed25519<\/td>\n<td>Not started<\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>P-256, P-384 ECDSA<\/td>\n<td>Started<\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>GOST R 34.10-2001<\/td>\n<td>Started<\/td>\n<td><a href=\"https:\/\/git.cryptech.is\/user\/shatov\/gost\/streebog\">https:\/\/git.cryptech.is\/user\/shatov\/gost\/streebog<\/a><\/td>\n<td>Core in provisional repo. Will be moved to the the hash core section.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h3>Random Number Generators<\/h3>\n<table>\n<thead>\n<tr>\n<th>Component<\/th>\n<th>Status<\/th>\n<th>Repository<\/th>\n<th>Comment<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>TRNG<\/td>\n<td>Done<\/td>\n<td><a href=\"https:\/\/git.cryptech.is\/core\/rng\/trng\/about\">core\/rng\/trng<\/a><\/td>\n<td>Depends on SHA-512 and ChaCha<\/td>\n<\/tr>\n<tr>\n<td>External Avalanche Entropy<\/td>\n<td>Done<\/td>\n<td><a href=\"https:\/\/git.cryptech.is\/core\/rng\/avalanche_entropy\/about\">core\/rng\/avalanche_entropy<\/a><\/td>\n<td><a href=\"https:\/\/git.cryptech.is\/user\/ft\/stm32-avalanche-noise\/about\">Hardware<\/a> and stand-alone PoC<\/td>\n<\/tr>\n<tr>\n<td>Internal Ring Oscillator<\/td>\n<td>Done<\/td>\n<td><a href=\"https:\/\/git.cryptech.is\/core\/rng\/rosc_entropy\/about\">core\/rng\/rosc_entropy<\/a><\/td>\n<td><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h3>Key wrapping and Cipher Modes<\/h3>\n<table>\n<thead>\n<tr>\n<th>Component<\/th>\n<th>Status<\/th>\n<th>Repository<\/th>\n<th>Comment<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>KEY WRAP<\/td>\n<td>Done<\/td>\n<td><\/td>\n<td>Key wrapping mode. Will be used for key storage. See <a href=\"https:\/\/tools.ietf.org\/html\/rfc3394\">rfc 3394<\/a>. #17<\/td>\n<\/tr>\n<tr>\n<td>GCM<\/td>\n<td>Not started<\/td>\n<td><\/td>\n<td>Galois Counter Mode. AEAD cipher.<\/td>\n<\/tr>\n<tr>\n<td>CTR and CBC<\/td>\n<td>Not started<\/td>\n<td><\/td>\n<td>Basic block cipher modes.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h3>Support Functionality<\/h3>\n<table>\n<thead>\n<tr>\n<th>Component<\/th>\n<th>Status<\/th>\n<th>Repository<\/th>\n<th>Comment<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>Coretest<\/td>\n<td>Done<\/td>\n<td><a href=\"https:\/\/git.cryptech.is\/core\/comm\/coretest\/about\">core\/comm\/coretest<\/a><\/td>\n<td>Command-response based core tester for HW accelerated core verification.<\/td>\n<\/tr>\n<tr>\n<td>UART<\/td>\n<td>Done<\/td>\n<td><a href=\"https:\/\/git.cryptech.is\/core\/comm\/uart\/about\">core\/comm\/uart<\/a><\/td>\n<td>Serial interface module used on the TerasIC C5G development board.<\/td>\n<\/tr>\n<tr>\n<td>I2C<\/td>\n<td>Done<\/td>\n<td><a href=\"https:\/\/git.cryptech.is\/core\/comm\/i2c\/about\">core\/comm\/i2c<\/a><\/td>\n<td>I2C interface module used on the Novena board.<\/td>\n<\/tr>\n<tr>\n<td>EIM<\/td>\n<td>Done<\/td>\n<td><a href=\"https:\/\/git.cryptech.is\/core\/comm\/eim\/about\">core\/comm\/eim<\/a><\/td>\n<td>Interface for the Freescale EIM memory interface used on the Novena board.<\/td>\n<\/tr>\n<tr>\n<td>FMC<\/td>\n<td>Done<\/td>\n<td><a href=\"https:\/\/git.cryptech.is\/core\/comm\/fmc\/about\">core\/comm\/fmc<\/a><\/td>\n<td>Interface for the STM32 FMC memory interface used on the dev-bridge and Alpha boards.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>","category":{"@attributes":{"term":"misc"}}},{"title":"Comparison of On-Chip Bus Standards","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/InterconnectStandards","rel":"alternate"}},"published":"2016-12-15T22:44:00+00:00","updated":"2016-12-15T22:44:00+00:00","author":{"name":"Cryptech Core Team"},"id":"tag:wiki.cryptech.is,2016-12-15:\/InterconnectStandards","summary":"<h2>Introduction<\/h2>\n<p>This document contains a brief summary of different on-chip bus\nstandards. The standards are described and compared based on license and\navailability, technical specifications and general usage.<\/p>\n<p>The purpose of the document is to provide a basis for selecting the\nprimary bus standard for the Cryptech Open HSM project \u2026<\/p>","content":"<h2>Introduction<\/h2>\n<p>This document contains a brief summary of different on-chip bus\nstandards. The standards are described and compared based on license and\navailability, technical specifications and general usage.<\/p>\n<p>The purpose of the document is to provide a basis for selecting the\nprimary bus standard for the Cryptech Open HSM project.<\/p>\n<h2>Overview<\/h2>\n<p>System on Chip (SoC) designs require some sort of connectivity between\nthe different components (called cores or IP-cores, as in Intellectual\nProperty) that are placed onto the same die.<\/p>\n<p>There are several standards for on-chip interconnect, standards that\nprovide technical diversity that might be required by the\nsystem. Typical differences are:<\/p>\n<ul>\n<li>\n<p>Performance. The capacity as well as latency.<\/p>\n<\/li>\n<li>\n<p>Intelligence. Simple master-slave read\/write access or DMA-transfers,\n   coherence support etc.<\/p>\n<\/li>\n<li>\n<p>point to point or point to multipoint. Basically bus based or switch\n   fabric.<\/p>\n<\/li>\n<\/ul>\n<p>There are also non-technical differences:<\/p>\n<ul>\n<li>\n<p>Licensing and pricing. Does using a standard add monetary cost and\n   does using the standard infer restrictions in sharing, disclosure of\n   source code?<\/p>\n<\/li>\n<li>\n<p>Market share. The market share is primarily interesting as basis for\n   the availability of other cores that could be integrated.<\/p>\n<\/li>\n<\/ul>\n<h2>Description of Standards<\/h2>\n<h3>AMBA<\/h3>\n<p>AMBA (Advanced Microcontroller Bus Architecture) <a href=\"#fn1\">(1)<\/a>, <a href=\"#fn2\">(2)<\/a> is a family of\ninterconnect standards from ARM Ltd. AMBA is widely used in systems\nimplemented in ASICs (for example mobile phone platforms), but are also\nused in FPGAs. AMBA is for example used by the LEON <a href=\"#fn3\">(3)<\/a> processor\ncores and subsystem GRLIB.<\/p>\n<p>AMBA currently contains four main interconnect types:<\/p>\n<ul>\n<li>\n<p>APB. A simple register read\/write bus used to connect simpler\n    devices such as timers, IRQ handlers, slow serial I\/O such as UARTS\n    and GPIO interfaces. The peripherals are connected to a common bus\n    with a single master.<\/p>\n<\/li>\n<li>\n<p>AHB. A more advanced bus based interconnect. Supports more complex\n    data transfers of up to 1 kByte data. Supports multiple masters.<\/p>\n<\/li>\n<li>\n<p>AXI. A switch fabric based interconnect that supports multiple\n    parallel transfers, multiple masters etc.<\/p>\n<\/li>\n<li>\n<p>ACE. A low latency interconnect that supports cache coherency to\n    allow the design of multicore, multiprocessor systems on-chip.<\/p>\n<\/li>\n<\/ul>\n<p>(There are also additional protocols in the AMBA specification for\nthings like tracing etc.)<\/p>\n<p>The license model for AMBA is <em>Open<\/em> according to ARM. This seems to\nmean that one can use AMBA to build a system. But at the same time, ARM\nhas intellectual properties to parts of the technology as well as\ntrademarks. For more information on ARM licensing, see <a href=\"#fn4\">(4)<\/a>.<\/p>\n<p>The OpenCores project <a href=\"#fn7\">(7)<\/a> lists several cores as well as tools for\ndifferent AMBA interconnect types.<\/p>\n<p>Pros:<\/p>\n<ul>\n<li>\n<p>Technically advanced and covers a wide range of system\n    requirements.<\/p>\n<\/li>\n<li>\n<p>A huge user base.<\/p>\n<\/li>\n<li>\n<p>A huge selection of third party support in terms of tools as well as\n    cores. Most of these cores and tools are commercial and proprietary,\n    closed source.<\/p>\n<\/li>\n<\/ul>\n<p>Cons:<\/p>\n<ul>\n<li>\n<p>Licensing. Would Cryptech need to get a license?<\/p>\n<\/li>\n<li>\n<p>Availability of open cores<\/p>\n<\/li>\n<\/ul>\n<h3>Avalon<\/h3>\n<p>Avalon <a href=\"#fn5\">(5)<\/a> is a proprietary switch fabric interconnect from Altera\ncorporation. It is used in systems developed using the Altera Nios-II\n<a href=\"#fn6\">(6)<\/a> family of soft processor cores and related peripherals.<\/p>\n<p>According to Altera, the license for Avalon is open: \"Avalon interfaces\nare an open standard. No license or royalty is required to develop and\nsell products that use, or are based on Avalon interfaces.\"<\/p>\n<p>As far as we can discern, Avalon is not generally used outside of Altera\nbased designs and not supported by a large group of third party\nvendors. The OpenCores project lists only a few cores that uses Avalon\nas interface standard.<\/p>\n<p>=\nPros:<\/p>\n<ul>\n<li>\n<p>Good technical features.<\/p>\n<\/li>\n<li>\n<p>Easy integration in Nios-II based systems.<\/p>\n<\/li>\n<\/ul>\n<p>Cons:<\/p>\n<ul>\n<li>\n<p>Limited to Altera based FPGA designs.<\/p>\n<\/li>\n<li>\n<p>Low support from open and proprietary third party suppliers of tools\n    and cores.<\/p>\n<\/li>\n<\/ul>\n<h3>CoreConnect<\/h3>\n<p>CoreConnect <a href=\"#fn8\">(8)<\/a> is an interconnect standard initially developed by\nIBM. The standard is now used by several vendors, for example the\nFPGA-vendor Xilinx<a href=\"#fn9\">(9)<\/a>.<\/p>\n<p>Similarly to AMBA, CoreConnect contains several types of buses providing\nsimple peripheral access (DCR), high speed access for processor based\nsystems (OPB), as well as multicore solutions (PLB).<\/p>\n<p>The license for CoreConnect is granted by IBM <a href=\"#fn10\">(10)<\/a>. The license seems to be\nan AS IS-license, but contains a lot of other regulations. IBM holds a\nnumber of patents related to CoreConnect (see the license agreement).<\/p>\n<p>Pros:<\/p>\n<ul>\n<li>Good support on for systems implemented on Xilinx FPGAs.<\/li>\n<\/ul>\n<p>Cons:<\/p>\n<ul>\n<li>Low support by open cores and tools.<\/li>\n<li>License agreement.<\/li>\n<\/ul>\n<h3>OCP<\/h3>\n<p>The Open Core Protocol <a href=\"#fn11\">(11)<\/a> is a vendor neutral open interconnect standard\nbeing developed by the EDA standards organisation Accellera <a href=\"#fn12\">(12)<\/a>. The\nstandards was previously developed by the vendor organisation OCP-IP <a href=\"#fn13\">(13)<\/a>,\nbut were transferred to Accellera in October 2013.<\/p>\n<p>Like AMBA, OCP contains a wide range of interconnect types from simple\nregister read\/write access over a common bus to point to\npoint-interconnect and coherency support.<\/p>\n<p>There are quite a few commercial cores using OCP, but there seem to be\nvery few open cores using OCP. OpenCores only lists a few cores and\nthey are all bridges used to connect OCP to AMBA or Wishbone.<\/p>\n<p>The license for accessing the specification itself is an amended AS\nIS-type license<a href=\"#fn14\">(14)<\/a>. The license for the interconnect seems to be rather\nopen.<\/p>\n<p>Pros:<\/p>\n<ul>\n<li>Good technical features.<\/li>\n<\/ul>\n<p>Cons:<\/p>\n<ul>\n<li>Not very common in use by open cores.<\/li>\n<\/ul>\n<h3>Wishbone<\/h3>\n<p>Wishbone <a href=\"#fn15\">(15)<\/a><a href=\"#fn16\">(16)<\/a> (often written WISHBONE) is an open interconnect\nstandard developed by members of the OpenCore project as an alternative\nto commercial solutions - primarily AMBA.<\/p>\n<p>Wishbone supports bus based as well as switch fabric interconnect\nsolutions of Wishbone cores. There are cores and tools to create CPU\nbased systems with buses and fabrics. Technically Wishbone is simpler\nthat AMBA and CoreConnect, but provides multimasters, point to point\nswitch fabrics, etc.<\/p>\n<p>There are tools available to generate Wishbone interfaces for a core as\nwell as creating a Wishbone connected system with different types of\ninterconnect solutions.<\/p>\n<p>The main use is related to the OpenRISC CPU core platform\n<a href=\"#fn17\">(17)<\/a><a href=\"#fn18\">(18)<\/a>. OpenCores lists a huge selection of cores with Wishbone\nsupport. The majority of these cores have LGPL and GPL licenses. There\nare also third party commercial vendors that support Wishbone cores and\nsystems.<\/p>\n<p>The license for the Wishbone standard is public domain and dos not\nimpose any restrictions on usage in cores and systems. The\nspecification document itself is close to Creative Commons CC-BY.<\/p>\n<p>Pros:<\/p>\n<ul>\n<li>Fairly good technical support.<\/li>\n<li>Good support from open tools and cores.<\/li>\n<li>Public domain license.<\/li>\n<\/ul>\n<p>Cons:<\/p>\n<ul>\n<li>Not as advanced. No good coherency support for example.<\/li>\n<\/ul>\n<h2>Conclusions<\/h2>\n<p>OF the different standards, only two standards are really interesting\nfor Cryptech - AMBA and Wishbone.<\/p>\n<p>From a technical point of view, selecting AMBA would be the proper\nchoice. AMBA provides all types of interconnect that a Cryptech\nimplementation might need. Also, building a Cryptech implementation\nusing third party cores (CPU cores for example) would be easier with\nAMBA than the other standards. Wher AMBA falls short is the questions\nrelated to licensing as well as the a bit less common support from open\ncores and tools.<\/p>\n<p>Based on ease of licensing, openness and availability of open cores,\nWishbone is an easy choice. Wishbone would quite probably meet all\nperformance and functionality requirements a Cryptech implementation\nmight have. Integration with and support from commercial cores, tools\nand vendors will however not be as good. Choosing Wishbone will quite\nprobably mean more work for the Cryptech project to deliver cores and\ntools. And for the users of Cryptech Wishbone may also require more work\nand thus reduce the interest Cryptech as a HSM solution.<\/p>\n<h2>References<\/h2>\n<ol>\n<li>\n<p>https:\/\/en.wikipedia.org\/wiki\/Advanced_Microcontroller_Bus_Architecture<\/p>\n<\/li>\n<li>\n<p>http:\/\/www.arm.com\/products\/system-ip\/amba\/amba-open-specifications.php<\/p>\n<\/li>\n<li>\n<p>https:\/\/en.wikipedia.org\/wiki\/LEON<\/p>\n<\/li>\n<li>\n<p>http:\/\/www.arm.com\/products\/system-ip\/amba\/index.php?tab=AMBA+Trademark+Guidelines<\/p>\n<\/li>\n<li>\n<p>http:\/\/www.altera.com\/literature\/manual\/mnl_avalon_spec.pdf<\/p>\n<\/li>\n<li>\n<p>http:\/\/www.altera.com\/devices\/processor\/nios2\/ni2-index.html<\/p>\n<\/li>\n<li>\n<p>http:\/\/opencores.org\/<\/p>\n<\/li>\n<li>\n<p>https:\/\/en.wikipedia.org\/wiki\/CoreConnect<\/p>\n<\/li>\n<li>\n<p>http:\/\/www.xilinx.com\/products\/intellectual-property\/dr_pcentral_coreconnect.htm<\/p>\n<\/li>\n<li>\n<p>http:\/\/www.xilinx.com\/ipcenter\/doc\/ibm_click_core_connect_license.pdf<\/p>\n<\/li>\n<li>\n<p>https:\/\/en.wikipedia.org\/wiki\/Open_Core_Protocol<\/p>\n<\/li>\n<li>\n<p>https:\/\/en.wikipedia.org\/wiki\/Accellera<\/p>\n<\/li>\n<li>\n<p>http:\/\/www.ocpip.org\/<\/p>\n<\/li>\n<li>\n<p>http:\/\/www.ocpip.org\/license_signup.php<\/p>\n<\/li>\n<li>\n<p>http:\/\/opencores.org\/opencores,wishbone<\/p>\n<\/li>\n<li>\n<p>https:\/\/en.wikipedia.org\/wiki\/Wishbone_(computer_bus)<\/p>\n<\/li>\n<li>\n<p>http:\/\/openrisc.net\/<\/p>\n<\/li>\n<li>\n<p>http:\/\/opencores.org\/or1k\/Main_Page<\/p>\n<\/li>\n<\/ol>\n<h2>Copyright and License<\/h2>\n<p>This document has been written by Joachim Str\u00f6mbergson.<\/p>\n<p>(c) 2014 SUNET - The Swedish University Network<\/p>\n<p>This document is licensed under a Creative Commons license (CC BY 3.0).\nFor more information, see:<\/p>\n<p>https:\/\/creativecommons.org\/licenses\/by\/3.0\/<\/p>","category":{"@attributes":{"term":"misc"}}},{"title":"An Open Crypto Chip","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/OpenCryptoChip","rel":"alternate"}},"published":"2016-12-15T22:44:00+00:00","updated":"2016-12-15T22:44:00+00:00","author":{"name":"Cryptech Core Team"},"id":"tag:wiki.cryptech.is,2016-12-15:\/OpenCryptoChip","summary":"<h2>The Layer Cake Architecture Picture<\/h2>\n<p><br\/>\n<img alt=\"layer-cake.jpg\" src=\"https:\/\/wiki.cryptech.is\/OpenCryptoChip\/OpenCryptoChip\/layer-cake.jpg\"><\/p>\n<p><br\/>\n<br\/><\/p>\n<h2>Use Cases<\/h2>\n<ul>\n<li>RPKI\/DNSSEC Signing<\/li>\n<li>Transport VPNs<\/li>\n<li>Routers and TCP\/AO<\/li>\n<li>Email<\/li>\n<li>Federations, Identity Systems, SSO etc<\/li>\n<li>Password Stretching &amp; HMAC:ing<\/li>\n<li>PGP and SSH Keys on a Stick<\/li>\n<li>High Quality Entropy Randomness<\/li>\n<li>A Communications Terminal Doing One Thing Well, Like Jabber w\/o X11<\/li>\n<li>HSM \u2026<\/li><\/ul>","content":"<h2>The Layer Cake Architecture Picture<\/h2>\n<p><br\/>\n<img alt=\"layer-cake.jpg\" src=\"https:\/\/wiki.cryptech.is\/OpenCryptoChip\/OpenCryptoChip\/layer-cake.jpg\"><\/p>\n<p><br\/>\n<br\/><\/p>\n<h2>Use Cases<\/h2>\n<ul>\n<li>RPKI\/DNSSEC Signing<\/li>\n<li>Transport VPNs<\/li>\n<li>Routers and TCP\/AO<\/li>\n<li>Email<\/li>\n<li>Federations, Identity Systems, SSO etc<\/li>\n<li>Password Stretching &amp; HMAC:ing<\/li>\n<li>PGP and SSH Keys on a Stick<\/li>\n<li>High Quality Entropy Randomness<\/li>\n<li>A Communications Terminal Doing One Thing Well, Like Jabber w\/o X11<\/li>\n<li>HSM for Pond, OTR identity keys, ssh private keys, etc. (i.e. key gen, store, import\/export non X.509 packages)<\/li>\n<li>Password management<\/li>\n<\/ul>\n<p><img alt=\"cryptech venn.png\" src=\"https:\/\/wiki.cryptech.is\/OpenCryptoChip\/OpenCryptoChip\/cryptech venn.png\"><\/p>\n<h2>Basic Functions of Crypto Chip<\/h2>\n<ul>\n<li>Key Generation<\/li>\n<li>Key Storage<\/li>\n<li>Key Wrap<\/li>\n<li>Key Unwrap<\/li>\n<li>Hash<\/li>\n<li>Sign<\/li>\n<li>M of N Sign<\/li>\n<li>Verify Signature<\/li>\n<li>Encrypt<\/li>\n<li>Decrypt<\/li>\n<li>KDFs, e.g. Password Stretching (a la PBKDF2)<\/li>\n<li>Random (RO + noisy diode?)<\/li>\n<\/ul>\n<h2>Key wrapping<\/h2>\n<p>We need to support key wrapping. Some pointers:<\/p>\n<ul>\n<li>https:\/\/en.wikipedia.org\/wiki\/Key_Wrap<\/li>\n<li>http:\/\/tools.ietf.org\/html\/rfc5297<\/li>\n<li>http:\/\/csrc.nist.gov\/groups\/ST\/toolkit\/documents\/kms\/key-wrap.pdf<\/li>\n<li>https:\/\/tools.ietf.org\/html\/rfc3394<\/li>\n<li>https:\/\/tools.ietf.org\/html\/rfc5649<\/li>\n<\/ul>\n<h2>Things we Should Try To Do, Even if we Can't Do Them Perfectly<\/h2>\n<ul>\n<li>Tamper Protection (wipe on signal, suggest detectors, suggest potting features)<\/li>\n<li>Side Channel Attack Reduction<\/li>\n<\/ul>\n<h1>Rough Cut at v0.01 Proof of Concept Feature Set<\/h1>\n<p>As a proof of concept, to validate as much as possible the assurance of the tools and methods, and as a demonstration of the project tools, team, and architecture, we have a <a href=\"https:\/\/wiki.cryptech.is\/RoughV1\">proposed version 0.01 product<\/a> as a proof of concept and a demonstration of the project tools, team, and architecture\n<br\/>\n<br\/><\/p>\n<h1>Ongoing Decisions and Research<\/h1>\n<ul>\n<li>Security Target Description<\/li>\n<li>Performance Target(s)<\/li>\n<li>Tool-Chain Investigation<\/li>\n<li>Prototype Design<\/li>\n<li>Testing \/ Assurance Methods for all Components<\/li>\n<li>Verilog\/RTL assurance, with open source and with proprietary<\/li>\n<li>Prototyping Platform(s)<\/li>\n<li>Documentation, Decision History, &amp; Transparency<\/li>\n<\/ul>\n<p><br\/>\n<br\/><\/p>\n<h1>Ongoing Development<\/h1>\n<ul>\n<li><a href=\"https:\/\/wiki.cryptech.is\/SunetInitialDevelopment\">SUNET is sponsoring the first two development steps<\/a> currently being done.<\/li>\n<li><a href=\"https:\/\/wiki.cryptech.is\/TRNGDevelopment\"> Investigation and planning of a TRNG with entropy sources<\/a><\/li>\n<li><a href=\"https:\/\/wiki.cryptech.is\/EDAToolchainSurvey\">Investigation of possible EDA tools and ways to do open and assured HW development\"<\/a><\/li>\n<li><a href=\"https:\/\/wiki.cryptech.is\/SideChannel\">Collection about side-channel attacks and detection, mitigation methods<\/a><\/li>\n<\/ul>\n<h1>v0.1 Major Sub-Projects<\/h1>\n<h2>Security Goals and Documentation<\/h2>\n<ul>\n<li>Agreement<\/li>\n<li>Specification<\/li>\n<\/ul>\n<h2>Development Platform<\/h2>\n<ul>\n<li>\n<p>The Bunnie laptop Novena. Includes a Xilinx Spartan 6 LX45 FPGHA. The specs, drivers, source for Novena can be found here: http:\/\/www.kosagi.com\/w\/index.php?title=Novena_Main_Page<\/p>\n<\/li>\n<li>\n<p>TerasIC C5G Cyclone 5 GX Starter Kit. Includes an Altera C5GX FPGA. This board is used for core, subsystem development and verification. Info, documentation and ordering of the TerasIC board can be found here: http:\/\/www.terasic.com.tw\/cgi-bin\/page\/archive.pl?Language=English&amp;CategoryNo=167&amp;No=830<\/p>\n<\/li>\n<\/ul>\n<p>Here is a writeup on how to <a href=\"https:\/\/wiki.cryptech.is\/CoretestHashesC5G\">setup and run coretest_hashes on the C5G board<\/a>.<\/p>\n<ul>\n<li>TerasIC DE0-Nano board. This tiny, USB powered board is used for core development and verification. Info, documentation, resources, ordering of the TerasIC board can be found here: http:\/\/www.terasic.com.tw\/cgi-bin\/page\/archive.pl?Language=English&amp;CategoryNo=139&amp;No=593<\/li>\n<\/ul>\n<h2>Hardware Development Tools<\/h2>\n<h2>Component Libraries<\/h2>\n<ul>\n<li>Research<\/li>\n<li>Select<\/li>\n<li><a href=\"https:\/\/wiki.cryptech.is\/InterconnectStandards\">On-chip Interconnect Standards<\/a> to use.<\/li>\n<\/ul>\n<h2>Methods and Validation<\/h2>\n<ul>\n<li>Overall Strategy<\/li>\n<li>Following the Tool-Chain<\/li>\n<\/ul>\n<h2>Detailed Specification<\/h2>\n<ul>\n<li>Feature Set<\/li>\n<\/ul>\n<h2>QA &amp; Documentation<\/h2>\n<h2>Green\/Yellow Software Support<\/h2>\n<ul>\n<li>Spec \/ ABI<\/li>\n<li>Development<\/li>\n<li>Documentationa and Testing<\/li>\n<\/ul>\n<h2>Assured Linux Platform<\/h2>\n<ul>\n<li>DDC Compiler<\/li>\n<li>System Build<\/li>\n<li>Minimal Component Set<\/li>\n<\/ul>\n<h1>v0.1 Project Timeline<\/h1>\n<h2>February 2014<\/h2>\n<ul>\n<li>Specification of v0.1 Goals and Feature Set<\/li>\n<li>Security Goals &amp; Documentation Outline<\/li>\n<\/ul>\n<h2>July 2014<\/h2>\n<ul>\n<li>SHA &amp; AES<\/li>\n<\/ul>\n<h2>September 2014<\/h2>\n<ul>\n<li>TRNG<\/li>\n<li>Assured Linux Platform - Initial Report<\/li>\n<\/ul>\n<h2>November 2014<\/h2>\n<ul>\n<li>Security Goals &amp; Documentation Overall and v0.1<\/li>\n<li>RSA Signing on Bunnie Board<\/li>\n<li>Assured Linux Platform - Compiler<\/li>\n<\/ul>\n<h2>March 2015<\/h2>\n<ul>\n<li>v0.1 Protoype<\/li>\n<\/ul>\n<h1>Future Development<\/h1>\n<p>The v0.1 version of CrypTech is not the last version nor the only possible version. The project for example consider possible <a href=\"https:\/\/wiki.cryptech.is\/ASICImplementations\">ASIC Implementations<\/a>.<\/p>","category":{"@attributes":{"term":"misc"}}},{"title":"Post Alpha Plan","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/PostAlphaPlan","rel":"alternate"}},"published":"2016-12-15T22:44:00+00:00","updated":"2017-05-16T14:53:00+00:00","author":{"name":"Paul Selkirk"},"id":"tag:wiki.cryptech.is,2016-12-15:\/PostAlphaPlan","summary":"<p>The core dev team had a design meeting in Berlin after the alpha workshop. We came up with a plan for the hardware and the software work for the next few months:<\/p>\n<h2>Hardware<\/h2>\n<h3>Revision 04<\/h3>\n<p>This is targeted for the mid-flight revision in the 50 board order from propoint. For \u2026<\/p>","content":"<p>The core dev team had a design meeting in Berlin after the alpha workshop. We came up with a plan for the hardware and the software work for the next few months:<\/p>\n<h2>Hardware<\/h2>\n<h3>Revision 04<\/h3>\n<p>This is targeted for the mid-flight revision in the 50 board order from propoint. For practical reasons, we should limit ourselves to bugfixes and other \"low risk\" changes for this release.<\/p>\n<ul>\n<li>On-board battery (super-cap, long battery life etc, battery outside the tamper boundary etc)<\/li>\n<li>Next generation USB based on Stuges daughter board work<\/li>\n<li>Support higher clock speeds<\/li>\n<li>Proposed: pull out 2 more UARTS from the STM32 to support memory-card readers and pin-entry devices<\/li>\n<\/ul>\n<h3>Revision 05<\/h3>\n<ul>\n<li>Power instrumentation<\/li>\n<li>EMC<\/li>\n<li>Tamper revisions??<\/li>\n<\/ul>\n<h2>Software<\/h2>\n<p>The software plan is divided into 3 parts: \"now\", \"next week\" and \"next month\". These are labels, not a time frame. The \"now\" list represents stuff that is currently seeing active work. We move stuff from \"next week\" to \"now\" and from \"next month\" to \"next week\" as part of our planning process (at the engineering calls).<\/p>\n<h3>Now<\/h3>\n<ul>\n<li>CLI updates [Done, but waiting on a BSD-friendly license]<\/li>\n<li>rewrite keystore code to support larger keysizes and more slots [Done]<\/li>\n<li>multi-core resource management [Done]<\/li>\n<li>finish verilog EC point multiplier [Done]<\/li>\n<li>increase clock speed<\/li>\n<li>openssl engine [Done]<\/li>\n<li>debug log [Mechanism done, nothing using it yet]<\/li>\n<li>usb driver matching rev04 usb updates<\/li>\n<\/ul>\n<h3>Next Week<\/h3>\n<ul>\n<li>GOST drivers<\/li>\n<li>key backup [Done]<\/li>\n<li>SHA3<\/li>\n<li>ECDSA verilog [Done]<\/li>\n<li>build system configuration management<\/li>\n<li>real documentation: user, admin and dev manuals<\/li>\n<li>Python RPC client [Done]<\/li>\n<li>set time and date from CLI<\/li>\n<\/ul>\n<h3>Next Month<\/h3>\n<ul>\n<li>25519 verilog<\/li>\n<li>design papers<\/li>\n<li>doxygen<\/li>\n<li>m of n<\/li>\n<li>notify ARM and FPGA of tamper events<\/li>\n<li>secure channel<\/li>\n<li>ECDH<\/li>\n<li>AES drivers<\/li>\n<li>audit logging<\/li>\n<\/ul>\n<h3>Eventually<\/h3>\n<ul>\n<li>Profiling [Mechanism done]<\/li>\n<\/ul>","category":{"@attributes":{"term":"misc"}}},{"title":"Project Archive and Far Future Planning","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/ProjectArchive","rel":"alternate"}},"published":"2016-12-15T22:44:00+00:00","updated":"2016-12-15T22:44:00+00:00","author":{"name":"Cryptech Core Team"},"id":"tag:wiki.cryptech.is,2016-12-15:\/ProjectArchive","content":"<p><em>Page Under Construction<\/em><\/p>\n<h2><a href=\"https:\/\/wiki.cryptech.is\/AssuredTooChain\">Assured Tool Chain<\/a><\/h2>","category":{"@attributes":{"term":"misc"}}},{"title":"Project Management","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/ProjectManagement","rel":"alternate"}},"published":"2016-12-15T22:44:00+00:00","updated":"2016-12-15T22:44:00+00:00","author":{"name":"Cryptech Core Team"},"id":"tag:wiki.cryptech.is,2016-12-15:\/ProjectManagement","summary":"<h1>v0.1 Resources<\/h1>\n<h2>Human - 4-5 FTE<\/h2>\n<ul>\n<li>0.5 Specifications<\/li>\n<li>1.0 FPGA Tools and Core<\/li>\n<li>1.0 Core Libraries and Interfaces<\/li>\n<li>0.5 QA &amp; Docs<\/li>\n<li>0.5 Assured Linux Platform<\/li>\n<li>1.0 Coordination<\/li>\n<\/ul>\n<h2>Hardware<\/h2>\n<ul>\n<li>4 Bunnie Boards<\/li>\n<li>2 Altera Eval Systems<\/li>\n<li>Linux Platform<\/li>\n<\/ul>\n<h2>Travel &amp; Overhead<\/h2>\n<ul>\n<li>Travel $5k\/mo<\/li>\n<li>Communications $1k \u2026<\/li><\/ul>","content":"<h1>v0.1 Resources<\/h1>\n<h2>Human - 4-5 FTE<\/h2>\n<ul>\n<li>0.5 Specifications<\/li>\n<li>1.0 FPGA Tools and Core<\/li>\n<li>1.0 Core Libraries and Interfaces<\/li>\n<li>0.5 QA &amp; Docs<\/li>\n<li>0.5 Assured Linux Platform<\/li>\n<li>1.0 Coordination<\/li>\n<\/ul>\n<h2>Hardware<\/h2>\n<ul>\n<li>4 Bunnie Boards<\/li>\n<li>2 Altera Eval Systems<\/li>\n<li>Linux Platform<\/li>\n<\/ul>\n<h2>Travel &amp; Overhead<\/h2>\n<ul>\n<li>Travel $5k\/mo<\/li>\n<li>Communications $1k\/mo<\/li>\n<li>Administrative $1k\/mo<\/li>\n<\/ul>","category":{"@attributes":{"term":"misc"}}},{"title":"Project Status","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/ProjectStatus","rel":"alternate"}},"published":"2016-12-15T22:44:00+00:00","updated":"2016-12-15T22:44:00+00:00","author":{"name":"Cryptech Core Team"},"id":"tag:wiki.cryptech.is,2016-12-15:\/ProjectStatus","content":"<p><em>Page Under Development<\/em><\/p>\n<h2><a href=\"https:\/\/wiki.cryptech.is\/Dashboard\">Project Dashboard<\/a><\/h2>\n<h2>Crypto Chip Design and Prototype<\/h2>\n<ul>\n<li><a href=\"https:\/\/wiki.cryptech.is\/PostAlphaPlan\">PostAlphaPlan<\/a><\/li>\n<li><a href=\"https:\/\/wiki.cryptech.is\/AlphaBoardStrategy\">AlphaBoardStrategy<\/a><\/li>\n<li><a href=\"https:\/\/wiki.cryptech.is\/AlphaBoardComponents\">AlphaBoardComponents<\/a><\/li>\n<li><a href=\"https:\/\/git.cryptech.is\/\">Core Git Repository<\/a><\/li>\n<li><a href=\"https:\/\/wiki.cryptech.is\/Hardware\">Hardware<\/a><\/li>\n<li><a href=\"https:\/\/wiki.cryptech.is\/DevBridgeBoard\">DevBridgeBoard<\/a><\/li>\n<\/ul>\n<h2>Pilot Project<\/h2>\n<ul>\n<li><a href=\"https:\/\/wiki.cryptech.is\/DNSSEC\">Requirements<\/a><\/li>\n<\/ul>","category":{"@attributes":{"term":"misc"}}},{"title":"Related Work","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/RelatedWork","rel":"alternate"}},"published":"2016-12-15T22:44:00+00:00","updated":"2016-12-15T22:44:00+00:00","author":{"name":"Cryptech Core Team"},"id":"tag:wiki.cryptech.is,2016-12-15:\/RelatedWork","summary":"<h2>Richard Lamb \/ ICANN<\/h2>\n<p><a href=\"http:\/\/ccnso.icann.org\/file\/32383\/download\/37379\">Presentation at ICANN<\/a><br\/>\n<a href=\"http:\/\/ccnso.icann.org\/file\/40211\/download\/52359\">Presentation at ICANN<\/a><br\/>\n\"I wrote pkcs11 libraries and also have modified BIND that offloads full\nRRSIG calculation (including time) to board.  Clearly can use anything\nother than TPM to do RSA calculations.\"<\/p>\n<h2>SoftHSM<\/h2>\n<ul>\n<li><a href=\"https:\/\/www.opendnssec.org\/softhsm\/\">SoftHSM<\/a> - part of OpenDNSSEC<\/li>\n<li><a href=\"http:\/\/wiki.cacert.org\/Possum\">Possum<\/a> - an earlier attempt att an Open \u2026<\/li><\/ul>","content":"<h2>Richard Lamb \/ ICANN<\/h2>\n<p><a href=\"http:\/\/ccnso.icann.org\/file\/32383\/download\/37379\">Presentation at ICANN<\/a><br\/>\n<a href=\"http:\/\/ccnso.icann.org\/file\/40211\/download\/52359\">Presentation at ICANN<\/a><br\/>\n\"I wrote pkcs11 libraries and also have modified BIND that offloads full\nRRSIG calculation (including time) to board.  Clearly can use anything\nother than TPM to do RSA calculations.\"<\/p>\n<h2>SoftHSM<\/h2>\n<ul>\n<li><a href=\"https:\/\/www.opendnssec.org\/softhsm\/\">SoftHSM<\/a> - part of OpenDNSSEC<\/li>\n<li><a href=\"http:\/\/wiki.cacert.org\/Possum\">Possum<\/a> - an earlier attempt att an Open Source HSM.<\/li>\n<\/ul>\n<h2>Project Turris - CZNIC<\/h2>\n<p><a href=\"http:\/\/www.turris.cz\/en\/\">Project Thuris Web Pages<\/a><br\/>\nProject Turris is a service helping to protect its user's home network\nwith the help of a special router. It is a not-for-profit research\nproject of CZ.NIC, z. s. p. o., the registry of the Czech national top\nlevel domain .CZ.<\/p>","category":{"@attributes":{"term":"misc"}}},{"title":"Side Channel Attacks","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/SideChannel","rel":"alternate"}},"published":"2016-12-15T22:44:00+00:00","updated":"2016-12-15T22:44:00+00:00","author":{"name":"Cryptech Core Team"},"id":"tag:wiki.cryptech.is,2016-12-15:\/SideChannel","summary":"<p>Side Channel attacks on hardware are hard to avoid, detect and mitigate. But this should not stop us from trying. The CrypTech platform should be developed with side channel issues in mind. This page tries to collect information about relevant side channel attacks, mitigation strategies, side channel resistant design methods \u2026<\/p>","content":"<p>Side Channel attacks on hardware are hard to avoid, detect and mitigate. But this should not stop us from trying. The CrypTech platform should be developed with side channel issues in mind. This page tries to collect information about relevant side channel attacks, mitigation strategies, side channel resistant design methods (blinding for example) and detection.<\/p>\n<ul>\n<li>http:\/\/eprint.iacr.org\/2013\/579 \"On Measurable Side-Channel Leaks inside ASIC Design Primitives\"<\/li>\n<li>http:\/\/people.umass.edu\/gbecker\/BeckerChes13.pdf \"Stealthy Dopant-Level Hardware Trojans\"<\/li>\n<\/ul>","category":{"@attributes":{"term":"misc"}}},{"title":"How to start using coretest_hashes on the TerasIC C5G Board","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/CoretestHashesC5G","rel":"alternate"}},"published":"2016-12-15T22:43:00+00:00","updated":"2016-12-15T22:43:00+00:00","author":{"name":"Joachim Str\u00f6mbergson"},"id":"tag:wiki.cryptech.is,2016-12-15:\/CoretestHashesC5G","summary":"<p>This is a writeup on how to setup, build and testrun the <code>coretest_hashes<\/code>\nCryptech subsystem on a TerasiC C5G Cyclone V GX Starter Kit FPGA\ndevelopment board <a href=\"http:\/\/www.terasic.com.tw\/cgi-bin\/page\/archive.pl?Language=English&amp;No=830\">1<\/a>.<\/p>\n<h2>Introduction<\/h2>\n<h3>Test Setup<\/h3>\n<p>The test setup consists of:<\/p>\n<ul>\n<li>\n<p>A development computer running the Altera Quartus II FPGA development software. This computer will \u2026<\/p><\/li><\/ul>","content":"<p>This is a writeup on how to setup, build and testrun the <code>coretest_hashes<\/code>\nCryptech subsystem on a TerasiC C5G Cyclone V GX Starter Kit FPGA\ndevelopment board <a href=\"http:\/\/www.terasic.com.tw\/cgi-bin\/page\/archive.pl?Language=English&amp;No=830\">1<\/a>.<\/p>\n<h2>Introduction<\/h2>\n<h3>Test Setup<\/h3>\n<p>The test setup consists of:<\/p>\n<ul>\n<li>\n<p>A development computer running the Altera Quartus II FPGA development software. This computer will be building the FPGA comfiguration image (a sof-file) and then use the Altera USB-blaster to load the image into the FPGA on the TerasIC board. This computer shall therefore be connected to the USB-blaster port on the TerasIC board.<\/p>\n<\/li>\n<li>\n<p>A host computer that runs the <code>hash_tester<\/code> application that communicates with the FPGA design downloaded into the FPGA and perform tests on the hash functions. The host computer is connected to the USB-serial port on the TerasIC board.<\/p>\n<\/li>\n<li>\n<p>The TerasIC Cyclone 5 GX Starter Kit (C5G) board.<\/p>\n<\/li>\n<\/ul>\n<p><img src=\"http:\/\/www.terasic.com.tw\/attachment\/archive\/830\/image\/image_74_thumb.jpg\"><\/p>\n<p><em>The TerasIC Cyclone 5 GX Starter Kit board.<\/em><\/p>\n<p>The USB ports are the shown in the upper left corner. These are USB type B ports. The port to the left is the USB-blaster port. The port to the right is the USB-serial port. In the bottom right corner there is a row of buttons and just above them 8 LEDs. These will also be used by the <code>coretest_hashes<\/code> subsystem. There is a HDMI port on the C5G board but it will not be used. All communication is done in CLI on the host computer.<\/p>\n<p><strong>NOTE: You don't actually need two separate computers. You can use one computer with one or two USB ports. If you only have one USB port you will need to switch from connecting to the USB-Blaster port to the USB-serial port on the C5G board once the <code>coretest_hashes<\/code> FPGA configuration has been downloaded to the board.<\/strong><\/p>\n<p>My personal setup is a laptop with two USB ports which allows me to have connections to both USB ports on the C5G boards simultaneously.<\/p>\n<h3><code>Coretest_hashes<\/code><\/h3>\n<p>The <code>coretest_hashes<\/code> is a subsystem that is a FPGA design that contains Cryptech application cores as well as support cores used to run tests of the\nSHA-1 and SHA-256 hash functions from a host computer via a serial\ninterface connected to a FPGA device. The subsystem consists of:<\/p>\n<ul>\n<li>\n<p><a href=\"https:\/\/git.cryptech.is\/core\/sha1\">sha1<\/a>: A HW implementation of the SHA-1 hash function.<\/p>\n<\/li>\n<li>\n<p><a href=\"https:\/\/git.cryptech.is\/core\/sha256\">sha56<\/a>: A HW implementation of the SHA-256 hash function.<\/p>\n<\/li>\n<li>\n<p><a href=\"https:\/\/git.cryptech.is\/core\/coretest\">coretest<\/a>: A command parser that accepts read\/write commands from a\n  host, executes the commands and sends the response.<\/p>\n<\/li>\n<li>\n<p><a href=\"https:\/\/git.cryptech.is\/core\/usrt\">uart<\/a>: A simple serial interface that connects coretest to the host.<\/p>\n<\/li>\n<li>\n<p><a href=\"https:\/\/git.cryptech.is\/core\/coretest_hashes\"><code>coretest_hashes<\/code><\/a>: A top level wrapper that connects all the cores as\n  well as connecting the rxd and txd ports on the uart to external pins as well as clk and reset. This core repo also contains the Python command line program <code>hash_tester<\/code> we will be using to talk to coretester and perform tests of the sha1 and sha256 cores.<\/p>\n<\/li>\n<\/ul>\n<p><img alt=\"coretest_hashes.png\" src=\"https:\/\/wiki.cryptech.is\/CoretestHashesC5G\/CoretestHashesC5G\/coretest_hashes.png\"><\/p>\n<p><em>The <code>coretest_hashes<\/code> subsystem with sha1 and sha256 cores. The system is connected to a host computer via a serial interface.<\/em><\/p>\n<h2>SW and system requirements<\/h2>\n<p>You need to download and install the Altera Quartus II Web Edition\nsoftware <a href=\"http:\/\/www.altera.com\/products\/software\/quartus-ii\/web-edition\/qts-we-index.html\">2<\/a>. There are versions of Quartus II Web Edition for Windows and Linux. I'm using the Windows version, but Linux <strong>should<\/strong> work too.<\/p>\n<p>You will probably also install drivers for the Altera USB-blaster in order to program the FPGA on the development board. For instructions on how to install the driver, please see the Altera page for USB-blaster <a href=\"http:\/\/www.ftdichip.com\/Drivers\/VCP.htm\">7<\/a>.<\/p>\n<p>For communication with the <code>coretest_hashes<\/code> in the FPGA we will be using the USB-serial device on the development board. The USB-serial chip on the\nboard is a FTDI FT232R <a href=\"http:\/\/www.ftdichip.com\/Products\/ICs\/FT232R.htm\">3<\/a>. If your host OS does not have support for this device you will need to install drivers. For Windows the correct file to download seems to be a VCP file <a href=\"http:\/\/www.ftdichip.com\/Drivers\/VCP.htm\">7<\/a>.<\/p>\n<p>Finally, in order to talk to <code>coretest_hashes<\/code> from the host there is application SW. This SW is written in Python and uses the Pyserial<a href=\"http:\/\/pyserial.sourceforge.net\/\">5<\/a> library. If you don't have Python and\/or Pyserial installed you will need to install that too.<\/p>\n<p><strong>NOTE: Python and Pyserial does not have to be installed in the same OS as Quartus II but can be run from a separate system and OS.<\/strong><\/p>\n<p>(I'm using Quartus II 13.1 64-bit version running in Win8.1 in a VM in Parallels Desktop in OX 10.9.2 during this writeup. And I use Python and Pyserial in an iTerm in OSX for the serial communication.)<\/p>\n<p>With all this SW installed you should be ready to proceed to create the\n<code>coretest_hashes<\/code> project.<\/p>\n<p><strong>I also recommend that you download the TerasIC C5G User Manual <a href=\"http:\/\/www.terasic.com.tw\/cgi-bin\/page\/archive.pl?Language=English&amp;CategoryNo=165&amp;No=830&amp;PartNo=4\">4<\/a>. It is a really good document that describes the boards with all functions, pins etc.<\/strong><\/p>\n<h2>Downloading the cores<\/h2>\n<p>Create a project directory. I'm using test_<code>coretest_hashes<\/code>. In it I add\na core directory and a toolruns directory:<\/p>\n<div class=\"highlight\"><pre><span><\/span><code><span class=\"c1\">#&gt; ls test_coretest_hashes<\/span>\n<span class=\"n\">cores<\/span><span class=\"o\">\/<\/span><span class=\"w\">    <\/span><span class=\"n\">toolruns<\/span><span class=\"o\">\/<\/span>\n<\/code><\/pre><\/div>\n\n<p>The cores we need to build the subsystem must be downloaded from the\nCryptech server. The cores we need are:<\/p>\n<ul>\n<li><code>sha1<\/code><\/li>\n<li><code>sha256<\/code><\/li>\n<li><code>uart<\/code><\/li>\n<li><code>coretest<\/code><\/li>\n<li><code>coretest_hashes<\/code><\/li>\n<\/ul>\n<div class=\"highlight\"><pre><span><\/span><code><span class=\"err\">#<\/span><span class=\"o\">&gt;<\/span><span class=\"w\"> <\/span><span class=\"n\">cd<\/span><span class=\"w\"> <\/span><span class=\"n\">cores<\/span>\n<span class=\"err\">#<\/span><span class=\"o\">&gt;<\/span><span class=\"w\"> <\/span><span class=\"n\">ssh<\/span><span class=\"w\"> <\/span><span class=\"n\">git<\/span><span class=\"nv\">@git<\/span><span class=\"p\">.<\/span><span class=\"n\">cryptech<\/span><span class=\"p\">.<\/span><span class=\"k\">is<\/span>\n<span class=\"n\">hello<\/span><span class=\"w\"> <\/span><span class=\"o\">&lt;<\/span><span class=\"n\">FOO<\/span><span class=\"o\">&gt;<\/span><span class=\"p\">,<\/span><span class=\"w\"> <\/span><span class=\"n\">this<\/span><span class=\"w\"> <\/span><span class=\"k\">is<\/span><span class=\"w\"> <\/span><span class=\"n\">git<\/span><span class=\"nv\">@cryptech<\/span><span class=\"w\"> <\/span><span class=\"n\">running<\/span><span class=\"w\"> <\/span><span class=\"n\">gitolite3<\/span><span class=\"w\"> <\/span><span class=\"n\">v3<\/span><span class=\"mf\">.5.2<\/span><span class=\"o\">-<\/span><span class=\"mi\">0<\/span><span class=\"o\">-<\/span><span class=\"n\">g926bd5f<\/span><span class=\"w\"> <\/span><span class=\"k\">on<\/span><span class=\"w\"> <\/span><span class=\"n\">git<\/span><span class=\"w\"> <\/span><span class=\"mf\">1.9.0<\/span>\n\n<span class=\"w\"> <\/span><span class=\"n\">R<\/span><span class=\"w\">   <\/span><span class=\"n\">C<\/span><span class=\"w\">  <\/span><span class=\"o\">[<\/span><span class=\"n\">a-zA-Z0-9<\/span><span class=\"o\">]<\/span><span class=\"p\">.<\/span><span class=\"o\">*<\/span>\n<span class=\"w\"> <\/span><span class=\"n\">R<\/span><span class=\"w\"> <\/span><span class=\"n\">W<\/span><span class=\"w\">    <\/span><span class=\"n\">core<\/span><span class=\"o\">\/<\/span><span class=\"n\">coretest<\/span>\n<span class=\"w\"> <\/span><span class=\"n\">R<\/span><span class=\"w\"> <\/span><span class=\"n\">W<\/span><span class=\"w\">    <\/span><span class=\"n\">core<\/span><span class=\"o\">\/<\/span><span class=\"n\">coretest_hashes<\/span>\n<span class=\"w\"> <\/span><span class=\"n\">R<\/span><span class=\"w\"> <\/span><span class=\"n\">W<\/span><span class=\"w\">    <\/span><span class=\"n\">core<\/span><span class=\"o\">\/<\/span><span class=\"n\">coretest_test_core<\/span>\n<span class=\"w\"> <\/span><span class=\"n\">R<\/span><span class=\"w\"> <\/span><span class=\"n\">W<\/span><span class=\"w\">    <\/span><span class=\"n\">core<\/span><span class=\"o\">\/<\/span><span class=\"n\">sha1<\/span>\n<span class=\"w\"> <\/span><span class=\"n\">R<\/span><span class=\"w\"> <\/span><span class=\"n\">W<\/span><span class=\"w\">    <\/span><span class=\"n\">core<\/span><span class=\"o\">\/<\/span><span class=\"n\">sha256<\/span>\n<span class=\"w\"> <\/span><span class=\"n\">R<\/span><span class=\"w\"> <\/span><span class=\"n\">W<\/span><span class=\"w\">    <\/span><span class=\"n\">core<\/span><span class=\"o\">\/<\/span><span class=\"n\">test_core<\/span>\n<span class=\"w\"> <\/span><span class=\"n\">R<\/span><span class=\"w\"> <\/span><span class=\"n\">W<\/span><span class=\"w\">    <\/span><span class=\"n\">core<\/span><span class=\"o\">\/<\/span><span class=\"n\">uart<\/span>\n<span class=\"w\"> <\/span><span class=\"n\">R<\/span><span class=\"w\"> <\/span><span class=\"n\">W<\/span><span class=\"w\">    <\/span><span class=\"n\">doc<\/span><span class=\"o\">\/<\/span><span class=\"n\">presentations<\/span>\n<span class=\"w\"> <\/span><span class=\"n\">R<\/span><span class=\"w\">      <\/span><span class=\"n\">gitolite<\/span><span class=\"o\">-<\/span><span class=\"k\">admin<\/span>\n<span class=\"k\">Connection<\/span><span class=\"w\"> <\/span><span class=\"k\">to<\/span><span class=\"w\"> <\/span><span class=\"n\">cryptech<\/span><span class=\"p\">.<\/span><span class=\"k\">is<\/span><span class=\"w\"> <\/span><span class=\"n\">closed<\/span><span class=\"p\">.<\/span>\n<\/code><\/pre><\/div>\n\n<p>We can see the relevant cores and check them out one by one:<\/p>\n<div class=\"highlight\"><pre><span><\/span><code><span class=\"err\">#<\/span><span class=\"o\">&gt;<\/span><span class=\"w\"> <\/span><span class=\"n\">git<\/span><span class=\"w\"> <\/span><span class=\"n\">clone<\/span><span class=\"w\"> <\/span><span class=\"n\">git<\/span><span class=\"nv\">@git<\/span><span class=\"p\">.<\/span><span class=\"n\">cryptech<\/span><span class=\"p\">.<\/span><span class=\"k\">is<\/span><span class=\"err\">:<\/span><span class=\"n\">core<\/span><span class=\"o\">\/<\/span><span class=\"n\">sha1<\/span><span class=\"p\">.<\/span><span class=\"n\">git<\/span>\n<span class=\"err\">#<\/span><span class=\"o\">&gt;<\/span><span class=\"w\"> <\/span><span class=\"n\">git<\/span><span class=\"w\"> <\/span><span class=\"n\">clone<\/span><span class=\"w\"> <\/span><span class=\"n\">git<\/span><span class=\"nv\">@git<\/span><span class=\"p\">.<\/span><span class=\"n\">cryptech<\/span><span class=\"p\">.<\/span><span class=\"k\">is<\/span><span class=\"err\">:<\/span><span class=\"n\">core<\/span><span class=\"o\">\/<\/span><span class=\"n\">sha256<\/span><span class=\"p\">.<\/span><span class=\"n\">git<\/span>\n<span class=\"err\">#<\/span><span class=\"o\">&gt;<\/span><span class=\"w\"> <\/span><span class=\"n\">git<\/span><span class=\"w\"> <\/span><span class=\"n\">clone<\/span><span class=\"w\"> <\/span><span class=\"n\">git<\/span><span class=\"nv\">@git<\/span><span class=\"p\">.<\/span><span class=\"n\">cryptech<\/span><span class=\"p\">.<\/span><span class=\"k\">is<\/span><span class=\"err\">:<\/span><span class=\"n\">core<\/span><span class=\"o\">\/<\/span><span class=\"n\">uart<\/span><span class=\"p\">.<\/span><span class=\"n\">git<\/span>\n<span class=\"err\">#<\/span><span class=\"o\">&gt;<\/span><span class=\"w\"> <\/span><span class=\"n\">git<\/span><span class=\"w\"> <\/span><span class=\"n\">clone<\/span><span class=\"w\"> <\/span><span class=\"n\">git<\/span><span class=\"nv\">@git<\/span><span class=\"p\">.<\/span><span class=\"n\">cryptech<\/span><span class=\"p\">.<\/span><span class=\"k\">is<\/span><span class=\"err\">:<\/span><span class=\"n\">core<\/span><span class=\"o\">\/<\/span><span class=\"n\">coretest<\/span><span class=\"p\">.<\/span><span class=\"n\">git<\/span>\n<span class=\"err\">#<\/span><span class=\"o\">&gt;<\/span><span class=\"w\"> <\/span><span class=\"n\">git<\/span><span class=\"w\"> <\/span><span class=\"n\">clone<\/span><span class=\"w\"> <\/span><span class=\"n\">git<\/span><span class=\"nv\">@git<\/span><span class=\"p\">.<\/span><span class=\"n\">cryptech<\/span><span class=\"p\">.<\/span><span class=\"k\">is<\/span><span class=\"err\">:<\/span><span class=\"n\">core<\/span><span class=\"o\">\/<\/span><span class=\"n\">coretest_hashes<\/span><span class=\"p\">.<\/span><span class=\"n\">git<\/span>\n<\/code><\/pre><\/div>\n\n<p>We should now have a cores directory like this:<\/p>\n<div class=\"highlight\"><pre><span><\/span><code><span class=\"gh\">#<\/span>&gt; ls\ncoretest\/  coretest_hashes\/  sha1\/  sha256\/  uart\/\n<\/code><\/pre><\/div>\n\n<p>In each of these cores there are RTL and testbenches needed to simulate\nand build each of them. For example the sha1 core contains:<\/p>\n<div class=\"highlight\"><pre><span><\/span><code><span class=\"c1\">#&gt; cd sha1<\/span>\n<span class=\"c1\">#&gt; ls<\/span>\n<span class=\"n\">LICENSE<\/span><span class=\"o\">.<\/span><span class=\"n\">txt<\/span><span class=\"w\">  <\/span><span class=\"n\">README<\/span><span class=\"o\">.<\/span><span class=\"n\">md<\/span><span class=\"w\">  <\/span><span class=\"n\">src<\/span><span class=\"o\">\/<\/span><span class=\"w\">  <\/span><span class=\"n\">toolruns<\/span><span class=\"o\">\/<\/span>\n<\/code><\/pre><\/div>\n\n<p>The sha1 RTL source is in src\/rtl. Lets take a look:<\/p>\n<div class=\"highlight\"><pre><span><\/span><code><span class=\"gh\">#<\/span>&gt; cd src\/rtl\n<span class=\"gh\">#<\/span>&gt; ls\nsha1.v  sha1_core.v  sha1_w_mem.v\n<\/code><\/pre><\/div>\n\n<p>These files are:<\/p>\n<ul>\n<li>\n<p><code>sha1.v<\/code>: A top level wrapper that provides an interface to the core. In\n  this case a 32-bit memory like interface.<\/p>\n<\/li>\n<li>\n<p><code>sha1_core.v<\/code>: The actual SHA-1 hash function core.<\/p>\n<\/li>\n<li>\n<p><code>sha1_w_mem.v<\/code>: The W memory including sliding window functionality used\n  by the core.<\/p>\n<\/li>\n<\/ul>\n<p>The other cores follows a similar pattern with a top level wrapper named\n<code>&lt;core_name&gt;.v<\/code>, the main functionality in <code>&lt;core_name&gt;_core.v<\/code> and then one\nor more submodules.<\/p>\n<h2>Creating the project in Quartus<\/h2>\n<ul>\n<li>\n<p>Start Quartus and select file\/new... and select New Quartus II\n  Project.<\/p>\n<\/li>\n<li>\n<p>Select destination directory to be toolruns\/ in your project\n  directory.<\/p>\n<\/li>\n<li>\n<p>Set<code>'coretest_hashes<\/code> as name of the project<\/p>\n<\/li>\n<li>\n<p>Set <code>coretest_hashes<\/code> as nem of the top level design entity. (Should be\n  done automatically when entering the name of the project.)<\/p>\n<\/li>\n<li>\n<p>Press next.<\/p>\n<\/li>\n<li>\n<p>You should now be on the 'Add Files' page. Press '...'.<\/p>\n<\/li>\n<li>\n<p>Navigate to <code>test_coretest_hashes\/cores\/coretest\/src\/rtl<\/code>.<\/p>\n<\/li>\n<li>\n<p>Select coretest and press 'Open'. (Note: Quartus seems to sometimes omit the .v suffix\n  for the files depending on Windows\/OS version.)<\/p>\n<\/li>\n<li>\n<p>Back on the 'Add Files' page. Press Add to actually add coretest to\n  the project.<\/p>\n<\/li>\n<li>\n<p>Press '...' again and navigate to the rtl directory in\n  <code>coretest_hashes<\/code>. Add it like you did with coretest.<\/p>\n<\/li>\n<li>\n<p>Navigate to <code>test_coretest_hashes\/cores\/sha1\/src\/rtl<\/code> and add the files <code>sha1<\/code>, <code>sha1_core<\/code>,\n  <code>sha1_w_mem<\/code>. This time you don't need to press 'Add' on the 'Add\n  Files'. It is done automatically when adding more than one file at a\n  time.<\/p>\n<\/li>\n<li>\n<p>Navigate to <code>test_coretest_hashes\/cores\/sha256\/src\/rtl<\/code> and add the files <code>sha256<\/code>, <code>sha256_core<\/code>,\n  <code>sha256_k_constants<\/code>, <code>sha256_w_mem<\/code>. Do <strong>NOT<\/strong> add the file <code>wb_sha256<\/code>. This file contains an alternative top level wrapper to the one in <code>sha256.v<\/code> that instead provides a <a href=\"http:\/\/opencores.org\/opencores,wishbone\">WISHBONE<\/a> interface. This interface is not used in the <code>coretest_hashes<\/code> design.<\/p>\n<\/li>\n<li>\n<p>Finally navigate to <code>test_coretest_hashes\/cores\/uart\/src\/rtl<\/code> and add <code>uart<\/code>, <code>uart_core<\/code>.<\/p>\n<\/li>\n<\/ul>\n<p>Back on the 'Add Files page you should now see a list of source files:<\/p>\n<div class=\"highlight\"><pre><span><\/span><code><span class=\"c\">..\/cores\/uart\/src\/rtl\/uart_core.v<\/span>\n<span class=\"c\">..\/cores\/uart\/src\/rtl\/uart.v<\/span>\n<span class=\"c\">..\/cores\/sha256\/src\/rtl\/sha256_w_mem.v<\/span>\n<span class=\"c\">..\/cores\/sha256\/src\/rtl\/sha256_k_constants.v<\/span>\n<span class=\"c\">..\/cores\/sha256\/src\/rtl\/sha256_core.v<\/span>\n<span class=\"c\">..\/cores\/sha256\/src\/rtl\/sha256.v<\/span>\n<span class=\"c\">..\/cores\/sha1\/src\/rtl\/sha1_w_mem.v<\/span>\n<span class=\"c\">..\/cores\/sha1\/src\/rtl\/sha1_core.v<\/span>\n<span class=\"c\">..\/cores\/sha1\/src\/rtl\/sha1.v<\/span>\n<span class=\"c\">..\/cores\/coretest_hashes\/src\/rtl\/coretest_hashes.v<\/span>\n<span class=\"c\">..\/cores\/coretest\/src\/rtl\/coretest.v<\/span>\n<\/code><\/pre><\/div>\n\n<p>Press 'Next' to get to the 'Family &amp; Device Settings' page.<\/p>\n<ul>\n<li>\n<p>In 'Device Family', 'Family' list select 'Cyclone V (E\/GX\/GT\/SX\/SE\/ST)'.<\/p>\n<\/li>\n<li>\n<p>In 'Device Family', 'Devices' list select 'Cyclone V GX Extended Features'<\/p>\n<\/li>\n<li>\n<p>In the 'Available Devices' list select: 5CGXFC5C6F27C7.<\/p>\n<\/li>\n<\/ul>\n<p>Press 'Finish'.<\/p>\n<h2>Setting up and building the FPGA design<\/h2>\n<p>You should now be in the main Quartus II window. In the project\nnavigator you can see all files, open the source files etc.<\/p>\n<p>You could now just press 'Start Compilation' button in the menue row\n(the purple play\/triangle button.) This will build the complete\nsubsystem for the type of device selected. But the generated FPGA configuration image will not map to the correct pins on the C5G board. But this build should go through without errors or warnings related to problems in the source files. It is therefore a good test to see that all files has been included.<\/p>\n<p>The result from this generic build should be a FPGA configuration that\nuses 3666 registers, 2846 ALMs, 12 pins and can run at 88.3 MHz in worst\ncase temperature and timing.<\/p>\n<p>You now need to define the correct pins and define the clock to allow\nQuartus to create a FPGA configuration for our board.<\/p>\n<p>All pins needed are described in the C5G manual. To save time there is\nalso a pin list available in the <code>coretest_hashes<\/code> directory.<\/p>\n<ul>\n<li>\n<p>Navigate to <code>test_coretest_hashes\/cores\/coretest_hashes\/toolruns\/quartus\/terasic_c5g<\/code><\/p>\n<\/li>\n<li>\n<p>The file <code>coretest_hashes.qsf<\/code> contains assignments for a project like\n  the one we are setting up. It contains the pin assignments. The\n  follwing list is a slightly cleaned up version of the pin assignments:<\/p>\n<\/li>\n<\/ul>\n<div class=\"highlight\"><pre><span><\/span><code><span class=\"n\">set_location_assignment<\/span><span class=\"w\"> <\/span><span class=\"n\">PIN_R20<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">to<\/span><span class=\"w\"> <\/span><span class=\"n\">clk<\/span>\n<span class=\"n\">set_location_assignment<\/span><span class=\"w\"> <\/span><span class=\"n\">PIN_P11<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">to<\/span><span class=\"w\"> <\/span><span class=\"n\">reset_n<\/span>\n<span class=\"n\">set_location_assignment<\/span><span class=\"w\"> <\/span><span class=\"n\">PIN_M9<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">to<\/span><span class=\"w\"> <\/span><span class=\"n\">rxd<\/span>\n<span class=\"n\">set_location_assignment<\/span><span class=\"w\"> <\/span><span class=\"n\">PIN_L9<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">to<\/span><span class=\"w\"> <\/span><span class=\"n\">txd<\/span>\n<span class=\"n\">set_location_assignment<\/span><span class=\"w\"> <\/span><span class=\"n\">PIN_L7<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">to<\/span><span class=\"w\"> <\/span><span class=\"n\">debug<\/span><span class=\"p\">[<\/span><span class=\"mh\">0<\/span><span class=\"p\">]<\/span>\n<span class=\"n\">set_location_assignment<\/span><span class=\"w\"> <\/span><span class=\"n\">PIN_K6<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">to<\/span><span class=\"w\"> <\/span><span class=\"n\">debug<\/span><span class=\"p\">[<\/span><span class=\"mh\">1<\/span><span class=\"p\">]<\/span>\n<span class=\"n\">set_location_assignment<\/span><span class=\"w\"> <\/span><span class=\"n\">PIN_D8<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">to<\/span><span class=\"w\"> <\/span><span class=\"n\">debug<\/span><span class=\"p\">[<\/span><span class=\"mh\">2<\/span><span class=\"p\">]<\/span>\n<span class=\"n\">set_location_assignment<\/span><span class=\"w\"> <\/span><span class=\"n\">PIN_E9<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">to<\/span><span class=\"w\"> <\/span><span class=\"n\">debug<\/span><span class=\"p\">[<\/span><span class=\"mh\">3<\/span><span class=\"p\">]<\/span>\n<span class=\"n\">set_location_assignment<\/span><span class=\"w\"> <\/span><span class=\"n\">PIN_A5<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">to<\/span><span class=\"w\"> <\/span><span class=\"n\">debug<\/span><span class=\"p\">[<\/span><span class=\"mh\">4<\/span><span class=\"p\">]<\/span>\n<span class=\"n\">set_location_assignment<\/span><span class=\"w\"> <\/span><span class=\"n\">PIN_B6<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">to<\/span><span class=\"w\"> <\/span><span class=\"n\">debug<\/span><span class=\"p\">[<\/span><span class=\"mh\">5<\/span><span class=\"p\">]<\/span>\n<span class=\"n\">set_location_assignment<\/span><span class=\"w\"> <\/span><span class=\"n\">PIN_H8<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">to<\/span><span class=\"w\"> <\/span><span class=\"n\">debug<\/span><span class=\"p\">[<\/span><span class=\"mh\">6<\/span><span class=\"p\">]<\/span>\n<span class=\"n\">set_location_assignment<\/span><span class=\"w\"> <\/span><span class=\"n\">PIN_H9<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">to<\/span><span class=\"w\"> <\/span><span class=\"n\">debug<\/span><span class=\"p\">[<\/span><span class=\"mh\">7<\/span><span class=\"p\">]<\/span>\n<span class=\"n\">set_instance_assignment<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">name<\/span><span class=\"w\"> <\/span><span class=\"n\">IO_STANDARD<\/span><span class=\"w\"> <\/span><span class=\"s\">&quot;3.3-V LVTTL&quot;<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">to<\/span><span class=\"w\"> <\/span><span class=\"n\">clk<\/span>\n<span class=\"n\">set_instance_assignment<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">name<\/span><span class=\"w\"> <\/span><span class=\"n\">IO_STANDARD<\/span><span class=\"w\"> <\/span><span class=\"s\">&quot;1.2 V&quot;<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">to<\/span><span class=\"w\"> <\/span><span class=\"n\">reset_n<\/span>\n<span class=\"n\">set_instance_assignment<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">name<\/span><span class=\"w\"> <\/span><span class=\"n\">IO_STANDARD<\/span><span class=\"w\"> <\/span><span class=\"s\">&quot;2.5 V&quot;<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">to<\/span><span class=\"w\"> <\/span><span class=\"n\">txd<\/span>\n<span class=\"n\">set_instance_assignment<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">name<\/span><span class=\"w\"> <\/span><span class=\"n\">IO_STANDARD<\/span><span class=\"w\"> <\/span><span class=\"s\">&quot;2.5 V&quot;<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">to<\/span><span class=\"w\"> <\/span><span class=\"n\">rxd<\/span>\n<span class=\"n\">set_instance_assignment<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">name<\/span><span class=\"w\"> <\/span><span class=\"n\">IO_STANDARD<\/span><span class=\"w\"> <\/span><span class=\"s\">&quot;2.5 V&quot;<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">to<\/span><span class=\"w\"> <\/span><span class=\"n\">debug<\/span><span class=\"p\">[<\/span><span class=\"mh\">0<\/span><span class=\"p\">]<\/span>\n<span class=\"n\">set_instance_assignment<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">name<\/span><span class=\"w\"> <\/span><span class=\"n\">IO_STANDARD<\/span><span class=\"w\"> <\/span><span class=\"s\">&quot;2.5 V&quot;<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">to<\/span><span class=\"w\"> <\/span><span class=\"n\">debug<\/span><span class=\"p\">[<\/span><span class=\"mh\">1<\/span><span class=\"p\">]<\/span>\n<span class=\"n\">set_instance_assignment<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">name<\/span><span class=\"w\"> <\/span><span class=\"n\">IO_STANDARD<\/span><span class=\"w\"> <\/span><span class=\"s\">&quot;2.5 V&quot;<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">to<\/span><span class=\"w\"> <\/span><span class=\"n\">debug<\/span><span class=\"p\">[<\/span><span class=\"mh\">2<\/span><span class=\"p\">]<\/span>\n<span class=\"n\">set_instance_assignment<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">name<\/span><span class=\"w\"> <\/span><span class=\"n\">IO_STANDARD<\/span><span class=\"w\"> <\/span><span class=\"s\">&quot;2.5 V&quot;<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">to<\/span><span class=\"w\"> <\/span><span class=\"n\">debug<\/span><span class=\"p\">[<\/span><span class=\"mh\">3<\/span><span class=\"p\">]<\/span>\n<span class=\"n\">set_instance_assignment<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">name<\/span><span class=\"w\"> <\/span><span class=\"n\">IO_STANDARD<\/span><span class=\"w\"> <\/span><span class=\"s\">&quot;2.5 V&quot;<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">to<\/span><span class=\"w\"> <\/span><span class=\"n\">debug<\/span><span class=\"p\">[<\/span><span class=\"mh\">4<\/span><span class=\"p\">]<\/span>\n<span class=\"n\">set_instance_assignment<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">name<\/span><span class=\"w\"> <\/span><span class=\"n\">IO_STANDARD<\/span><span class=\"w\"> <\/span><span class=\"s\">&quot;2.5 V&quot;<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">to<\/span><span class=\"w\"> <\/span><span class=\"n\">debug<\/span><span class=\"p\">[<\/span><span class=\"mh\">5<\/span><span class=\"p\">]<\/span>\n<span class=\"n\">set_instance_assignment<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">name<\/span><span class=\"w\"> <\/span><span class=\"n\">IO_STANDARD<\/span><span class=\"w\"> <\/span><span class=\"s\">&quot;2.5 V&quot;<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">to<\/span><span class=\"w\"> <\/span><span class=\"n\">debug<\/span><span class=\"p\">[<\/span><span class=\"mh\">6<\/span><span class=\"p\">]<\/span>\n<span class=\"n\">set_instance_assignment<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">name<\/span><span class=\"w\"> <\/span><span class=\"n\">IO_STANDARD<\/span><span class=\"w\"> <\/span><span class=\"s\">&quot;2.5 V&quot;<\/span><span class=\"w\"> <\/span><span class=\"o\">-<\/span><span class=\"n\">to<\/span><span class=\"w\"> <\/span><span class=\"n\">debug<\/span><span class=\"p\">[<\/span><span class=\"mh\">7<\/span><span class=\"p\">]<\/span>\n<\/code><\/pre><\/div>\n\n<p>As you can see, for each pin we want to use we need to define the actual\npin in the FPGA (<code>PIN_R20<\/code> for example) and the I\/O standard the pin\nshould use\/support.<\/p>\n<p>In this design I've mapped the reset signal to the button 'KEY0' on the\nboard which you can find in the lower right corner. There is also a\ndebug port that in the <code>coretest_hashes<\/code> design is connected to the debug\nport in the uart. This allows us to see byte values received by the\nuart. This debug port is connected to pins that control the green LEDs\njust above the row of buttons that includes 'KEY0'.<\/p>\n<p>In order to enter the pin assignments select 'Assignments' in the\nQuartus top level menue bar. The select 'Assignment Editor'. Then either\nmanually enter each of the assignments above. This will require two rows\nfor each pin. For example for the clock ('clk') we would enter:<\/p>\n<ul>\n<li>Row 1: 'To': clk, 'Assignment name': Location, 'Value': <code>PIN_R20<\/code><\/li>\n<li>Row 2: 'To': clk, 'Assignment name': I\/O Standard, 'Value': 3.3-V LVTTL<\/li>\n<\/ul>\n<p>An easier way is to open up the file <code>coretest_hashes.qsf<\/code> in <code>test_coretest_hashes\/cores\/coretest_hashes\/toolruns\/quartus\/terasic_c5g<\/code> and add the pin assignment from that file to your qsf file in <code>test_coretest_hashes\/toolruns<\/code>. If you then open up the Assignments Editor the same definitions should be shown.<\/p>\n<p>We now need to define the clock. Under 'Assignments' in the top level\nmenue select 'TimeQuest Timing Analyzer Wizard'. Press 'Next' to get\nfrom the 'Intro' page.<\/p>\n<p>Under 'Specify base clock settings' enter 'clk' as 'Clock Name' and\n'Input Pin'. Enter '20' in 'Period' and note that 'ns' is selected as\ntime scale. In the 'Equivalent SDC Commands' you should see:<\/p>\n<div class=\"highlight\"><pre><span><\/span><code>  create_clock -name &quot;clk&quot; -period 20.000ns [get_ports {clk}]\n<\/code><\/pre><\/div>\n\n<p>Now press 'Next' four times to get to the final page and then press\n'Finish' to complete the clock setup. If we now look in the\n<code>test_coretest_hashes\/toolruns<\/code> directory there should be a file called\n<code>coretest_hashes.sdc<\/code> that contains the SDC command above.<\/p>\n<p>Now we are ready to build the real FPGA configuration. Press the purple\n'Start Compilation' button again. After build we should now have an FPGA\nconfiguration that requires 2852 ALMs, 3666 registers, 12 pins and meets\ntiming. The max clock frequency for the design should be about 72 MHz.<\/p>\n<p>Time to load the design onto the board.<\/p>\n<h2>Configuring the FPGA on the C5G board<\/h2>\n<p>If you haven't turned on the C5G board and connected the board to the\ncomputer Quartus is installed on, do so now. You should see the\n7-segment displays and LEDs start flashing in a simple sequence. This\nshows that the default configuration in the FPGA has been loaded and the\nboard works.<\/p>\n<p>In Quartus now locate the 'Programmer' menue button (it looks like a\nchip with waves). Alternatively Select 'Tools' in the top level Menue\nand then 'Programmer'.<\/p>\n<p>In the Programmer window if everything is working magically we should\nsee a list view with <code>toolruns\/output_files\/coretest_hashes.sof<\/code>\nselected. And below this list a graphic that shows a 'TDI' arrow\npointing to an Altera 5CGXFC5C6F27C7 device with a 'TDO' going out from\nthe device.<\/p>\n<p>If the graphic is not showing (probably), you need to press 'Hardware\nSetup'. In the Window you should see 'USB-blaster'. If not you need to\nfix the drivers for the USB-blaster in your OS. If the USB-blaster is\npresent make sure it is selected and then press 'Close'.<\/p>\n<p>If the file is not showing, in the main Programmer window, select 'Add\nFile' and navigate and to <code>toolruns\/output_files<\/code> in the <code>project<\/code>\ndirectory. Select <code>coretest_hashes.sof<\/code> and press 'Open'.<\/p>\n<p>In the main Programmer window now press 'Start' to start\nprogramming. When this has been completed (See 'Progress' in the upper\nright hand corner in the Programmer board) the LEDs etc should have\nstopped blinking. We should now have <code>coretest_hashes<\/code> alive on the\ndevelopment board. Time for host communication and testing!<\/p>\n<h2>Talking to <code>coretest_hashes<\/code> and test of SHA-1 and SHA-256<\/h2>\n<p>There is a (currently rather ugly) test program for\n<code>coretest_hashes<\/code>. Navigate to <code>test_coretest_hashes\/cores\/coretest_hashes\/src\/sw<\/code><\/p>\n<div class=\"highlight\"><pre><span><\/span><code><span class=\"gh\">#<\/span>&gt; ls\nhash_tester.py\n<\/code><\/pre><\/div>\n\n<p>This is a Python2.x program that uses Pyserial <a href=\"http:\/\/pyserial.sourceforge.net\/\">5<\/a> to open up a serial\nport and talk to coretest via the uart. The command and response format\nused is a very simple byte oriented format. For more info, see the\nREADME.md in <a href=\"https:\/\/git.cryptech.is\/core\/coretest\">the top of coretest<\/a>.<\/p>\n<p>The program <code>hash_tester.py<\/code> needs to know which serial interface to\nuse. This is defined in the main() function (yes, VERY ugly). You will\nneed to edit the program source to point to the serial interface\nconnected to the USB-serial chip on the C5G board. For me that device\nis:<\/p>\n<div class=\"highlight\"><pre><span><\/span><code>  ser.port=&#39;\/dev\/cu.usbserial-A801SA6T&#39;\n<\/code><\/pre><\/div>\n\n<p>If everthing is working properly you should now just have to do:<\/p>\n<div class=\"highlight\"><pre><span><\/span><code>  python hash_tester.py\n<\/code><\/pre><\/div>\n\n<p>If the communication has been set up properly you should now see:<\/p>\n<div class=\"highlight\"><pre><span><\/span><code><span class=\"w\">  <\/span><span class=\"nx\">TC1<\/span><span class=\"o\">-<\/span><span class=\"mi\">1<\/span><span class=\"p\">:<\/span><span class=\"w\"> <\/span><span class=\"nx\">Reading<\/span><span class=\"w\"> <\/span><span class=\"nx\">name<\/span><span class=\"p\">,<\/span><span class=\"w\"> <\/span><span class=\"k\">type<\/span><span class=\"w\"> <\/span><span class=\"k\">and<\/span><span class=\"w\"> <\/span><span class=\"nx\">version<\/span><span class=\"w\"> <\/span><span class=\"nx\">words<\/span><span class=\"w\"> <\/span><span class=\"nx\">from<\/span><span class=\"w\"> <\/span><span class=\"nx\">SHA<\/span><span class=\"o\">-<\/span><span class=\"mi\">1<\/span><span class=\"w\"> <\/span><span class=\"nx\">core<\/span><span class=\"p\">.<\/span>\n<span class=\"w\">  <\/span><span class=\"nx\">READ_OK<\/span><span class=\"p\">.<\/span><span class=\"w\"> <\/span><span class=\"nx\">address<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x1000<\/span><span class=\"w\"> <\/span><span class=\"p\">=<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x73686131<\/span><span class=\"p\">.<\/span>\n<span class=\"w\">  <\/span><span class=\"nx\">READ_OK<\/span><span class=\"p\">.<\/span><span class=\"w\"> <\/span><span class=\"nx\">address<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x1001<\/span><span class=\"w\"> <\/span><span class=\"p\">=<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x20202020<\/span><span class=\"p\">.<\/span>\n<span class=\"w\">  <\/span><span class=\"nx\">READ_OK<\/span><span class=\"p\">.<\/span><span class=\"w\"> <\/span><span class=\"nx\">address<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x1002<\/span><span class=\"w\"> <\/span><span class=\"p\">=<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x302e3530<\/span><span class=\"p\">.<\/span>\n<span class=\"w\">  <\/span><span class=\"o\">...<\/span>\n<\/code><\/pre><\/div>\n\n<p>That is the first test case that reads from specific registers in the\nSHA-1 core. If we look in <code>sha1\/src\/rtl\/sha1.v<\/code> there are some defines:<\/p>\n<div class=\"highlight\"><pre><span><\/span><code>  parameter CORE_NAME0     = 32&#39;h73686131; \/\/ &quot;sha1&quot;\n  parameter CORE_NAME1     = 32&#39;h20202020; \/\/ &quot;    &quot;\n  parameter CORE_VERSION   = 32&#39;h302e3530; \/\/ &quot;0.50&quot;\n<\/code><\/pre><\/div>\n\n<p>As we can see those hex values matches what is being read from the FPGA\nand is the name and version strings in the core.<\/p>\n<p>Moving on, <code>hash_tester.py<\/code> also performs single block message hash tests\nof both the SHA-1 and SHA-256 core. The message is \"abc\" padded to the\ncorrect block size for SHA-1 and SHA-256. These tests are defined by\nNIST including the expected result in <a href=\"http:\/\/csrc.nist.gov\/groups\/ST\/toolkit\/documents\/Examples\/SHA_All.pdf\">6<\/a>. The block is written as a\nsequence of 32-bit words to addresses mapped to the block registers in\nthe sha1 core.<\/p>\n<p>Finally we set the <code>init_flag<\/code> in the control register in\nsha1 to one which should make the sha1 core initialize and then process\nthe first (of possible several) message block. This takes in total 82\ncycles for the core. This means that by the time the host gets the\n<code>WRITE_OK. address 0x1008.<\/code> message, the core is done since many cycles\nago. We therefore check status and try to extract the digest.<\/p>\n<p>Looking at the output from <code>hash_tester.py<\/code> we see:<\/p>\n<div class=\"highlight\"><pre><span><\/span><code><span class=\"w\">  <\/span><span class=\"nx\">TC1<\/span><span class=\"o\">-<\/span><span class=\"mi\">3<\/span><span class=\"p\">:<\/span><span class=\"w\"> <\/span><span class=\"nx\">Reading<\/span><span class=\"w\"> <\/span><span class=\"nx\">SHA<\/span><span class=\"o\">-<\/span><span class=\"mi\">1<\/span><span class=\"w\"> <\/span><span class=\"nx\">status<\/span><span class=\"w\"> <\/span><span class=\"k\">and<\/span><span class=\"w\"> <\/span><span class=\"nx\">digest<\/span><span class=\"p\">.<\/span>\n<span class=\"w\">  <\/span><span class=\"nx\">READ_OK<\/span><span class=\"p\">.<\/span><span class=\"w\"> <\/span><span class=\"nx\">address<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x1009<\/span><span class=\"w\"> <\/span><span class=\"p\">=<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x00000003<\/span><span class=\"p\">.<\/span>\n<span class=\"w\">  <\/span><span class=\"nx\">READ_OK<\/span><span class=\"p\">.<\/span><span class=\"w\"> <\/span><span class=\"nx\">address<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x1020<\/span><span class=\"w\"> <\/span><span class=\"p\">=<\/span><span class=\"w\"> <\/span><span class=\"mh\">0xa9993e36<\/span><span class=\"p\">.<\/span>\n<span class=\"w\">  <\/span><span class=\"nx\">READ_OK<\/span><span class=\"p\">.<\/span><span class=\"w\"> <\/span><span class=\"nx\">address<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x1021<\/span><span class=\"w\"> <\/span><span class=\"p\">=<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x4706816a<\/span><span class=\"p\">.<\/span>\n<span class=\"w\">  <\/span><span class=\"nx\">READ_OK<\/span><span class=\"p\">.<\/span><span class=\"w\"> <\/span><span class=\"nx\">address<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x1022<\/span><span class=\"w\"> <\/span><span class=\"p\">=<\/span><span class=\"w\"> <\/span><span class=\"mh\">0xba3e2571<\/span><span class=\"p\">.<\/span>\n<span class=\"w\">  <\/span><span class=\"nx\">READ_OK<\/span><span class=\"p\">.<\/span><span class=\"w\"> <\/span><span class=\"nx\">address<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x1023<\/span><span class=\"w\"> <\/span><span class=\"p\">=<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x7850c26c<\/span><span class=\"p\">.<\/span>\n<span class=\"w\">  <\/span><span class=\"nx\">READ_OK<\/span><span class=\"p\">.<\/span><span class=\"w\"> <\/span><span class=\"nx\">address<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x1024<\/span><span class=\"w\"> <\/span><span class=\"p\">=<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x9cd0d89d<\/span><span class=\"p\">.<\/span>\n<\/code><\/pre><\/div>\n\n<p>Address 0x1009 corresponds to address 0x09 in the SHA-1 core. This\naddress contains the status of the core. 0x03 means that the data in the\ndigest is valid and that the core is ready to accept now commnands.<\/p>\n<p>The digest generated by the sha1 core is in MSB format which means that\nthe digest generated is:<\/p>\n<div class=\"highlight\"><pre><span><\/span><code>  0xa9993e36 0x4706816a 0xba3e2571 0x7850c26c 0x9cd0d89d\n<\/code><\/pre><\/div>\n\n<p>If we compare that to the expected result in <a href=\"http:\/\/csrc.nist.gov\/groups\/ST\/toolkit\/documents\/Examples\/SHA_All.pdf\">6<\/a> we can see that this is\ncorrect. Similarly, for SHA-256 we get:<\/p>\n<div class=\"highlight\"><pre><span><\/span><code><span class=\"w\">  <\/span><span class=\"nx\">TC2<\/span><span class=\"o\">-<\/span><span class=\"mi\">3<\/span><span class=\"p\">:<\/span><span class=\"w\"> <\/span><span class=\"nx\">Reading<\/span><span class=\"w\"> <\/span><span class=\"nx\">SHA<\/span><span class=\"o\">-<\/span><span class=\"mi\">256<\/span><span class=\"w\"> <\/span><span class=\"nx\">status<\/span><span class=\"w\"> <\/span><span class=\"k\">and<\/span><span class=\"w\"> <\/span><span class=\"nx\">digest<\/span><span class=\"p\">.<\/span>\n<span class=\"w\">  <\/span><span class=\"nx\">READ_OK<\/span><span class=\"p\">.<\/span><span class=\"w\"> <\/span><span class=\"nx\">address<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x2009<\/span><span class=\"w\"> <\/span><span class=\"p\">=<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x00000003<\/span><span class=\"p\">.<\/span>\n<span class=\"w\">  <\/span><span class=\"nx\">READ_OK<\/span><span class=\"p\">.<\/span><span class=\"w\"> <\/span><span class=\"nx\">address<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x2020<\/span><span class=\"w\"> <\/span><span class=\"p\">=<\/span><span class=\"w\"> <\/span><span class=\"mh\">0xba7816bf<\/span><span class=\"p\">.<\/span>\n<span class=\"w\">  <\/span><span class=\"nx\">READ_OK<\/span><span class=\"p\">.<\/span><span class=\"w\"> <\/span><span class=\"nx\">address<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x2021<\/span><span class=\"w\"> <\/span><span class=\"p\">=<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x8f01cfea<\/span><span class=\"p\">.<\/span>\n<span class=\"w\">  <\/span><span class=\"nx\">READ_OK<\/span><span class=\"p\">.<\/span><span class=\"w\"> <\/span><span class=\"nx\">address<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x2022<\/span><span class=\"w\"> <\/span><span class=\"p\">=<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x414140de<\/span><span class=\"p\">.<\/span>\n<span class=\"w\">  <\/span><span class=\"nx\">READ_OK<\/span><span class=\"p\">.<\/span><span class=\"w\"> <\/span><span class=\"nx\">address<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x2023<\/span><span class=\"w\"> <\/span><span class=\"p\">=<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x5dae2223<\/span><span class=\"p\">.<\/span>\n<span class=\"w\">  <\/span><span class=\"nx\">READ_OK<\/span><span class=\"p\">.<\/span><span class=\"w\"> <\/span><span class=\"nx\">address<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x2024<\/span><span class=\"w\"> <\/span><span class=\"p\">=<\/span><span class=\"w\"> <\/span><span class=\"mh\">0xb00361a3<\/span><span class=\"p\">.<\/span>\n<span class=\"w\">  <\/span><span class=\"nx\">READ_OK<\/span><span class=\"p\">.<\/span><span class=\"w\"> <\/span><span class=\"nx\">address<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x2025<\/span><span class=\"w\"> <\/span><span class=\"p\">=<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x96177a9c<\/span><span class=\"p\">.<\/span>\n<span class=\"w\">  <\/span><span class=\"nx\">READ_OK<\/span><span class=\"p\">.<\/span><span class=\"w\"> <\/span><span class=\"nx\">address<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x2026<\/span><span class=\"w\"> <\/span><span class=\"p\">=<\/span><span class=\"w\"> <\/span><span class=\"mh\">0xb410ff61<\/span><span class=\"p\">.<\/span>\n<span class=\"w\">  <\/span><span class=\"nx\">READ_OK<\/span><span class=\"p\">.<\/span><span class=\"w\"> <\/span><span class=\"nx\">address<\/span><span class=\"w\"> <\/span><span class=\"mh\">0x2027<\/span><span class=\"w\"> <\/span><span class=\"p\">=<\/span><span class=\"w\"> <\/span><span class=\"mh\">0xf20015ad<\/span><span class=\"p\">.<\/span>\n<\/code><\/pre><\/div>\n\n<p>The digest generated is thus:<\/p>\n<div class=\"highlight\"><pre><span><\/span><code>  0xba7816bf 0x8f01cfea 0x414140de 0x5dae2223\n  0xb00361a3 0x96177a9c 0xb410ff61 0xf20015ad\n<\/code><\/pre><\/div>\n\n<p>Which again matches what is specified in <a href=\"http:\/\/csrc.nist.gov\/groups\/ST\/toolkit\/documents\/Examples\/SHA_All.pdf\">6<\/a><\/p>\n<h2>Summary<\/h2>\n<p>We have now set up a complete development and verification environment\nfor Cryptech. We have setup and built the <code>coretest_hashes<\/code> subsystem for\nthe TerasIC C5G board. Finally we have connected to <code>coretest_hashes<\/code> from\nSW in the host and verified that we can write to and receive response\nneeded to perform SHA-1 and SHA-256 hash operations and get correct\ndigest back.<\/p>\n<p>If you have not been able to complete this, please contact me (Joachim Str\u00f6mbergson).<\/p>\n<p>Happy Hashing!<\/p>\n<h2>References<\/h2>\n<ul>\n<li><\/li>\n<li><\/li>\n<li><\/li>\n<li><\/li>\n<li><\/li>\n<li><\/li>\n<li><\/li>\n<li><\/li>\n<\/ul>","category":{"@attributes":{"term":"misc"}}},{"title":"dev-bridge board","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/DevBridgeBoard","rel":"alternate"}},"published":"2016-12-15T22:43:00+00:00","updated":"2021-02-14T17:30:00+00:00","author":{"name":"Paul Selkirk"},"id":"tag:wiki.cryptech.is,2016-12-15:\/DevBridgeBoard","summary":"<p>In the process of developing the <a href=\"https:\/\/wiki.cryptech.is\/AlphaBoardComponents\">AlphaBoardComponents<\/a> design, the project has made what is known as the \"dev-bridge board\".<\/p>\n<p>This is a board, 100x70 mm, with about 2\/3 of the components intended to be on the Alpha design. What is missing is basically the FPGA and it's supporting circuits \u2026<\/p>","content":"<p>In the process of developing the <a href=\"https:\/\/wiki.cryptech.is\/AlphaBoardComponents\">AlphaBoardComponents<\/a> design, the project has made what is known as the \"dev-bridge board\".<\/p>\n<p>This is a board, 100x70 mm, with about 2\/3 of the components intended to be on the Alpha design. What is missing is basically the FPGA and it's supporting circuits.<\/p>\n<p>To date, the dev-bridge board has been used to implement and validate the FMC based interface that will be used to connect the ARM and the FPGA on the Alpha.<\/p>\n<p>Schematics and layouts are at <a href=\"https:\/\/wiki.cryptech.is\/browser\/user\/ft\/stm32-dev-bridge\/hardware\/rev01\">user\/ft\/stm32-dev-bridge\/hardware\/rev01<\/a>.<\/p>\n<p>High resolution pictures of rev01 of the dev-bridge board are attached at the bottom of this page, but the following should be more than sufficient to read the silkscreens.<\/p>\n<p><img alt=\"dev-bridge_rev01_front_medium.jpg\" src=\"https:\/\/wiki.cryptech.is\/DevBridgeBoard\/DevBridgeBoard\/dev-bridge_rev01_front_medium.jpg\"><\/p>\n<p><img alt=\"dev-bridge_rev01_back_medium.jpg\" src=\"https:\/\/wiki.cryptech.is\/DevBridgeBoard\/DevBridgeBoard\/dev-bridge_rev01_back_medium.jpg\"><\/p>\n<p>Here is the board mounted on the Novena, attached to the programmer:<\/p>\n<p><img alt=\"IMG_9983s.jpg\" src=\"https:\/\/wiki.cryptech.is\/DevBridgeBoard\/DevBridgeBoard\/IMG_9983s.jpg\"><\/p>\n<p>Note that it's rather bigger than the Netgear enclosure I use to transport the Novena. (Not only does it protect the board, but I have this superstition that TSA is more comfortable with a home gateway than a bare motherboard.)<\/p>\n<p>Also note that the dev-bridge board is connected to the Novena by the\nhigh-speed expansion connector, which forms a bit of a pivot point.\nAs Pavel says, \"High speed and mechanical reliability are not very good\nfriends usually.\"<\/p>\n<p>For that reason, I highly recommend stabilizing the board by bolting it to\nthe Novena with a 5mm spacer. There are two through-holes that line up\nwith mounting holes on the Novena, one at the corner and one next to the\nwifi connector.  I've found that even one bolt is enough to stabilize the\nboard.<\/p>\n<p>Finally note that the board traces come rather close to the through-holes, so\nyou want to avoid scraping them with the bolt head or the nut. I happen to\nbe using a countersink-head bolt, which is beveled toward the shaft, but\nit's probably even better to use a nylon washer.<\/p>\n<p>All the software, as well as flashing instructions, are at <a href=\"https:\/\/git.cryptech.is\/sw\/stm32.md\">sw\/stm32<\/a>.<\/p>","category":{"@attributes":{"term":"misc"}}},{"title":"Presentations and Design Documents","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/Documents","rel":"alternate"}},"published":"2016-12-15T22:43:00+00:00","updated":"2016-12-15T22:43:00+00:00","author":{"name":"Cryptech Core Team"},"id":"tag:wiki.cryptech.is,2016-12-15:\/Documents","content":"<p><a href=\"https:\/\/wiki.cryptech.is\/RandomnessTesting\">Randomness Testing Tools<\/a><br\/><\/p>\n<p><a href=\"https:\/\/wiki.cryptech.is\/AlphaBoardStrategy\">Alpha board strategy<\/a><\/p>\n<p><a href=\"https:\/\/git.cryptech.is\/doc\/design\/tree\/Alpha_board_drawing.pdf\">Alpha board drawing<\/a><\/p>\n<p><a href=\"https:\/\/wiki.cryptech.is\/AlphaBoardPictures\">Alpha board pictures<\/a><\/p>\n<p>Placeholder until somebody fills this in with something else interesting.<\/p>","category":{"@attributes":{"term":"misc"}}},{"title":"EDA Toolchain Survey","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/EDAToolchainSurvey","rel":"alternate"}},"published":"2016-12-15T22:43:00+00:00","updated":"2016-12-15T22:43:00+00:00","author":{"name":"Cryptech Core Team"},"id":"tag:wiki.cryptech.is,2016-12-15:\/EDAToolchainSurvey","summary":"<p>The major issue is finding tools that allows a designer, user to\nverify that the RTL source code (in Verilog or VHDL) matches what is\ngenerated at the physical level. As part of the project we need to\ninvestigate the current status of open tools in the toolchain for\nimplementation \u2026<\/p>","content":"<p>The major issue is finding tools that allows a designer, user to\nverify that the RTL source code (in Verilog or VHDL) matches what is\ngenerated at the physical level. As part of the project we need to\ninvestigate the current status of open tools in the toolchain for\nimplementation and verification of hardware. This includes RTL\nsimulation, synthesis, place &amp; route, netlist verification, timing\nanalysis and configuration file generation and analysis. (This implies\nthat the target is an FPGA.). If there are no open tools we need to\nfind ways of verifying pre- and post-functionality to check that the\nblack box tool does not alter (subvert) the design in ways not\nintended.<\/p>\n<p>The basic action flow is:<\/p>\n<ul>\n<li>Finding open EDA tools and assess their status<\/li>\n<li>Settling for Closed<\/li>\n<li>Strategy to Develop Trust in Tools<\/li>\n<li>Validation Methods for Output<\/li>\n<\/ul>\n<p>Some tools and frameworks worth investigating are:<\/p>\n<ul>\n<li><a href=\"http:\/\/www.optimsoc.org\/index.html\">OpTiMSoC<\/a> - An open System on Chip (SoC) framework built around the OpenRISC CPU.<\/li>\n<li><a href=\"http:\/\/iverilog.icarus.com\/\">Icarus Verilog<\/a> - An open Verilog event driven simulator that supports Verilog 2001, 2005 and SystemVerilog.<\/li>\n<li><a href=\"http:\/\/www.geda-project.org\/\">gEDA<\/a> - A project that aims at developing GNU based EDA tools.<\/li>\n<li><a href=\"http:\/\/www.gpleda.org\/\">gplEDA<\/a> - A collection of GPL licensed EDA tools. Points to gEDA.<\/li>\n<\/ul>","category":{"@attributes":{"term":"misc"}}},{"title":"Project Metadata","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/ProjectMetadata","rel":"alternate"}},"published":"2016-12-15T22:43:00+00:00","updated":"2016-12-15T22:43:00+00:00","author":{"name":"Cryptech Core Team"},"id":"tag:wiki.cryptech.is,2016-12-15:\/ProjectMetadata","content":"<h2>Project Logo Files<\/h2>\n<ul>\n<li>See \"Attachments\" at the bottom of this page<\/li>\n<li>PhotoFolder<\/li>\n<\/ul>\n<p>==\u00a0Meeting Presentations\u00a0and Notes ==<\/p>\n<ul>\n<li><a href=\"https:\/\/wiki.cryptech.is\/DocMeet\">DocMeet<\/a><\/li>\n<li><a href=\"https:\/\/wiki.cryptech.is\/PrahaWorkshop\">PrahaWorkshop<\/a><\/li>\n<li><a href=\"https:\/\/wiki.cryptech.is\/BerlinWorkshop\">BerlinWorkshop<\/a><\/li>\n<\/ul>\n<p>==\u00a0Technical\u00a0References ==<\/p>\n<ul>\n<li><a href=\"https:\/\/wiki.cryptech.is\/MiscStuff\">MiscStuff<\/a><\/li>\n<li><a href=\"https:\/\/wiki.cryptech.is\/InterconnectStandards\">InterconnectStandards<\/a><\/li>\n<li><a href=\"https:\/\/wiki.cryptech.is\/RandomnessTesting\">RandomnessTesting<\/a><\/li>\n<\/ul>\n<p>==\u00a0Related\u00a0Work ==<\/p>\n<ul>\n<li><a href=\"https:\/\/wiki.cryptech.is\/RelatedWork\">RelatedWork<\/a><\/li>\n<li><a href=\"https:\/\/wiki.cryptech.is\/SideChannel\">SideChannel<\/a><\/li>\n<\/ul>","category":{"@attributes":{"term":"misc"}}},{"title":"Quick Start","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/QuickStart","rel":"alternate"}},"published":"2016-12-15T22:43:00+00:00","updated":"2017-05-13T20:39:00+00:00","author":{"name":"Cryptech Core Team"},"id":"tag:wiki.cryptech.is,2016-12-15:\/QuickStart","summary":"<p><em>Page Under Development<\/em><\/p>\n<h2>Git Repositories<\/h2>\n<p>The team uses Git to store and track project development. All submissions are <a href=\"https:\/\/git-scm.com\/book\/en\/v2\/Git-Tools-Signing-Your-Work\">signed<\/a>.<\/p>\n<h2>The Alpha Board<\/h2>\n<p>The current hardware is the AlphaBoard.  More information (to be organized at some point -- yes, this wiki is a mess, again):<\/p>\n<ul>\n<li><a href=\"https:\/\/wiki.cryptech.is\/AlphaBoardComponents\">AlphaBoardComponents<\/a><\/li>\n<li><a href=\"https:\/\/wiki.cryptech.is\/AlphaBoardPictures\">AlphaBoardPictures<\/a><\/li>\n<li><a href=\"https:\/\/wiki.cryptech.is\/AlphaBoardStrategy\">AlphaBoardStrategy<\/a><\/li>\n<li><a href=\"https:\/\/wiki.cryptech.is\/AlphaReviewLog\">AlphaReviewLog<\/a><\/li>\n<li><a href=\"https:\/\/wiki.cryptech.is\/AlphaSchematics\">AlphaSchematics<\/a><\/li>\n<\/ul>\n<p>The Alpha \u2026<\/p>","content":"<p><em>Page Under Development<\/em><\/p>\n<h2>Git Repositories<\/h2>\n<p>The team uses Git to store and track project development. All submissions are <a href=\"https:\/\/git-scm.com\/book\/en\/v2\/Git-Tools-Signing-Your-Work\">signed<\/a>.<\/p>\n<h2>The Alpha Board<\/h2>\n<p>The current hardware is the AlphaBoard.  More information (to be organized at some point -- yes, this wiki is a mess, again):<\/p>\n<ul>\n<li><a href=\"https:\/\/wiki.cryptech.is\/AlphaBoardComponents\">AlphaBoardComponents<\/a><\/li>\n<li><a href=\"https:\/\/wiki.cryptech.is\/AlphaBoardPictures\">AlphaBoardPictures<\/a><\/li>\n<li><a href=\"https:\/\/wiki.cryptech.is\/AlphaBoardStrategy\">AlphaBoardStrategy<\/a><\/li>\n<li><a href=\"https:\/\/wiki.cryptech.is\/AlphaReviewLog\">AlphaReviewLog<\/a><\/li>\n<li><a href=\"https:\/\/wiki.cryptech.is\/AlphaSchematics\">AlphaSchematics<\/a><\/li>\n<\/ul>\n<p>The Alpha board currently ships with very old firmware, but you can <a href=\"https:\/\/wiki.cryptech.is\/Upgrading\">upgrade it yourself<\/a>.<\/p>\n<h2>DNSSEC signing using OpenDNSSEC<\/h2>\n<ul>\n<li><a href=\"https:\/\/wiki.cryptech.is\/OpenDNSSEC\">OpenDNSSEC<\/a><\/li>\n<\/ul>","category":{"@attributes":{"term":"misc"}}},{"title":"Rough Cut at v0.01 Proof of Concept Feature Set","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/RoughV1","rel":"alternate"}},"published":"2016-12-15T22:43:00+00:00","updated":"2021-02-14T17:33:00+00:00","author":{"name":"Cryptech Core Team"},"id":"tag:wiki.cryptech.is,2016-12-15:\/RoughV1","summary":"<p>This is a proposed version 0.01 product as a proof of concept.  The\nintent is not to have a very useful product, but rather to gain\nconfidence in our architecture, tools, and team.  The result is intended\nto be the basis for further development into a more useful second \u2026<\/p>","content":"<p>This is a proposed version 0.01 product as a proof of concept.  The\nintent is not to have a very useful product, but rather to gain\nconfidence in our architecture, tools, and team.  The result is intended\nto be the basis for further development into a more useful second stage,\nin the sense of\n<a href=\"https:\/\/en.wikipedia.org\/wiki\/Agile_software_development\">agile development<\/a>.\nIt very intentionally is not a\n<a href=\"https:\/\/en.wikipedia.org\/wiki\/Waterfall_model\">waterfall design<\/a>,<\/p>\n<p>The interface between the Green and Yellow layers is seen as an important design\ninflection.<\/p>\n<p>Some code will be in C in the Green (auxiliary core) because we can get it open\nsource out of the can.  for v.2 (or whatever) we would move it down to the FPGA in\nVerilog.<\/p>\n<h2>FPGA Overview<\/h2>\n<p><img alt=\"HW_sketch_v0001.png\" src=\"https:\/\/wiki.cryptech.is\/RoughV1\/RoughV1\/HW_sketch_v0001.png\">\n<br\/>\n<br\/><\/p>\n<h2>Sketch of TRNG Chain<\/h2>\n<p><img alt=\"HW_RNG.png\" src=\"https:\/\/wiki.cryptech.is\/RoughV1\/RoughV1\/HW_RNG.png\">\n<br\/>\n<br\/><\/p>\n<h2>Off-FPGA<\/h2>\n<ul>\n<li>Persistent Storage<ul>\n<li>For Keys and Time<\/li>\n<li>Or the battery for tamper wipe is big enough to hold the FPGA up<\/li>\n<li>Or the Green processor has enough non-volatile store<\/li>\n<\/ul>\n<\/li>\n<li>Entropy Source<\/li>\n<li>Realtime Clock<\/li>\n<li>Tamper Mechanism<\/li>\n<\/ul>\n<h2>Layers<\/h2>\n<div class=\"highlight\"><pre><span><\/span><code>#!html\n<span class=\"nt\">&lt;h1<\/span><span class=\"w\"> <\/span><span class=\"na\">style=<\/span><span class=\"s\">&quot;text-align: left; color: blue&quot;<\/span><span class=\"nt\">&gt;<\/span>\n<span class=\"w\">  <\/span>Blue<span class=\"w\"> <\/span>\/<span class=\"w\"> <\/span>FPGA\n<span class=\"nt\">&lt;\/h1&gt;<\/span>\n<\/code><\/pre><\/div>\n\n<ul>\n<li>TRNG<\/li>\n<li>BigNumber, Modular, &amp; Exponentiation (expose to green for RSA)<\/li>\n<li>SHA-256<\/li>\n<li>AES-128<\/li>\n<li>EC for ECDH. Curve3617 would be nice, but whatever we can get open source to start<\/li>\n<li>OpenRISC Core or ARM to support Green (maybe FreeScale from Bunnie)<\/li>\n<\/ul>\n<div class=\"highlight\"><pre><span><\/span><code>#!html\n<span class=\"nt\">&lt;h1<\/span><span class=\"w\"> <\/span><span class=\"na\">style=<\/span><span class=\"s\">&quot;text-align: left; color: green&quot;<\/span><span class=\"nt\">&gt;<\/span>\n<span class=\"w\">  <\/span>Green<span class=\"w\"> <\/span>\/<span class=\"w\"> <\/span>On-Chip<span class=\"w\"> <\/span>Core\n<span class=\"nt\">&lt;\/h1&gt;<\/span>\n<\/code><\/pre><\/div>\n\n<ul>\n<li>RSA 2048 &amp; 4096 (move to blue later) [ 1024 for Tor? ]<\/li>\n<li>MACs: HMAC, 1305, uMAC<\/li>\n<li>DH (move to blue later)<\/li>\n<li>Device Activation, Move Authorization, Wiping<\/li>\n<\/ul>\n<div class=\"highlight\"><pre><span><\/span><code>#!html\n<span class=\"nt\">&lt;h1<\/span><span class=\"w\"> <\/span><span class=\"na\">style=<\/span><span class=\"s\">&quot;text-align: left; color: yellow&quot;<\/span><span class=\"nt\">&gt;<\/span>\n<span class=\"w\">  <\/span>Yellow<span class=\"w\"> <\/span>\/<span class=\"w\"> <\/span>Off-Chip<span class=\"w\"> <\/span>Support\n<span class=\"nt\">&lt;\/h1&gt;<\/span>\n<\/code><\/pre><\/div>\n\n<ul>\n<li>Interface to Red<ul>\n<li>PKCS#8<\/li>\n<li>PKCS#11<\/li>\n<li>PGP Support<\/li>\n<\/ul>\n<\/li>\n<li>X.509 and PGP<\/li>\n<li>PKCS#11 for POLA resistance<\/li>\n<li>No PKCS#10 because it will take a year<\/li>\n<li>Backup may be just dump\/restore of the whole FPGA\/CoreState<\/li>\n<\/ul>\n<div class=\"highlight\"><pre><span><\/span><code>#!html\n<span class=\"nt\">&lt;h1<\/span><span class=\"w\"> <\/span><span class=\"na\">style=<\/span><span class=\"s\">&quot;text-align: left; color: red&quot;<\/span><span class=\"nt\">&gt;<\/span>\n<span class=\"w\">  <\/span>Red<span class=\"w\"> <\/span>\/<span class=\"w\"> <\/span>Applications\n<span class=\"nt\">&lt;\/h1&gt;<\/span>\n<\/code><\/pre><\/div>\n\n<ul>\n<li>X.509 CA<\/li>\n<li>DNSSEC<\/li>\n<li>PGP (asymmetric key sign\/verify + symmetric message encryption\/decryption)<\/li>\n<li>Tor consensus(?)<\/li>\n<\/ul>\n<h2>Issues in v0.01<\/h2>\n<ul>\n<li>License of tool chain to build<\/li>\n<li>License for borrowed components (open cores, open fpga)<\/li>\n<li>License for result<ul>\n<li>What we build ourselves - BSD<\/li>\n<li>What components we ship - life is compromise<\/li>\n<\/ul>\n<\/li>\n<li>Toolchains, Verilog, C, ...<\/li>\n<li>FPGAs and ASICs use a Verilog-based toolchain.  There are no mature open\n  Verilog compilers so the <a href=\"http:\/\/www.dwheeler.com\/trusting-trust\/\">DDC approach<\/a>\n  will not work.  Net-list optimization is also an issue.  We're looking into this,\n  but it's going to be really hard.  Research for v2.<\/li>\n<li>Protoyping platform<ul>\n<li><a href=\"http:\/\/www.bunniestudios.com\/blog\/?p=3265\">Bunnie's Novena laptop<\/a><\/li>\n<li>Altera Evaluation Board<\/li>\n<\/ul>\n<\/li>\n<li>RTC, external connectivity to et some sort of assured time<\/li>\n<li>Repository - too many git junkies.  Keep main repo on our server for the security boundary.  Can mirror on GitHub to be socially cool.<\/li>\n<li>Emacs or vi (no Rob, not TECO) :)<\/li>\n<\/ul>","category":{"@attributes":{"term":"misc"}}},{"title":"Planning for SUNET funded Cryptech Work","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/SunetInitialDevelopment","rel":"alternate"}},"published":"2016-12-15T22:43:00+00:00","updated":"2016-12-15T22:43:00+00:00","author":{"name":"Cryptech Core Team"},"id":"tag:wiki.cryptech.is,2016-12-15:\/SunetInitialDevelopment","summary":"<p>The following documents the first two development steps in Cryptech\nfunded by SUNET. The development is being done by Joachim Str\u00f6mbergson\nfrom Secworks AB.<\/p>\n<h2>Step one (Deadline 2014-02-28)<\/h2>\n<ul>\n<li>Acquire a FPGA development platform.<\/li>\n<\/ul>\n<p>DONE. We have a Terasic DE0 board and a Terasic Cyclone V GX starter kit board.<\/p>\n<ul>\n<li>\n<p>Create \u2026<\/p><\/li><\/ul>","content":"<p>The following documents the first two development steps in Cryptech\nfunded by SUNET. The development is being done by Joachim Str\u00f6mbergson\nfrom Secworks AB.<\/p>\n<h2>Step one (Deadline 2014-02-28)<\/h2>\n<ul>\n<li>Acquire a FPGA development platform.<\/li>\n<\/ul>\n<p>DONE. We have a Terasic DE0 board and a Terasic Cyclone V GX starter kit board.<\/p>\n<ul>\n<li>\n<p>Create a working development and verification flow from RTL design\n   downto FPGA.<\/p>\n<\/li>\n<li>\n<p>Verify the functionality of the SHA-256 core in a physical FPGA.<\/p>\n<\/li>\n<\/ul>\n<h3>Actions for step one<\/h3>\n<ul>\n<li>\n<p>Select FPGA development board to acquire<\/p>\n<ul>\n<li>Large enough to test sub systems and possibly a complete HSM.<\/li>\n<li>Good external interfaces for communication with host systems.<\/li>\n<li>Good external interfaces to entropy sources, memories,\n GPIO. Arduino Shields would be good.<\/li>\n<\/ul>\n<\/li>\n<li>\n<p>Create a survey on interconnect standards usable for Cryptech<\/p>\n<ul>\n<li>Availability and market share\/usage in third party cores.<\/li>\n<li>License<\/li>\n<li>Technical details - Bus, fabric, performance etc.<\/li>\n<\/ul>\n<\/li>\n<li>\n<p>Create base coretest functionality to allow testing of cores in the\n     FPGA on the development board. Read and write access to registers\n     over a known communication channel.<\/p>\n<\/li>\n<li>\n<p>Verify the development flow from Verilog RTL downto FPGA.<\/p>\n<\/li>\n<li>\n<p>Verifiera SHA-256 core using coretest.<\/p>\n<\/li>\n<li>\n<p>Start FPGA tool survey<\/p>\n<ul>\n<li>What is available as open tools and what is the status.<\/li>\n<li>What is available as open tools from the vendors.<\/li>\n<li>Talk to people in the industry to get their views on an open toolchain.<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<h2>Step two (Deadline 2014-03-31)<\/h2>\n<ul>\n<li>\n<p>Produce first draft of design proposal to the Cryptech True Random Number Generator (TRNG)<\/p>\n<ul>\n<li>Security target, security model and assumptions<\/li>\n<li>Structure, architecture<\/li>\n<li>API<\/li>\n<li>Functionality<\/li>\n<li>Online test system<\/li>\n<li>Verification model<\/li>\n<li>First two entropy sources<\/li>\n<\/ul>\n<\/li>\n<li>\n<p>Complete SHA-1 core. Including functional verification in FPGA.<\/p>\n<\/li>\n<li>\n<p>First draft of SHA-256 and SHA-1 core documentation.<\/p>\n<\/li>\n<\/ul>\n<h3>Actions for step two<\/h3>\n<ul>\n<li>\n<p>Create template for documentation<\/p>\n<\/li>\n<li>\n<p>Collect info on known TRNGs and TRNG strategies<\/p>\n<\/li>\n<li>\n<p>Collect info on online tests being used.<\/p>\n<\/li>\n<li>\n<p>Create proposal for architecture.<\/p>\n<\/li>\n<li>\n<p>Write implementation proposal.<\/p>\n<\/li>\n<li>\n<p>Specify API.<\/p>\n<\/li>\n<li>\n<p>Write security target and security model.<\/p>\n<\/li>\n<li>\n<p>Write assumptions and limitations.<\/p>\n<\/li>\n<li>\n<p>Write verification model.<\/p>\n<\/li>\n<li>\n<p>Finalize SHA-1 core RTl.<\/p>\n<\/li>\n<li>\n<p>Build SHA-1 core in FPGA.<\/p>\n<\/li>\n<li>\n<p>Verify SHA-1 functionality in FPGA using coretest.<\/p>\n<\/li>\n<li>\n<p>Write documentation for SHA-256 core.<\/p>\n<\/li>\n<li>\n<p>Write documentation for SHA-1 core.<\/p>\n<\/li>\n<\/ul>","category":{"@attributes":{"term":"misc"}}},{"title":"Developers' Guide","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/DevelopersGuide","rel":"alternate"}},"published":"2016-12-15T22:39:00+00:00","updated":"2016-12-15T22:39:00+00:00","author":{"name":"Cryptech Core Team"},"id":"tag:wiki.cryptech.is,2016-12-15:\/DevelopersGuide","content":"<p><em>Page Under Development<\/em><\/p>\n<h2>Architecture<\/h2>\n<ul>\n<li><a href=\"https:\/\/wiki.cryptech.is\/OpenCryptoChip\">OpenCryptoChip<\/a><\/li>\n<li><a href=\"https:\/\/wiki.cryptech.is\/NoisyDiode\">NoisyDiode<\/a><\/li>\n<li><a href=\"https:\/\/wiki.cryptech.is\/AlphaBoard\">AlphaBoard<\/a><\/li>\n<\/ul>\n<h2>Known Limitations<\/h2>\n<ul>\n<li>\n<p><a href=\"https:\/\/wiki.cryptech.is\/AssuredTooChain\">AssuredTooChain<\/a><\/p>\n<\/li>\n<li>\n<p>EDAToolchainSurvey<\/p>\n<\/li>\n<\/ul>\n<h2>Building the Bitstream<\/h2>","category":{"@attributes":{"term":"misc"}}},{"title":"Mailing Lists","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/MailingLists","rel":"alternate"}},"published":"2016-12-15T22:39:00+00:00","updated":"2016-12-15T22:39:00+00:00","author":{"name":"Cryptech Core Team"},"id":"tag:wiki.cryptech.is,2016-12-15:\/MailingLists","summary":"<p>The following lists are open to all:<\/p>\n<ul>\n<li>Cryptech Project Announcements<br\/>\n  announce@cryptech.is<br\/>\n  <a href=\"https:\/\/lists.cryptech.is\/listinfo\/announce\">Subscribe\/Unsubscribe<\/a><br\/>\n  <a href=\"https:\/\/lists.cryptech.is\/archives\/announce\/\">Announce List Archive<\/a><\/li>\n<li>General technology and engineering list<br\/>\n  tech@cryptech.is<br\/>\n  <a href=\"https:\/\/lists.cryptech.is\/listinfo\/tech\">Subscribe\/Unsubscribe<\/a><br\/>\n  <a href=\"https:\/\/lists.cryptech.is\/archives\/tech\/\">Tech List Archive<\/a><\/li>\n<li>Repository commit watch list (posting restricted)<br\/>\n  commit@cryptech.is<br\/>\n  <a href=\"https:\/\/lists.cryptech.is\/listinfo\/commits\">Subscribe\/Unsubscribe<\/a><br\/>\n  <a href=\"https:\/\/lists.cryptech.is\/archives\/commits\">Commit List Archive<\/a><\/li>\n<\/ul>\n<p>The following lists require approval \u2026<\/p>","content":"<p>The following lists are open to all:<\/p>\n<ul>\n<li>Cryptech Project Announcements<br\/>\n  announce@cryptech.is<br\/>\n  <a href=\"https:\/\/lists.cryptech.is\/listinfo\/announce\">Subscribe\/Unsubscribe<\/a><br\/>\n  <a href=\"https:\/\/lists.cryptech.is\/archives\/announce\/\">Announce List Archive<\/a><\/li>\n<li>General technology and engineering list<br\/>\n  tech@cryptech.is<br\/>\n  <a href=\"https:\/\/lists.cryptech.is\/listinfo\/tech\">Subscribe\/Unsubscribe<\/a><br\/>\n  <a href=\"https:\/\/lists.cryptech.is\/archives\/tech\/\">Tech List Archive<\/a><\/li>\n<li>Repository commit watch list (posting restricted)<br\/>\n  commit@cryptech.is<br\/>\n  <a href=\"https:\/\/lists.cryptech.is\/listinfo\/commits\">Subscribe\/Unsubscribe<\/a><br\/>\n  <a href=\"https:\/\/lists.cryptech.is\/archives\/commits\">Commit List Archive<\/a><\/li>\n<\/ul>\n<p>The following lists require approval for subscription:<\/p>\n<ul>\n<li>Cryptech Project Core Team<br\/>\n  core@cryptech.is<br\/>\n  <a href=\"https:\/\/lists.cryptech.is\/listinfo\/core\">Subscribe\/Unsubscribe<\/a><br\/>\n  <a href=\"https:\/\/lists.cryptech.is\/archives\/core\/\">Core List Archive<\/a><\/li>\n<li>Finance, funding, administration<br\/>\n  org@cryptec.is<br\/>\n  <a href=\"https:\/\/lists.cryptech.is\/listinfo\/org\">Subscribe\/Unsubscribe<\/a><br\/>\n  <a href=\"https:\/\/lists.cryptech.is\/archives\/org\/\">Org List Archive<\/a><\/li>\n<\/ul>","category":{"@attributes":{"term":"misc"}}},{"title":"References & Miscellaneous","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/MiscStuff","rel":"alternate"}},"published":"2016-12-15T22:39:00+00:00","updated":"2016-12-15T22:39:00+00:00","author":{"name":"Cryptech Core Team"},"id":"tag:wiki.cryptech.is,2016-12-15:\/MiscStuff","summary":"<h2>Interesting research and people<\/h2>\n<p>Advisory board, reviewers etc.<\/p>\n<h3>Elliptic Curves<\/h3>\n<ul>\n<li><a href=\"http:\/\/safecurves.cr.yp.to\/\">http:\/\/safecurves.cr.yp.to\/<\/a>. Including Curve3617.<\/li>\n<li><a href=\"http:\/\/www.nsa.gov\/ia\/_files\/nist-routines.pdf\">http:\/\/www.nsa.gov\/ia\/_files\/nist-routines.pdf<\/a>. Details for implementing NIST curves.<\/li>\n<li><a href=\"http:\/\/blog.cr.yp.to\/20140323-ecdsa.html\">http:\/\/blog.cr.yp.to\/20140323-ecdsa.html<\/a> djb on How to design an elliptic-curve signature system<\/li>\n<\/ul>\n<h3>Side channel attacks<\/h3>\n<ul>\n<li><a href=\"http:\/\/www.cl.cam.ac.uk\/~sps32\/\">http \u2026<\/a><\/li><\/ul>","content":"<h2>Interesting research and people<\/h2>\n<p>Advisory board, reviewers etc.<\/p>\n<h3>Elliptic Curves<\/h3>\n<ul>\n<li><a href=\"http:\/\/safecurves.cr.yp.to\/\">http:\/\/safecurves.cr.yp.to\/<\/a>. Including Curve3617.<\/li>\n<li><a href=\"http:\/\/www.nsa.gov\/ia\/_files\/nist-routines.pdf\">http:\/\/www.nsa.gov\/ia\/_files\/nist-routines.pdf<\/a>. Details for implementing NIST curves.<\/li>\n<li><a href=\"http:\/\/blog.cr.yp.to\/20140323-ecdsa.html\">http:\/\/blog.cr.yp.to\/20140323-ecdsa.html<\/a> djb on How to design an elliptic-curve signature system<\/li>\n<\/ul>\n<h3>Side channel attacks<\/h3>\n<ul>\n<li><a href=\"http:\/\/www.cl.cam.ac.uk\/~sps32\/\">http:\/\/www.cl.cam.ac.uk\/~sps32\/<\/a>, Dr Sergei Skorobogatov<\/li>\n<li><a href=\"https:\/\/www.bsi.bund.de\/SharedDocs\/Downloads\/DE\/BSI\/Zertifizierung\/Interpretationen\/AIS_46_ECCGuide_e_pdf.pdf\">BSI - Minimum Requirements for Evaluating Side-Channel Attack Resistance of Elliptic Curve Implementations<\/a><\/li>\n<\/ul>\n<h2>Useful References<\/h2>\n<ul>\n<li><a href=\"https:\/\/crypto.stanford.edu\/~dabo\/pubs\/abstracts\/ssl-timing.html\">Remote timing attacks are practical<\/a>, D. Boneh and D. Brumley.<\/li>\n<li><a href=\"http:\/\/www.cybersecurity.my\/mycc\/document\/mycpr\/C037\/AEP_Keyper_EAL4_ASE_1.3.pdf\">Common Critiera Security Target for the AEP Keyper<\/a><\/li>\n<li><a href=\"https:\/\/www.cosic.esat.kuleuven.be\/ches2012\/tutorials.shtml\">Cryptographic hardware: how to make it cool, fast and unbreakable<\/a>,\n  Junfeng Fan, KU Leuven<\/li>\n<li><a href=\"http:\/\/web.mit.edu\/bunnie\/www\/xi\/rec.html\">REC FPGA Seminar IAP 1998<\/a>, Bunnie Huang<\/li>\n<li><a href=\"http:\/\/compcert.inria.fr\/\">the formal verification of realistic compilers usable for critical embedded software<\/a><\/li>\n<\/ul>\n<h2>Somewhat Related Web Sites<\/h2>\n<ul>\n<li><a href=\"https:\/\/prism-break.org\/\">List of Open SW Alternatives<\/a><\/li>\n<\/ul>","category":{"@attributes":{"term":"misc"}}},{"title":"HSM Requirements","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/Requirements","rel":"alternate"}},"published":"2016-12-15T22:39:00+00:00","updated":"2016-12-15T22:39:00+00:00","author":{"name":"Cryptech Core Team"},"id":"tag:wiki.cryptech.is,2016-12-15:\/Requirements","summary":"<p>Requirements for the Cryptech Alpha System. Derived from Use Cases (see below). There are also utility, internal requirements (again, see below).<\/p>\n<h2>Capacity<\/h2>\n<h3>Per key storage requirements<\/h3>\n<p>In addition to the actual key data, each key requires<\/p>\n<ul>\n<li>Key type \u2013 4 bytes<\/li>\n<li>Key identifier \u2013 4 bytes<\/li>\n<li>Key flags, e.g. exportable \u2013 8 \u2026<\/li><\/ul>","content":"<p>Requirements for the Cryptech Alpha System. Derived from Use Cases (see below). There are also utility, internal requirements (again, see below).<\/p>\n<h2>Capacity<\/h2>\n<h3>Per key storage requirements<\/h3>\n<p>In addition to the actual key data, each key requires<\/p>\n<ul>\n<li>Key type \u2013 4 bytes<\/li>\n<li>Key identifier \u2013 4 bytes<\/li>\n<li>Key flags, e.g. exportable \u2013 8 bytes<\/li>\n<\/ul>\n<p>This results a total 16 bytes overhead for each key.<\/p>\n<h3>Examples per algorithm<\/h3>\n<p>(For RSA, we  might also want to include the primes p and q might also be included which requires additional storage.)<\/p>\n<ul>\n<li>RSA-8192 requires 1024 bytes secret key, 1024 bytes public key + 4 bytes exponent + 16 bytes overhead = 2068 bytes<\/li>\n<li>RSA-4096 requires 512 bytes secret key,   512 bytes public key + 4 bytes exponent + 16 bytes overhead = 1044 bytes<\/li>\n<li>RSA-2048 requires 256 bytes secret key,   256 bytes public key + 4 bytes exponent + 16 bytes overhead = 532 bytes<\/li>\n<li>EC P-256 requires 32 bytes secret key, 64 bytes public key + 16 bytes overhead = 112 bytes<\/li>\n<li>EC P-384 requires 48 bytes secret key, 96 bytes public key + 16 bytes overhead = 160 bytes<\/li>\n<li>Curve 25519 requires 32 bytes secret key, 32 bytes public key + 16 bytes overhead = 80 bytes<\/li>\n<\/ul>\n<h2>Use Cases<\/h2>\n<h3>DNSSEC<\/h3>\n<h4>Number of keys<\/h4>\n<ul>\n<li>TLD (or provider using key sharing) requires ~ 100 key pairs<\/li>\n<li>3 KSK per zone (previous, current, new)<\/li>\n<li>3 ZSK per zone (previous, current, new)<\/li>\n<\/ul>\n<h4>Possibly dual algorithms<\/h4>\n<ul>\n<li>A typical TLD operator usually has less than 10 TLDs<\/li>\n<li>Other DNS providers may use key sharing to limit number of keys required<\/li>\n<\/ul>\n<h4>Algorithms<\/h4>\n<ul>\n<li>RSA-1024\/SHA-256<\/li>\n<li>RSA-2048\/SHA-256<\/li>\n<li>EC-P256\/SHA-256<\/li>\n<\/ul>\n<h4>Performance<\/h4>\n<p>Each update to a zone requires 3-4 signatures (per algorithm)<\/p>\n<ul>\n<li>Resign SOA (signed by ZSK)<\/li>\n<li>Resign updated RR (signed by ZSK)<\/li>\n<li>Resign NSEC\/NSEC3 (signed by ZSK), may require multiple signatures<\/li>\n<\/ul>\n<p>Non-interactive latency (batch), dynamic updates may require faster signing<\/p>\n<h3>SAML<\/h3>\n<h4>Number of keys<\/h4>\n<p>SAML federation operator requires max 10 key pairs (including space for roll)<\/p>\n<h4>Algorithms<\/h4>\n<ul>\n<li>RSA-2048\/SHA-256<\/li>\n<\/ul>\n<h4>Performance<\/h4>\n<ul>\n<li>Non-interactive latency (batch)<ul>\n<li>non-MDX: \u2026<\/li>\n<\/ul>\n<\/li>\n<li>Interactive latency<ul>\n<li>MDX: \u2026<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<h3>PKIX (including RPKI)<\/h3>\n<h4>Number of keys<\/h4>\n<ul>\n<li>Typical Certification Authority ~ 10 key pairs<ul>\n<li>CA key, OCSP, CRL per level in the CA<\/li>\n<li>Root CA is one level<\/li>\n<li>For subordinate CAs, perhaps 2-5 CAs in a HSM is reasonable?<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<h4>Algorithms<\/h4>\n<ul>\n<li>RSA-2048\/SHA-256<\/li>\n<li>RSA-4096\/SHA-256<\/li>\n<li>RSA-4096\/SHA-512 ?<\/li>\n<li>EC-P256\/SHA-256<\/li>\n<\/ul>\n<h4>Performance<\/h4>\n<ul>\n<li>Non-interactive latency<ul>\n<li>Root CA: Less than 1 signature per day<\/li>\n<li>Issuing CA: One signature per issued certificate<\/li>\n<li>CRL: Less than 1 signature per hour<\/li>\n<\/ul>\n<\/li>\n<li>Interactive latency<ul>\n<li>OCSP: Multiple signatures per second<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<h3>Tor<\/h3>\n<p>Requirements according to (section 1): https:\/\/gitweb.torproject.org\/torspec.git\/plain\/dir-spec.txt<\/p>\n<h4>Number of keys<\/h4>\n<ul>\n<li>1 private key<\/li>\n<li>10 public keys<\/li>\n<\/ul>\n<h4>Algorithms<\/h4>\n<ul>\n<li>RSA-2048\/SHA-1 ?<\/li>\n<li>RSA-2048\/SHA-256<\/li>\n<li>RSA-4096\/SHA-256 ?<\/li>\n<li>RSA-4096\/SHA-512 ?<\/li>\n<\/ul>\n<h4>Performance<\/h4>\n<ul>\n<li>2 signatures per hour<\/li>\n<li>20 verification operations per hour<\/li>\n<li>1 second max latency for RSA-2048 based verification<\/li>\n<\/ul>\n<h3>Certificate Transparency (CT)<\/h3>\n<h4>Number of keys<\/h4>\n<p>CT requires 1 key (ECDSA or RSA) per log<\/p>\n<h4>Algorithms<\/h4>\n<ul>\n<li>RSA-2048\/SHA-256<\/li>\n<li>RSA-4096\/SHA-256 ?<\/li>\n<li>RSA-4096\/SHA-512 ?<\/li>\n<li>EC-P256\/SHA-256<\/li>\n<\/ul>\n<h4>Performance<\/h4>\n<ul>\n<li>A Certificate Transparency log uses one ECDSA or one RSA key to sign two separate documents:<\/li>\n<li>STH's might need to be signed once per hour<\/li>\n<li>SCT's might need to be signed once per second (*)<\/li>\n<\/ul>\n<p>See RFC 6962, section 2.1.4 \u2013 https:\/\/tools.ietf.org\/html\/rfc6962<\/p>\n<h2>Internal Functional Requirements<\/h2>\n<h3>Algorithms and functions<\/h3>\n<ul>\n<li>Key wrapping using AES-256 with SIV, http:\/\/tools.ietf.org\/html\/rfc5297<\/li>\n<li>Internal Storage Master Key (ISMK) in battery backed RAM connected to FPGA<ul>\n<li>Battery connection controlled by tamper mechanism<\/li>\n<li>Active erasure controlled by tamper mechanism<\/li>\n<\/ul>\n<\/li>\n<li>32-bit high quality random number generation<\/li>\n<\/ul>\n<h3>PKCS11<\/h3>\n<p>The following PKCS11 mechanisms are required to fulfill the aforementioned use cases:<\/p>\n<ul>\n<li>RSA<ul>\n<li>CKM_RSA_PKCS_KEY_PAIR_GEN<\/li>\n<li>CKM_RSA_PKCS<\/li>\n<li>CKM_RSA_X_509 ?<\/li>\n<li>CKM_SHA256_RSA_PKCS<\/li>\n<li>CKM_SHA512_RSA_PKCS ?<\/li>\n<\/ul>\n<\/li>\n<li>ECDSA<ul>\n<li>CKM_EC_KEY_PAIR_GEN<\/li>\n<li>CKM_ECDSA<\/li>\n<\/ul>\n<\/li>\n<li>AES<ul>\n<li>\u2026 TBD \u2026<\/li>\n<\/ul>\n<\/li>\n<li>Random<ul>\n<li>\u2026 TBD \u2026<\/li>\n<\/ul>\n<\/li>\n<li>Key Wrapping<ul>\n<li>\u2026 TBD \u2026<\/li>\n<\/ul>\n<\/li>\n<li>Hash<ul>\n<li>CKM_SHA256<\/li>\n<li>CKM_SHA512 (?)<\/li>\n<\/ul>\n<\/li>\n<\/ul>","category":{"@attributes":{"term":"misc"}}},{"title":"Welcome to the Cryptech Project","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/","rel":"alternate"}},"published":"2016-12-15T20:46:00+00:00","updated":"2017-05-13T20:30:00+00:00","author":{"name":"Cryptech Core Team"},"id":"tag:wiki.cryptech.is,2016-12-15:\/","summary":"<h1>Overview<\/h1>\n<p>Recent revelations have called into question the integrity of some of\nthe implementations of basic cryptographic functions and devices used to\nsecure communications on the Internet. There are serious questions about\nalgorithms and about implementations of those algorithms in software and\nparticularly hardware. The goal of the <a href=\"https:\/\/cryptech.is\">CrypTech<\/a>\nproject \u2026<\/p>","content":"<h1>Overview<\/h1>\n<p>Recent revelations have called into question the integrity of some of\nthe implementations of basic cryptographic functions and devices used to\nsecure communications on the Internet. There are serious questions about\nalgorithms and about implementations of those algorithms in software and\nparticularly hardware. The goal of the <a href=\"https:\/\/cryptech.is\">CrypTech<\/a>\nproject is to provide some possible answers to those questions by\ndeveloping an open-source hardware cryptographic engine that meets the\nneeds of high assurance Internet infrastructure systems that use\ncryptography.<\/p>\n<p>The algorithmic issues are in the domain of the heavy math cryptography\nfolk; the implementation issues are the primary focus of the project.\nThe open-source hardware cryptographic engine must be of general use to\nthe broad Internet community, covering needs such as secure email, web,\nDNS, PKIs, etc.<\/p>\n<p>The intent of the project is that the final open-source hardware cryptographic\nengine can be built by anyone from public hardware specifications and\nopen-source firmware. Anyone can then operate it without fees of any\nkind.<\/p>\n<h1>About Us<\/h1>\n<p><a href=\"https:\/\/cryptech.is\">CrypTech.IS<\/a> is a loose international collective\nof <a href=\"https:\/\/wiki.cryptech.is\/WhoWeAre\">engineers<\/a> trying to improve assurance and privacy on the\nInternet. It is funded diversely and is administratively quartered outside\nthe US.<\/p>\n<p>We are actively seeking use cases for an initial project which is to\nproduce a design of an open and auditable Hardware Security Module (HSM)\nand supporting software.<\/p>\n<p>We are also considering the issues around assurance of a tool-chain,\nfrom compiler to operating system and as close to the hardware as we can\nreasonably get.<\/p>\n<p>The project solicits functional requirements from a wide range of\norganizations. It will focus on the classic low level cryptographic\nfunctions and primitives, and not get drawn into re-implementation of\napplication protocol layers.<\/p>\n<p>We hope that a group of interested organizations will offer funding\nfor development, and that the IACR and public sector cryptographers will\nprovide algorithmic advice and wide and open review. If you or your\norganization is interested in helping this effort, please consider\noffering <a href=\"https:\/\/cryptech.is\/funding\/\">financial support<\/a> to keep the\nwork flowing.<\/p>\n<h1>More Information<\/h1>\n<h2><a href=\"https:\/\/wiki.cryptech.is\/QuickStart\">Quick Start Guide<\/a><\/h2>\n<ul>\n<li>including pointers to the git repositories, information on how to set up and configure the board and software, and HSM requirements<\/li>\n<\/ul>\n<h2><a href=\"https:\/\/wiki.cryptech.is\/DevelopersGuide\">Developers Guide<\/a><\/h2>\n<ul>\n<li>including the architecture diagrams, and known information<\/li>\n<\/ul>\n<h2><a href=\"https:\/\/wiki.cryptech.is\/ProjectStatus\">Project Status<\/a><\/h2>\n<ul>\n<li>including information on the chip design and prototypes as well as the pilot project(s)<\/li>\n<\/ul>\n<h2><a href=\"https:\/\/wiki.cryptech.is\/ProjectMetadata\">Project Metadata<\/a><\/h2>\n<ul>\n<li>including information on presentations and meeting notes, technical references, and related work<\/li>\n<\/ul>\n<h2><a href=\"https:\/\/wiki.cryptech.is\/ProjectArchive\">Project Archive<\/a><\/h2>\n<ul>\n<li>including information on dormant and far-future work<\/li>\n<\/ul>","category":{"@attributes":{"term":"misc"}}},{"title":"A Completely Informal Snapshot Of The Current State Of The Cryptech Project As Of 2014-11-06","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/StateOfPlay","rel":"alternate"}},"published":"2014-11-06T00:00:00+00:00","updated":"2014-11-06T00:00:00+00:00","author":{"name":"Cryptech Core Team"},"id":"tag:wiki.cryptech.is,2014-11-06:\/StateOfPlay","summary":"<p>This page contains a snapshot of the status in the project and will almost certainly be obsolete by the time you read it.  If you find something that's wrong, please fix it!<\/p>\n<h2>Cores<\/h2>\n<p>We have a bunch of cores, primarily for FPGA implementation.  Some of them implement cryptographic\nalgorithms or \u2026<\/p>","content":"<p>This page contains a snapshot of the status in the project and will almost certainly be obsolete by the time you read it.  If you find something that's wrong, please fix it!<\/p>\n<h2>Cores<\/h2>\n<p>We have a bunch of cores, primarily for FPGA implementation.  Some of them implement cryptographic\nalgorithms or critical functionality like the TRNG. Other cores are support cores for implementation of the Cryptech HSM. Other cores are for developing the cores and the HW. Finally some are just test\ncode.<\/p>\n<p>Cores that have been promoted to official cryptech HW cores:<\/p>\n<ul>\n<li><code>core\/chacha<\/code> - The ChaCha stream cipher<\/li>\n<li><code>core\/sha1<\/code> - FIPS 180-2 SHA-1 hash<\/li>\n<li><code>core\/sha256<\/code> - FIPS 180-4 SHA-256 hash<\/li>\n<li><code>core\/sha512<\/code> - FIPS 180-4 SHA-512\/x hash<\/li>\n<li><code>core\/trng<\/code> - The Cryptech TRNG sub system. Uses ChaCha, SHA-512 and entropy cores.<\/li>\n<li><code>core\/avalanche_entropy<\/code> - Avalanche entropy provider core. Requires external avalanche noise source.<\/li>\n<li><code>core\/rosc_entropy<\/code> - Digital ring oscillator based entropy provider core.<\/li>\n<\/ul>\n<p>Utility, test, board support:<\/p>\n<ul>\n<li><code>core\/coretest<\/code> - Core for performing command\/response operations to drive testing of a core.<\/li>\n<li><code>core\/coretest_hashes<\/code> - Subsysem with coretest and the hash function cores as test objects.<\/li>\n<li><code>core\/coretest_test_core<\/code> - Coretest with a simple test core<\/li>\n<li><code>core\/i2c<\/code> - I2C interface core.<\/li>\n<li><code>core\/novena<\/code><\/li>\n<li><code>core\/novena_eim<\/code><\/li>\n<li><code>core\/novena_i2c_simple<\/code><\/li>\n<li><code>core\/test_core<\/code><\/li>\n<li><code>core\/uart<\/code>- UART interface core to allow serial communication with FPGA functionality.<\/li>\n<li><code>core\/vndecorrelator<\/code> - von Neumann decorrelation core.<\/li>\n<\/ul>\n<p>Documentation is very haphazard: some of the repositories have\ndetailed README.md files, but in many cases the documentation, what\nthere is of it, is probably meaningful only to the person who wrote\nit, not because of any lack of good intent, just because what's\nwritten assumes that the reader knows everything that the author does\nabout the other cores, the rest of the environment, and how everything\nfits together.<\/p>\n<h2>Builds<\/h2>\n<p>At this point I have figured out how to build two different FPGA\nimages for the Novena PVT1.  In both cases, I'm using the Makefile\nrather than attempting to use the XiLinx GUI environment.<\/p>\n<ul>\n<li>\n<p><code>core\/novena<\/code> builds the current set of digest cores into a\n  framework that uses the \"coretest\" byte stream protocol over an I2C\n  bus.<\/p>\n<\/li>\n<li>\n<p><code>core\/novena_i2c_simple<\/code> builds the current set of digest cores into\n  a framework that uses a simplfied write()\/read() API over an I2C bus.<\/p>\n<\/li>\n<\/ul>\n<p>There's a third build, <code>core\/novena_eim<\/code>, which was only just updated\ntoday, and which is reported as not quite stable yet.  Will try\nbuilding it soon and report here.<\/p>\n<p>Both working builds (and, almost certainly, any useful build) involve\nmore than just the named repository.  <code>verilator<\/code>, when asked nicely,\nwill draw a graph of Verilog module relationships.  Take this with\nsalt, as I am a long way from getting <code>verilator<\/code> to run cleanly on\nany of this, but the current graphs may still be useful in visualizing\nwhat's happening here.<\/p>\n<p>At least some of the modules that <code>verilator<\/code> complains about not\nbeing able to find appear to come from XiLinx libraries that\n<code>verilator<\/code> doesn't know about.\nSee <a href=\"http:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx12_1\/spartan6_hdl.pdf\">Spartan-6 Libraries Guide for HDL Designs<\/a> for details.<\/p>\n<h3>Module relationships in core\/novena build<\/h3>\n<p><img alt=\"novena__linkcells.svg\" src=\"https:\/\/wiki.cryptech.is\/StateOfPlay\/StateOfPlay\/novena__linkcells.svg\"><\/p>\n<h3>Module relationships in core\/novena_i2c_simple build<\/h3>\n<p><img alt=\"novena_i2c_simple__linkcells.svg\" src=\"https:\/\/wiki.cryptech.is\/StateOfPlay\/StateOfPlay\/novena_i2c_simple__linkcells.svg\"><\/p>\n<h3>Module relationships in core\/novena_eim build<\/h3>\n<p><img alt=\"novena_eim__linkcells.svg\" src=\"https:\/\/wiki.cryptech.is\/StateOfPlay\/StateOfPlay\/novena_eim__linkcells.svg\"><\/p>\n<h3>Module relationships in cores\/trng build<\/h3>\n<p>By special request, here's a graph for the TRNG too, even though we\ndon't yet have a way to speak to it from the Novena:<\/p>\n<p><img alt=\"trng__linkcells.svg\" src=\"https:\/\/wiki.cryptech.is\/StateOfPlay\/StateOfPlay\/trng__linkcells.svg\"><\/p>\n<h2>C Code<\/h2>\n<p>Most of the cores have at least minimal test frameworks, written in a\ncombination of Verilog, C, and Python, but there's also a preliminary\nport of Cryptlib to the Cryptech environment, in <code>sw\/cryptlib<\/code>.  As of\nthis writing, the only Cryptech-specific features of this port, other\nthan a few makefile tricks, are:<\/p>\n<ul>\n<li>\n<p>A set of HALs that make use of the <code>core\/novena<\/code> and\n  <code>core\/novena_i2c_simple<\/code> FPGA builds, using the Linux \/dev\/i2c\n  device interface; and<\/p>\n<\/li>\n<li>\n<p>Another Python script to test the resulting Cryptlib build, using\n  the stock Cryptlib Python bindings.<\/p>\n<\/li>\n<\/ul>\n<p>No HAL for <code>core\/novena_eim<\/code> yet.<\/p>\n<p>The Cryptlib Python bindings build kind of slowly on the Novena, sorry\nabout that.<\/p>\n<h2>Hardware<\/h2>\n<p>The hardware guys have done cool stuff with hardware entropy sources.\nI even have one of the noise boards, but until I have some way to\nconnect C code to the TRNG, I don't have much use for it other than to\nadmire the craftsmanship.  Soon, I hope.<\/p>\n<h2>Tools<\/h2>\n<p>Already mentioned <code>verilator<\/code>.  In addition to generating GraphViz\ninput, <code>verilator<\/code> has a <code>--lint<\/code> mode which looks interesting.<\/p>\n<p>(JS) Verilator is fairly usable, at least as a linter. Adding <code>-Wall<\/code> provides more warnings.\nSince we at least uses Icarus Verilog (iverilog), Altera Quartus and Xilinx ISE one would assume that they would provide all possible warnings. That is not the case. They all seem to fins different things to warn about. And Verilator provides even more. The more parsers and checkers the better. But we will not be able to, or want to fix all warnings. Some things are by design. We should probably document what we ignore.<\/p>\n<p>I haven't yet figured out whether we have any real use for\n<code>verilator<\/code>'s core function of synthesizing Verilog into C++.  I've\nbeen toying with the idea of a software-only development environment,\nwhere one simulates an embedded machine using two Unix processes: one\nwould be a virtual FPGA generated by <code>verilator<\/code>, the other would be a\nclassical deeply embedded system running as a single process.  The two\nprocesses would communicate via a <code>PF_UNIX<\/code> socket or something on\nthat order.  It might be possible to jam everything into a single\nprocess, but I suspect it wouldn't be worth the trouble.<\/p>\n<p>Joachim has Makefiles which use <code>iverilog<\/code> to generate simulation\nimages.  Installing <code>iverilog<\/code> is easy enough (<code>apt-get install<\/code>, etc)\nbut I haven't yet figured out how to do anything interesting with the\nsimulation images.  Joachim replies:<\/p>\n<div class=\"highlight\"><pre><span><\/span><code><span class=\"nv\">There<\/span><span class=\"w\"> <\/span><span class=\"nv\">is<\/span><span class=\"w\"> <\/span><span class=\"nv\">help<\/span><span class=\"w\"> <\/span><span class=\"nv\">in<\/span><span class=\"w\"> <\/span><span class=\"nv\">the<\/span><span class=\"w\"> <\/span><span class=\"nv\">Makefile<\/span>.<span class=\"w\">  <\/span><span class=\"nv\">You<\/span><span class=\"w\"> <\/span><span class=\"nv\">run<\/span><span class=\"w\"> <\/span><span class=\"nv\">the<\/span><span class=\"w\"> <\/span><span class=\"nv\">targets<\/span>,<span class=\"w\"> <\/span><span class=\"nv\">either<\/span><span class=\"w\"> <\/span><span class=\"nv\">as<\/span>\n<span class=\"nv\">make<\/span><span class=\"w\"> <\/span><span class=\"nv\">sim<\/span><span class=\"o\">-<\/span><span class=\"nv\">foo<\/span><span class=\"w\"> <\/span><span class=\"nv\">or<\/span><span class=\"w\"> <\/span><span class=\"nv\">just<\/span><span class=\"w\"> <\/span>.<span class=\"o\">\/<\/span><span class=\"nv\">foo<\/span>.<span class=\"nv\">sim<\/span>.<span class=\"w\">  <\/span><span class=\"nv\">Most<\/span><span class=\"w\"> <\/span><span class=\"k\">if<\/span><span class=\"w\"> <\/span><span class=\"nv\">not<\/span><span class=\"w\"> <\/span><span class=\"nv\">all<\/span><span class=\"w\"> <\/span><span class=\"nv\">tests<\/span><span class=\"w\"> <\/span><span class=\"nv\">are<\/span><span class=\"w\"> <\/span><span class=\"nv\">self<\/span>\n<span class=\"nv\">testing<\/span><span class=\"w\"> <\/span><span class=\"nv\">with<\/span><span class=\"w\"> <\/span><span class=\"nv\">test<\/span><span class=\"w\"> <\/span><span class=\"nv\">cases<\/span><span class=\"w\"> <\/span><span class=\"nv\">and<\/span><span class=\"w\"> <\/span><span class=\"nv\">should<\/span><span class=\"w\"> <\/span><span class=\"nv\">report<\/span><span class=\"w\"> <\/span><span class=\"nv\">number<\/span><span class=\"w\"> <\/span><span class=\"nv\">of<\/span><span class=\"w\"> <\/span><span class=\"nv\">test<\/span><span class=\"w\"> <\/span><span class=\"nv\">cases<\/span><span class=\"w\"> <\/span><span class=\"nv\">and<\/span>\n<span class=\"nv\">how<\/span><span class=\"w\"> <\/span><span class=\"nv\">many<\/span><span class=\"w\"> <\/span><span class=\"nv\">passed<\/span>.<span class=\"w\">  <\/span><span class=\"nv\">Which<\/span><span class=\"w\"> <\/span><span class=\"nv\">should<\/span><span class=\"w\"> <\/span><span class=\"nv\">be<\/span><span class=\"w\"> <\/span><span class=\"nv\">all<\/span>.\n<\/code><\/pre><\/div>\n\n<p>As far as I know we've done nothing yet to deal with threats to the\ntool chain (Thompson attack, etc).<\/p>","category":{"@attributes":{"term":"misc"}}}]}