{"title":"Cryptech Project - AlphaBoard","link":[{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/","rel":"alternate"}},{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/feeds\/alphaboard.atom.xml","rel":"self"}}],"id":"https:\/\/wiki.cryptech.is\/","updated":"2019-01-24T14:37:00+00:00","entry":[{"title":"Using ST-Link on the Alpha Board","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/UsingSTLink","rel":"alternate"}},"published":"2017-05-13T03:37:00+00:00","updated":"2019-01-24T14:37:00+00:00","author":{"name":"Joachim Str\u00f6mbergson"},"id":"tag:wiki.cryptech.is,2017-05-13:\/UsingSTLink","summary":"<p>ST-LINK is STM's implementation of the <a href=\"https:\/\/developer.arm.com\/products\/architecture\/cpu-architecture\/debug-visibility-and-trace\/coresight-architecture\/serial-wire-debug\">| Serial Wire Debug (SWD)<\/a> protocol.\nThink of it as JTAG if you're more comfortable with that.<\/p>\n<h2>Getting an ST-LINK programmer<\/h2>\n<p>ST-LINK is built into all(?) of STM's Nucleo and Discovery evaluation\nboards, which can be had for as little as US$10 from <a href=\"http:\/\/mouser.com\">Mouser \u2026<\/a><\/p>","content":"<p>ST-LINK is STM's implementation of the <a href=\"https:\/\/developer.arm.com\/products\/architecture\/cpu-architecture\/debug-visibility-and-trace\/coresight-architecture\/serial-wire-debug\">| Serial Wire Debug (SWD)<\/a> protocol.\nThink of it as JTAG if you're more comfortable with that.<\/p>\n<h2>Getting an ST-LINK programmer<\/h2>\n<p>ST-LINK is built into all(?) of STM's Nucleo and Discovery evaluation\nboards, which can be had for as little as US$10 from <a href=\"http:\/\/mouser.com\">Mouser<\/a>\nor <a href=\"http:\/\/element14.com\">element14<\/a> (<a href=\"http:\/\/newark.com\">Newark<\/a> in\nthe Americas, <a href=\"http:\/\/farnell.com\">Farnell<\/a> in Europe).<\/p>\n<p>We have tested with STM32F0DISCOVERY and STM32F4DISCOVERY (both with ST-LINK\nv2.0) and NUCLEO-F411RE (with ST-LINK v2.1).<\/p>\n<h3>Connecting the ST-LINK programmer to the Alpha<\/h3>\n<p>On the STM board, remove the pair of ST-LINK jumpers (CN4 on the F4DISCO,\nCN2 on the F0DISCO and NUCLEO). Then locate the 6-pin SWD header (CN3 on\nthe F0DISCO, CN2 on the F4DISCO, CN4 on the NUCLEO), and connect it to J1\non the Alpha board (top, just left of center).<\/p>\n<p>This photo shows the correct orientation of the cables (both boards\noriented so that the logo is right-side up):<\/p>\n<p><img alt=\"IMG_20170512_205557_s.jpg\" src=\"https:\/\/wiki.cryptech.is\/UsingSTLink\/UsingSTLink\/IMG_20170512_205557_s.jpg\"><\/p>\n<p>NOTE: The STM boards have an unfortunate tendency to short unexpectedly, so\nI recommend putting them in an enclosure. In this case, I've cut holes in\nthe original packaging.<\/p>\n<h2>Install OpenOCD and the debugger<\/h2>\n<div class=\"highlight\"><pre><span><\/span><code>$<span class=\"w\"> <\/span>apt-get<span class=\"w\"> <\/span>install<span class=\"w\"> <\/span>gdb-arm-none-eabi<span class=\"w\"> <\/span>openocd\n<\/code><\/pre><\/div>\n\n<h2>Get the <code>debug<\/code> and <code>flash-target<\/code> scripts<\/h2>\n<p>If you don't already have a cryptech source tree somewhere, get the source distribution, e.g.<\/p>\n<div class=\"highlight\"><pre><span><\/span><code>$<span class=\"w\"> <\/span>apt-get<span class=\"w\"> <\/span><span class=\"nb\">source<\/span><span class=\"w\"> <\/span>cryptech-alpha\n<\/code><\/pre><\/div>\n\n<p>The scripts are in <code>sw\/stm32\/bin<\/code>.<\/p>\n<h2>Re-flashing the Alpha<\/h2>\n<h3>To reflash with our binary firmware<\/h3>\n<div class=\"highlight\"><pre><span><\/span><code>$<span class=\"w\"> <\/span>tar<span class=\"w\"> <\/span>xfz<span class=\"w\"> <\/span>\/usr\/share\/cryptech-alpha-firmware.tar.gz\n$<span class=\"w\"> <\/span>flash-target<span class=\"w\"> <\/span>hsm\n<\/code><\/pre><\/div>\n\n<p>What you should see is something like:<\/p>\n<div class=\"highlight\"><pre><span><\/span><code>** Programming Started **\nauto erase enabled\nInfo : device id = 0x20016419\nInfo : flash size = 2048kbytes\nInfo : Dual Bank 2048 kiB STM32F42x\/43x\/469\/479 found\ntarget halted due to breakpoint, current mode: Thread\nxPSR: 0x61000000 pc: 0x20000046 msp: 0x2002fffc\nwrote 524288 bytes from file projects\/hsm\/hsm.elf in 12.344705s (41.475 KiB\/s)\n** Programming Finished **\n** Verify Started **\ntarget halted due to breakpoint, current mode: Thread\nxPSR: 0x61000000 pc: 0x2000002e msp: 0x2002fffc\ntarget halted due to breakpoint, current mode: Thread\nxPSR: 0x61000000 pc: 0x2000002e msp: 0x2002fffc\nverified 509100 bytes in 0.953672s (521.320 KiB\/s)\n** Verified OK **\n** Resetting Target **\nInfo : Unable to match requested speed 2000 kHz, using 1800 kHz\nInfo : Unable to match requested speed 2000 kHz, using 1800 kHz\nadapter speed: 1800 kHz\nshutdown command invoked\n<\/code><\/pre><\/div>\n\n<h3>To reflash with firmware you built from source<\/h3>\n<p>See BuildingFromSource.<\/p>\n<h2>Debugging the Alpha<\/h2>\n<p>This site shows several ways to use various debuggers to debug the\nfirmware in an STM32:<\/p>\n<div class=\"highlight\"><pre><span><\/span><code>http:\/\/fun-tech.se\/stm32\/OpenOCD\/gdb.php\n<\/code><\/pre><\/div>\n\n<p>There is a shell script called 'bin\/debug' that starts an OpenOCD server\nand GDB:<\/p>\n<div class=\"highlight\"><pre><span><\/span><code>$<span class=\"w\"> <\/span>sw\/stm32\/bin\/debug<span class=\"w\"> <\/span>projects\/hsm\/hsm\n<\/code><\/pre><\/div>","category":{"@attributes":{"term":"AlphaBoard"}}},{"title":"Disaster Recovery on the Alpha Board","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/DisasterRecovery","rel":"alternate"}},"published":"2017-05-13T00:30:00+00:00","updated":"2017-05-13T00:30:00+00:00","author":{"name":"Paul Selkirk"},"id":"tag:wiki.cryptech.is,2017-05-13:\/DisasterRecovery","summary":"<p>This page covers a few likely (hopefully unlikely) oh-noes.<\/p>\n<h2>Oh no, I bricked my device<\/h2>\n<h3>Recovering from a bad firmware install<\/h3>\n<p>You can upload new firmware through the bootloader. On power-up or reset,\nthe bootloader flashes the blue LED for 10 seconds. During that time, start\n<code>cryptech_upload<\/code>:<\/p>\n<div class=\"highlight\"><pre><span><\/span><code><span class=\"o\">$<\/span><span class=\"w\"> <\/span><span class=\"n\">cryptech_upload<\/span><span class=\"w\"> <\/span><span class=\"o\">--<\/span><span class=\"n\">firmware<\/span><span class=\"w\"> <\/span><span class=\"o\">--<\/span><span class=\"n\">user \u2026<\/span><\/code><\/pre><\/div>","content":"<p>This page covers a few likely (hopefully unlikely) oh-noes.<\/p>\n<h2>Oh no, I bricked my device<\/h2>\n<h3>Recovering from a bad firmware install<\/h3>\n<p>You can upload new firmware through the bootloader. On power-up or reset,\nthe bootloader flashes the blue LED for 10 seconds. During that time, start\n<code>cryptech_upload<\/code>:<\/p>\n<div class=\"highlight\"><pre><span><\/span><code><span class=\"o\">$<\/span><span class=\"w\"> <\/span><span class=\"n\">cryptech_upload<\/span><span class=\"w\"> <\/span><span class=\"o\">--<\/span><span class=\"n\">firmware<\/span><span class=\"w\"> <\/span><span class=\"o\">--<\/span><span class=\"n\">user<\/span><span class=\"w\"> <\/span><span class=\"n\">wheel<\/span>\n<span class=\"n\">PIN<\/span><span class=\"p\">:<\/span><span class=\"w\"> <\/span><span class=\"o\">&lt;<\/span><span class=\"n\">your<\/span><span class=\"o\">-<\/span><span class=\"n\">wheel<\/span><span class=\"o\">-<\/span><span class=\"n\">pin<\/span><span class=\"o\">&gt;<\/span>\n<\/code><\/pre><\/div>\n\n<h3>Recovering from a bad bootloader install<\/h3>\n<p>Well, now you've done it. You'll need to buy an ST-LINK programmer.\nSee <a href=\"https:\/\/wiki.cryptech.is\/UsingSTLink\">UsingSTLink<\/a>.<\/p>\n<h2>Oh no, I'm locked out of my device<\/h2>\n<p>If you're staring at this thing for the first time, or if you ran\n<code>keystore erase<\/code>, then you have no PIN. Believe it or not, this is the\nbest case scenario. Log in as wheel with the default PIN\n<code>YouReallyNeedToChangeThisPINRightNowWeAreNotKidding<\/code>, and you should be\nable to reset the PINs.<\/p>\n<p>If you forgot the PIN, I feel sorry for you. The only way out of this is\nvia <a href=\"https:\/\/wiki.cryptech.is\/UsingSTLink\">ST-LINK<\/a>. The easiest way is to debug with <code>gdb<\/code>, set a breakpoint on\n<code>hal_rpc_login<\/code>, and issue the gdb command <code>return 0<\/code>.<\/p>\n<h2>Oh no, I forgot (or reset) the master key<\/h2>\n<p>As shipped, the Alpha doesn't include a battery backup for the Master Key\nMemory. So if power is interrupted, the MKM is wiped. (Also, if we had\ntamper protection more sophisticated than a Panic Button, it would wipe\nthe MKM when you opened the case to install the ST-LINK cable.)<\/p>\n<p>Sorry, there's nothing that can be done about that. All your keys are\nstill in flash memory, but encrypted with the KEK, which is now gone.\n(Unless you used the <code>masterkey unsecure set<\/code> command to store the KEK in\nunprotected flash memory, but you wouldn't do that, would you?)<\/p>","category":{"@attributes":{"term":"AlphaBoard"}}},{"title":"Alpha Sealed Bags","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/AlphaSealedBags","rel":"alternate"}},"published":"2016-12-16T14:09:00+00:00","updated":"2016-12-16T14:12:00+00:00","author":{"name":"Fredrik Thulin"},"id":"tag:wiki.cryptech.is,2016-12-16:\/AlphaSealedBags","summary":"<h2>Chain of custody<\/h2>\n<p>At present, we can't make any statements at all about the integrity of the hardware before it reached us - assembled and ready.<\/p>\n<p>We test and program the Alphas using a dedicated computer, but not in a secure facility by any means.\nA concerned user is advised to \u2026<\/p>","content":"<h2>Chain of custody<\/h2>\n<p>At present, we can't make any statements at all about the integrity of the hardware before it reached us - assembled and ready.<\/p>\n<p>We test and program the Alphas using a dedicated computer, but not in a secure facility by any means.\nA concerned user is advised to reprogram the firmware with binaries built from source.<\/p>\n<p>To provide some assurance the devices have not been tampered with after they have been programmed we put them in sealed bags with individual serial numbers.<\/p>\n<p>As the model of bags might change over time, we will publish photos of the bags used here as well as PGP signed statements for what serial numbers can be expected.\nAt this time, we do not keep records of which exact unit was sent to whom.<\/p>\n<p>This is a picture of the currently used bags:<\/p>\n<p><img alt=\"Alpha_tamper_bag_2016-12-16.png\" src=\"https:\/\/wiki.cryptech.is\/AlphaSealedBags\/AlphaSealedBags\/Alpha_tamper_bag_2016-12-16.png\"><\/p>\n<div class=\"highlight\"><pre><span><\/span><code><span class=\"gh\">-----BEGIN PGP SIGNED MESSAGE-----<\/span>\n<span class=\"na\">Hash<\/span><span class=\"o\">:<\/span><span class=\"w\"> <\/span><span class=\"s\">SHA512<\/span>\n\n<span class=\"s\">At<\/span><span class=\"w\"> <\/span><span class=\"s\">2016-12-16,<\/span><span class=\"w\"> <\/span><span class=\"s\">I<\/span><span class=\"w\"> <\/span><span class=\"s\">put<\/span><span class=\"w\"> <\/span><span class=\"s\">Cryptech<\/span><span class=\"w\"> <\/span><span class=\"s\">Alpha<\/span><span class=\"w\"> <\/span><span class=\"s\">units<\/span><span class=\"w\"> <\/span><span class=\"s\">into<\/span><span class=\"w\"> <\/span><span class=\"s\">sealed<\/span><span class=\"w\"> <\/span><span class=\"s\">bags<\/span><span class=\"w\"> <\/span><span class=\"s\">with<\/span><span class=\"w\"> <\/span><span class=\"s\">the<\/span>\n<span class=\"s\">following<\/span><span class=\"w\"> <\/span><span class=\"s\">serial<\/span><span class=\"w\"> <\/span><span class=\"s\">numbers:<\/span>\n\n<span class=\"w\">  <\/span><span class=\"s\">26<\/span><span class=\"w\"> <\/span><span class=\"s\">0<\/span><span class=\"w\"> <\/span><span class=\"s\">027<\/span><span class=\"w\"> <\/span><span class=\"s\">233<\/span><span class=\"w\"> <\/span><span class=\"s\">507<\/span>\n<span class=\"w\">  <\/span><span class=\"s\">26<\/span><span class=\"w\"> <\/span><span class=\"s\">0<\/span><span class=\"w\"> <\/span><span class=\"s\">027<\/span><span class=\"w\"> <\/span><span class=\"s\">233<\/span><span class=\"w\"> <\/span><span class=\"s\">508<\/span>\n<span class=\"w\">  <\/span><span class=\"s\">26<\/span><span class=\"w\"> <\/span><span class=\"s\">0<\/span><span class=\"w\"> <\/span><span class=\"s\">027<\/span><span class=\"w\"> <\/span><span class=\"s\">233<\/span><span class=\"w\"> <\/span><span class=\"s\">509<\/span>\n<span class=\"w\">  <\/span><span class=\"s\">26<\/span><span class=\"w\"> <\/span><span class=\"s\">0<\/span><span class=\"w\"> <\/span><span class=\"s\">027<\/span><span class=\"w\"> <\/span><span class=\"s\">233<\/span><span class=\"w\"> <\/span><span class=\"s\">510<\/span>\n<span class=\"w\">  <\/span><span class=\"s\">26<\/span><span class=\"w\"> <\/span><span class=\"s\">0<\/span><span class=\"w\"> <\/span><span class=\"s\">027<\/span><span class=\"w\"> <\/span><span class=\"s\">233<\/span><span class=\"w\"> <\/span><span class=\"s\">511<\/span>\n<span class=\"w\">  <\/span><span class=\"s\">26<\/span><span class=\"w\"> <\/span><span class=\"s\">0<\/span><span class=\"w\"> <\/span><span class=\"s\">027<\/span><span class=\"w\"> <\/span><span class=\"s\">233<\/span><span class=\"w\"> <\/span><span class=\"s\">512<\/span>\n<span class=\"w\">  <\/span><span class=\"s\">26<\/span><span class=\"w\"> <\/span><span class=\"s\">0<\/span><span class=\"w\"> <\/span><span class=\"s\">027<\/span><span class=\"w\"> <\/span><span class=\"s\">233<\/span><span class=\"w\"> <\/span><span class=\"s\">513<\/span>\n<span class=\"w\">  <\/span><span class=\"s\">26<\/span><span class=\"w\"> <\/span><span class=\"s\">0<\/span><span class=\"w\"> <\/span><span class=\"s\">027<\/span><span class=\"w\"> <\/span><span class=\"s\">233<\/span><span class=\"w\"> <\/span><span class=\"s\">514<\/span>\n<span class=\"w\">  <\/span><span class=\"s\">26<\/span><span class=\"w\"> <\/span><span class=\"s\">0<\/span><span class=\"w\"> <\/span><span class=\"s\">027<\/span><span class=\"w\"> <\/span><span class=\"s\">233<\/span><span class=\"w\"> <\/span><span class=\"s\">515<\/span>\n<span class=\"w\">  <\/span><span class=\"s\">26<\/span><span class=\"w\"> <\/span><span class=\"s\">0<\/span><span class=\"w\"> <\/span><span class=\"s\">027<\/span><span class=\"w\"> <\/span><span class=\"s\">233<\/span><span class=\"w\"> <\/span><span class=\"s\">516<\/span>\n<span class=\"w\">  <\/span><span class=\"s\">26<\/span><span class=\"w\"> <\/span><span class=\"s\">0<\/span><span class=\"w\"> <\/span><span class=\"s\">027<\/span><span class=\"w\"> <\/span><span class=\"s\">233<\/span><span class=\"w\"> <\/span><span class=\"s\">517<\/span>\n<span class=\"w\">  <\/span><span class=\"s\">26<\/span><span class=\"w\"> <\/span><span class=\"s\">0<\/span><span class=\"w\"> <\/span><span class=\"s\">027<\/span><span class=\"w\"> <\/span><span class=\"s\">233<\/span><span class=\"w\"> <\/span><span class=\"s\">518<\/span>\n<span class=\"w\">  <\/span><span class=\"s\">26<\/span><span class=\"w\"> <\/span><span class=\"s\">0<\/span><span class=\"w\"> <\/span><span class=\"s\">027<\/span><span class=\"w\"> <\/span><span class=\"s\">233<\/span><span class=\"w\"> <\/span><span class=\"s\">519<\/span>\n<span class=\"w\">  <\/span><span class=\"s\">26<\/span><span class=\"w\"> <\/span><span class=\"s\">0<\/span><span class=\"w\"> <\/span><span class=\"s\">027<\/span><span class=\"w\"> <\/span><span class=\"s\">233<\/span><span class=\"w\"> <\/span><span class=\"s\">520<\/span>\n<span class=\"w\">  <\/span><span class=\"s\">26<\/span><span class=\"w\"> <\/span><span class=\"s\">0<\/span><span class=\"w\"> <\/span><span class=\"s\">027<\/span><span class=\"w\"> <\/span><span class=\"s\">233<\/span><span class=\"w\"> <\/span><span class=\"s\">521<\/span>\n<span class=\"w\">  <\/span><span class=\"s\">26<\/span><span class=\"w\"> <\/span><span class=\"s\">0<\/span><span class=\"w\"> <\/span><span class=\"s\">027<\/span><span class=\"w\"> <\/span><span class=\"s\">233<\/span><span class=\"w\"> <\/span><span class=\"s\">522<\/span>\n<span class=\"w\">  <\/span><span class=\"s\">26<\/span><span class=\"w\"> <\/span><span class=\"s\">0<\/span><span class=\"w\"> <\/span><span class=\"s\">027<\/span><span class=\"w\"> <\/span><span class=\"s\">233<\/span><span class=\"w\"> <\/span><span class=\"s\">523<\/span>\n<span class=\"w\">  <\/span><span class=\"s\">26<\/span><span class=\"w\"> <\/span><span class=\"s\">0<\/span><span class=\"w\"> <\/span><span class=\"s\">027<\/span><span class=\"w\"> <\/span><span class=\"s\">233<\/span><span class=\"w\"> <\/span><span class=\"s\">524<\/span>\n<span class=\"w\">  <\/span><span class=\"s\">26<\/span><span class=\"w\"> <\/span><span class=\"s\">0<\/span><span class=\"w\"> <\/span><span class=\"s\">027<\/span><span class=\"w\"> <\/span><span class=\"s\">233<\/span><span class=\"w\"> <\/span><span class=\"s\">525<\/span>\n<span class=\"w\">  <\/span><span class=\"s\">26<\/span><span class=\"w\"> <\/span><span class=\"s\">0<\/span><span class=\"w\"> <\/span><span class=\"s\">027<\/span><span class=\"w\"> <\/span><span class=\"s\">233<\/span><span class=\"w\"> <\/span><span class=\"s\">526<\/span>\n\n<span class=\"na\">\/Fredrik<\/span>\n<span class=\"na\">-----BEGIN PGP SIGNATURE-----<\/span>\n<span class=\"na\">Version<\/span><span class=\"o\">:<\/span><span class=\"w\"> <\/span><span class=\"s\">GnuPG v2<\/span>\n\n<span class=\"s\">iQEcBAEBCgAGBQJYU\/MVAAoJEBmMGv1QUVLd+2gH\/jLZ7aUGlZ+Iwj6b746Hh6u1<\/span>\n<span class=\"s\">2JAZ+2tk5tRooTwNb4A5P3ewRcbjA0jPJQQlpVqZcxdt0DDjS16AR0LEaH2rWL++<\/span>\n<span class=\"s\">sj\/OtBm5rqAmVcf1NNvzpC8f8WWgRYhx4nNhWKnEcTBQXT9NbFQhQY0WH3ebupnn<\/span>\n<span class=\"s\">8PK0mX8PpfsjM\/3vxtVVLmi+vBsxv0hBcdl+t4IPw\/UbzozicF6jZpxRXxVujTE6<\/span>\n<span class=\"s\">WLGXaCnySS4T1zgtpewfgVMOMouGScUw5n2yHRZJpissGUVJtuPrOEmNFvDz7LRD<\/span>\n<span class=\"s\">i00Rc4i2emsKTgKrkMIKyQWSqFIQ1nBUQ5B5ES1Q50432cppbyEW2rJJZjAuxgM=<\/span>\n<span class=\"s\">=s2D5<\/span>\n<span class=\"gh\">-----END PGP SIGNATURE-----<\/span>\n<\/code><\/pre><\/div>","category":{"@attributes":{"term":"AlphaBoard"}}},{"title":"High resolution pictures of the Alpha board","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/AlphaBoardPictures","rel":"alternate"}},"published":"2016-12-15T22:44:00+00:00","updated":"2017-05-19T17:49:00+00:00","author":{"name":"Rob Austein"},"id":"tag:wiki.cryptech.is,2016-12-15:\/AlphaBoardPictures","content":"<p>Attached to this page are high resolution pictures.<\/p>\n<p>The current revision of the Alpha board is rev03.<\/p>\n<p>rev01 was the board known as the 'dev-bridge'.<\/p>\n<p>rev02 was functionally the same as the rev03, but in another form factor.<\/p>\n<p><img alt=\"Alpha_rev03_top_med.jpg\" src=\"https:\/\/wiki.cryptech.is\/AlphaBoardPictures\/AlphaBoardPictures\/Alpha_rev03_top_med.jpg\"><\/p>\n<p><img alt=\"Alpha_rev03_bottom_med.jpg\" src=\"https:\/\/wiki.cryptech.is\/AlphaBoardPictures\/AlphaBoardPictures\/Alpha_rev03_bottom_med.jpg\"><\/p>","category":{"@attributes":{"term":"AlphaBoard"}}},{"title":"Alpha Board Strategy","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/AlphaBoardStrategy","rel":"alternate"}},"published":"2016-12-15T22:43:00+00:00","updated":"2016-12-15T22:43:00+00:00","author":{"name":"Cryptech Core Team"},"id":"tag:wiki.cryptech.is,2016-12-15:\/AlphaBoardStrategy","summary":"<h1>The Cryptech Alpha Board<\/h1>\n<h2>Goal<\/h2>\n<p>Develop a first, custom HSM board that can be used to support a first set of applications as well as being used for further development of new functionality as well as security mechanisms such as tamper detection and protection, key storage etc. Deadline is to \u2026<\/p>","content":"<h1>The Cryptech Alpha Board<\/h1>\n<h2>Goal<\/h2>\n<p>Develop a first, custom HSM board that can be used to support a first set of applications as well as being used for further development of new functionality as well as security mechanisms such as tamper detection and protection, key storage etc. Deadline is to produce palpable results before summer, 2015.<\/p>\n<ul>\n<li>The use cases and requirements for the alpha board are specified on the <a href=\"https:\/\/wiki.cryptech.is\/wiki\/Dashboard\">Dashboard<\/a>.<\/li>\n<li>The basic blocks of the Alpha board is <a href=\"https:\/\/wiki.cryptech.is\/Hardware\">shown here<\/a>.<\/li>\n<li>The <a href=\"https:\/\/wiki.cryptech.is\/AlphaBoardComponents\">BOM and component requirements<\/a>.<\/li>\n<li>The detailed <a href=\"https:\/\/wiki.cryptech.is\/browser\/doc\/design\/Alpha_board_drawing.pdf\">Alpha board functional drawing<\/a>.<\/li>\n<\/ul>\n<h2>Plan<\/h2>\n<ol>\n<li>Choose FPGA and ARM (done)<\/li>\n<li>Develop BOM, requirements and functional diagram (done-ish).<\/li>\n<li>Develop complete <a href=\"https:\/\/wiki.cryptech.is\/AlphaSchematics\">schematics<\/a> (almost done).<\/li>\n<li>Develop dev-board ouorselves to connect chosen ARM to FPGA on Novena, to do some early development and testing in parallell with step 5.<\/li>\n<li>Get professional designer to do many-layer PCB from schematics.<\/li>\n<li>Manufacture a couple of boards (~10).<\/li>\n<li>Bug fix hardware+software.<\/li>\n<li>Make beta design.<\/li>\n<li>Manufacture more boards (~50).<\/li>\n<\/ol>\n<h2>Way forward<\/h2>\n<p>We currently use the Novena as a dev-board. It has a <a href=\"http:\/\/www.freescale.com\/webapp\/sps\/site\/prod_summary.jsp?code=i.MX6Q&amp;tab=Documentation_Tab&amp;pspll=1&amp;SelectedAsset=Documentation&amp;ProdMetaId=PID\/DC\/i.MX6Q&amp;fromPSP=true&amp;assetLockedForNavigation=true&amp;componentId=2&amp;leftNavCode=1&amp;pageSize=25&amp;Documentation=Documentation\/00610Ksd1nd%60%60Data%20Sheets&amp;fpsp=1&amp;linkline=Data%20Sheets\">Freescale i.MX6 CPU (ARM Cortex A9)<\/a>, and a Xilinx Spartan-6 LX45 CSG324-packaged FPGA.<br\/><\/p>\n<p>We want to over-size rather than under-size the FPGA on the Alpha board. The biggest FPGA from Xilinx\/Altera that does not require tools with a commercial license that we've found is the \u200bXilinx Artix-7 XC7A200T FBG484.<\/p>\n<p>We've only considered ARM CPUs. Either about the size of Cortex M3 \/ M4 (or future M7) or Cortex A8 \/ A9.<br\/>\nA design with an A8\/A9 turned out to be unattractive from a complexity and price point of view, so we're going to use one of the biggest M4 we could find. STM32F429.<\/p>\n<p>We are currently using a Freescale proprietary interface called EIM between the ARM and the FPGA on the Novena. EIM is not available with microcontrollers from ST, so we will use a similar interface made for connecting the ARM to external memory (called FMC). This interface runs at speeds up to 90 MHz, which is more than we are going to be using with our current FPGA cores.<\/p>\n<h2>Risks at this point<\/h2>\n<ol>\n<li>Taking too long deciding on what the Alpha board should contain.<\/li>\n<li>Ordering PCB design and manufacturing boards that just does not work for our purposes.<\/li>\n<li>Getting Alpha boards that require too much time to get working.<\/li>\n<\/ol>\n<h2>Conclusion<\/h2>\n<p>Use a high-end Cortex-M4 ARM.<br\/>\nThere is a huge difference in complexity between M4 and A9, mainly because of the DDR3 memory used with A9. An M4 design will both be easier to design, cheaper to both design and build and will be fast enough for all our early use cases anyways.<\/p>\n<p>Do not use the exact same FPGA, as it is too small to fit everything we need.<br\/><\/p>\n<p>Develop full schematics in-house.<br\/>\nIt turned out to be hard, costly or both, to outsource this part. We will probably spend less time developing the schematics ourselves than we would spend explaining what to develop to a third party.<\/p>","category":{"@attributes":{"term":"AlphaBoard"}}},{"title":"Review feedback of the Alpha schematics","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/AlphaReviewLog","rel":"alternate"}},"published":"2016-12-15T22:43:00+00:00","updated":"2016-12-15T22:43:00+00:00","author":{"name":"Cryptech Core Team"},"id":"tag:wiki.cryptech.is,2016-12-15:\/AlphaReviewLog","summary":"<h2>Power subsystem<\/h2>\n<table>\n<thead>\n<tr>\n<th>Comment<\/th>\n<th>Who<\/th>\n<th>Resolution<\/th>\n<th>Status<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>The LTS3060ITS8 is a 8-lead device but the symbol shows only 6 (there are 3 GND leads).<\/td>\n<td>Kent<\/td>\n<td>ft to correct mapping of pins between symbol and package<\/td>\n<td>Done<\/td>\n<\/tr>\n<tr>\n<td>The output capacitor C13 can have higher capacitance. The 2.2 uF is the lowest \u2026<\/td><\/tr><\/tbody><\/table>","content":"<h2>Power subsystem<\/h2>\n<table>\n<thead>\n<tr>\n<th>Comment<\/th>\n<th>Who<\/th>\n<th>Resolution<\/th>\n<th>Status<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>The LTS3060ITS8 is a 8-lead device but the symbol shows only 6 (there are 3 GND leads).<\/td>\n<td>Kent<\/td>\n<td>ft to correct mapping of pins between symbol and package<\/td>\n<td>Done<\/td>\n<\/tr>\n<tr>\n<td>The output capacitor C13 can have higher capacitance. The 2.2 uF is the lowest recommended value and since this is a X7R\/25V type it may well fall below that. I recommend 4.7uF to add some margin. C7 may also be changed to 4.7uF.<\/td>\n<td>Kent<\/td>\n<td>Updated schematics<\/td>\n<td>Done<\/td>\n<\/tr>\n<tr>\n<td>LMZ13608 has 11 pins plus an exposed pad (must be connected to pin 5) but only 9 pins are shown in the schematic symbol.<\/td>\n<td>Kent<\/td>\n<td>Will change symbol to show both name and pin number(s)<\/td>\n<td>Done<\/td>\n<\/tr>\n<tr>\n<td>The output voltage for LMZ13608 is calculated as 0.795 V * (1 + R8\/R9) which is 4.93 V. It is a bit low for a 5.0 V supply.<\/td>\n<td>Kent<\/td>\n<td>5 volts not used, just an intermediate voltage. No change required.<\/td>\n<td>Done<\/td>\n<\/tr>\n<tr>\n<td>I don't see any SH pin in the datasheet for the LMZ13608 device. Is it the one called NC?<\/td>\n<td>Kent<\/td>\n<td>ft check symbol, then ask Pavel to review<\/td>\n<td>ft done, pavel<\/td>\n<\/tr>\n<tr>\n<td>What form factor and main power supply should we use for the Alpha?<\/td>\n<td>ft<\/td>\n<td>Try to find drawing with dimensions for NUC computers, to see if we can use that form factor and power supplies<\/td>\n<td>Pavel<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2>Entropy source<\/h2>\n<table>\n<thead>\n<tr>\n<th>Comment<\/th>\n<th>Who<\/th>\n<th>Resolution<\/th>\n<th>Status<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>Add optocoupler as per Jacob's suggestion on tech@ 2015-07-24? The suggestion is to add a fast optocoupler to really isolate AGND from GND.<\/td>\n<td>Jacob W<\/td>\n<td>As this appears to require a bigger digitizer, which in turn might require another 3V3 regulator, we don't want to add that to this otherwise quite well tested part of the circuitry for the Alpha.<\/td>\n<td>Done<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2>STM32<\/h2>\n<table>\n<thead>\n<tr>\n<th>Comment<\/th>\n<th>Who<\/th>\n<th>Resolution<\/th>\n<th>Status<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>The JTAG port is not connected. For debug puposes, it could be good to have access to the JTAG port, at least at the prototype board.<\/td>\n<td>Kent<\/td>\n<td>We don't know of a reason to add the full JTAG, when we have SWD. At least not if we keep the LQFP package because then we don't think we need to be able to do boundary scan.<\/td>\n<td>Done<\/td>\n<\/tr>\n<tr>\n<td>The capacitors C22-C25 are connected between VCAP1\/2 and VCCO_3V3. According to the datasheet as well as AN4488 they shall be connected to GND. It should be enough with one 2.2uF capacitor for each pin.<\/td>\n<td>Kent<\/td>\n<td>Yes, change to GND instead of 3V3. Our interpretation is that we actually should have 2x2.2 for both VCAP1 and VCAP2. We also prefer 2x2.2 over  1x4.7 so not changing that.<\/td>\n<td>Done<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2>2x512 Mbit SDRAM for the ARM<\/h2>\n<table>\n<thead>\n<tr>\n<th>Comment<\/th>\n<th>Who<\/th>\n<th>Resolution<\/th>\n<th>Status<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>U6 has no speed grade specified. TSOP-II package is selected. The BGA package is much smaller and easier to handle in production.<\/td>\n<td>Kent<\/td>\n<td>We will investigate packages and speed<\/td>\n<td>Pavel<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2>Keystore memory, 128 Mbit<\/h2>\n<table>\n<thead>\n<tr>\n<th>Comment<\/th>\n<th>Who<\/th>\n<th>Resolution<\/th>\n<th>Status<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>Hard to see which resistor is R17 and R18. What is R17 (the left one) intended for?<\/td>\n<td>Kent<\/td>\n<td>Fixed the resistors. CS should be connected to ARM, default is \"not enabled\" through pull-up.<\/td>\n<td>Done<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2>RTC<\/h2>\n<table>\n<thead>\n<tr>\n<th>Comment<\/th>\n<th>Who<\/th>\n<th>Resolution<\/th>\n<th>Status<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>From where is 3V3_BATT supplied? Is it an external power source from connector JP3? Or the JP4 jumper?<\/td>\n<td>Kent<\/td>\n<td>Yes, external power source connected to JP4.<\/td>\n<td>Done<\/td>\n<\/tr>\n<tr>\n<td>Do we need a separate RTC chip at all?<\/td>\n<td>Jacob W<\/td>\n<td>Keeping it for the Alpha since it is already there.<\/td>\n<td>Done<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2>Micro SD card<\/h2>\n<table>\n<thead>\n<tr>\n<th>Comment<\/th>\n<th>Who<\/th>\n<th>Resolution<\/th>\n<th>Status<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>Which connector to use? Haven't found a good one with Eagle symbol. Some different kinds available.<\/td>\n<td>ft<\/td>\n<td>Remove SD card.<\/td>\n<td>Done<\/td>\n<\/tr>\n<tr>\n<td>Novena seems to have card reset capability (power control from MCU). Do we want the same?<\/td>\n<td>ft<\/td>\n<td>Remove SD card.<\/td>\n<td>Done<\/td>\n<\/tr>\n<tr>\n<td>Novena has two SD slots, and list power at 200mA. Do we need a separate power regulator for the SD card, or can we use VCCO_3V3?<\/td>\n<td>ft<\/td>\n<td>Remove SD card.<\/td>\n<td>Done<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2>2x USB UARTs for management and application access<\/h2>\n<table>\n<thead>\n<tr>\n<th>Comment<\/th>\n<th>Who<\/th>\n<th>Resolution<\/th>\n<th>Status<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>Should we add an EEPROM for FTDI USB related settings or not?<\/td>\n<td>ft<\/td>\n<td>Not adding anything not strictly necessary to the schematics.<\/td>\n<td>Done<\/td>\n<\/tr>\n<tr>\n<td>LED6 is the same type as LED1 at page 4 but they have different values at their resistors (220\/330 ohm).<\/td>\n<td>Kent<\/td>\n<td>Went with 330 for consistency.<\/td>\n<td>Done<\/td>\n<\/tr>\n<tr>\n<td>The recommended protection devices on D+ and D- are missing.<\/td>\n<td>Kent<\/td>\n<td>Pavel to look for reference<\/td>\n<td>pavel<\/td>\n<\/tr>\n<tr>\n<td>Hard to see what reference designators that belong to which component in some places.<\/td>\n<td>Kent<\/td>\n<td>Fredrik will improve clarity<\/td>\n<td>Done<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2>AVR Tiny Tamper Detect MCU<\/h2>\n<p>Fredrik to verify if Kent had comments about AVR\n| Comment | Who | Resolution | Status | \n| --- | --- | --- | --- | \n| | | | <\/p>\n<h2>Analog switch controlling access to the MKM<\/h2>\n<table>\n<thead>\n<tr>\n<th>Comment<\/th>\n<th>Who<\/th>\n<th>Resolution<\/th>\n<th>Status<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>Suggest changing this chip to an 74AC244 like the one used for the FPGA config memory.<\/td>\n<td>Pavel<\/td>\n<td>Will change.<\/td>\n<td>Done<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2>FPGA configuration<\/h2>\n<table>\n<thead>\n<tr>\n<th>Comment<\/th>\n<th>Who<\/th>\n<th>Resolution<\/th>\n<th>Status<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>The mode signals are fixed to SPI Master mode. If more flexibility is needed, see next comment, jumpers may be added.<\/td>\n<td>Kent<\/td>\n<td>This is intentional.<\/td>\n<td>Done<\/td>\n<\/tr>\n<tr>\n<td>One-bit data us for the configuration memory makes the configuration rather slow. If higher speed is preferable the SPI memory supports 4-bit data.<\/td>\n<td>Kent<\/td>\n<td>Bitstream is around 65 MBit, takes 4-5 seconds to load using single bit (@ 15MHz). We think that should be good enough.<\/td>\n<td>Done<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2>FPGA I\/O<\/h2>\n<table>\n<thead>\n<tr>\n<th>Comment<\/th>\n<th>Who<\/th>\n<th>Resolution<\/th>\n<th>Status<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>A lot of the FPGA I\/Os are unused. For debug purposes some of these can be made available by connecting them to a pin header. Unconnected BGA balls are very hard to use.<\/td>\n<td>Kent<\/td>\n<td>Added two more GPIOs from AVR to FPGA and two more from AVR to ARM. Remaining question is how many we should add from FPGA to ARM.<\/td>\n<td>Pavel<\/td>\n<\/tr>\n<tr>\n<td>A zero ohm resistor at the oscillator output can simplify debug.<\/td>\n<td>Kent<\/td>\n<td>Fredrik will add zero ohm resistor<\/td>\n<td>Done<\/td>\n<\/tr>\n<tr>\n<td>Joachim suggests, that we may want to have some high-speed extension interface for debugging and dumping large amounts of data. For example, we can implement GMII or RGMII using external GbE PHY and GPIO header(s). In that sense, at least one of the GPIO header pins should be connected to clock-capable (MRCC) FPGA pin.<\/td>\n<td>Pavel<\/td>\n<td>Pavel will finalize notes in schematics to enable this.<\/td>\n<td>pavel<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2>FPGA voltage regulators<\/h2>\n<table>\n<thead>\n<tr>\n<th>Comment<\/th>\n<th>Who<\/th>\n<th>Resolution<\/th>\n<th>Status<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>U14 and U15 have 38 pins but only 11 are visible in the schematic symbol. No pin numbers are visible. The NC pins must not be connected which should be shown.<\/td>\n<td>Kent<\/td>\n<td>Fredrik will update symbol to show pins.<\/td>\n<td>Done<\/td>\n<\/tr>\n<tr>\n<td>I am not familiar with the EN6347Q device so I would add ferrite cores on the outputs, for debug and measurement. Maybe that's what the zero ohm resistors are intended for?<\/td>\n<td>Kent<\/td>\n<td>Will change 0-ohm to ferrites. Pavel will look up part number, Fredrik will update schematics.<\/td>\n<td>pavel, ft<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2>FPGA power regulators<\/h2>\n<table>\n<thead>\n<tr>\n<th>Comment<\/th>\n<th>Who<\/th>\n<th>Resolution<\/th>\n<th>Status<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>The EN5364 device has 68 pins and 2 exposed pads but the symbol only shows 19 pins, without pin number.<\/td>\n<td>Kent<\/td>\n<td>Fredrik will update symbol to show pins<\/td>\n<td>Done<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h3>Additional comments from Kent<\/h3>\n<p>I have reviewed the schematic drawings for 'Cryptech Alpha board', rev 02\n(12\/28\/15), together with the block diagram, rev 0.010 (2015-05-27). I\nhave spent 8 hours on this review.<\/p>\n<h4>General<\/h4>\n<p>The block diagram does not comply with the schematics:<\/p>\n<table>\n<thead>\n<tr>\n<th>Comment<\/th>\n<th>Who<\/th>\n<th>Resolution<\/th>\n<th>Status<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>Analog switch replaced by line driver (IC2)<\/td>\n<td>Kent<\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>There is no reset block to the Tamper Detect CPU (U10) in the schematics<\/td>\n<td>Kent<\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>I can't find any Reset_n signal to the FPGA (U13) nor any FPGA reset block (maybe it is supposed to indicate the FPGA configuration?).<\/td>\n<td>Kent<\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>Interfaces for Smart Card and display\/control seems to be missing in the schematics JTAG port for the ARM (U4) is not present in the schematics<\/td>\n<td>Kent<\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>JTAG port for the Tamper Detect CPU (U10) is not present in the schematics<\/td>\n<td>Kent<\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>Master Key Memory (U12) type is different (23A640 vs 23K640)<\/td>\n<td>Kent<\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>Power supply voltages does not comply with the schematics<\/td>\n<td>Kent<\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>The battery near the RTC on the block diagram is not present in the schematics<\/td>\n<td>Kent<\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>Minor differences in component names (suggestion: remove details from block diagram)<\/td>\n<td><\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>The header information should be updated with design name\/ID and author.<\/td>\n<td>Kent<\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>Some components in the schematic (U1, U2, U14, U15, Q3) doesn't show pin numbers which make it harder to review<\/td>\n<td>Kent<\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>The sheets seems to have different sizes (1-13 differs from 14-26) and origo is placed in different positions in different pages. Not important but looks a bit odd.<\/td>\n<td>Kent<\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>Eagle doesn't seem to have a symbol for unconnected pins. If nothing else, a comment would be good so it is obvious that the pin shall be unconnected and is not forgotten.<\/td>\n<td>Kent<\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>On prototype boards it can sometimes be beneficial to insert zero ohm resistances on certain nets, typical clock and reset signals, to simplify debug. Typical places can be voltage regulator outputs and signals that are buried in the PCB.<\/td>\n<td>Kent<\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>The selected package for the CPU (U4) is LQFP208. The size is 30x30 mm compared to the TFBGA216 package that is only 13x13 mm. Also, the pitch is 0.5 mm for the LQFP208 while the TFBGA216 package has a ball pitch of 0.8 mm.<\/td>\n<td>Kent<\/td>\n<td>Joachim and ft thinks LQFP package makes sense for the Alpha - gives 208 \"test points\" and physical size not that important<\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>For debug purposes it is recommended to place test points for signals that are hard to reach, to simplify measurement.<\/td>\n<td>Kent<\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h4>Not Reviewed<\/h4>\n<p>A one day review doesn't allow a thorough design review. Some\nprioritizations are necessary. I have not reviewed:<\/p>\n<table>\n<thead>\n<tr>\n<th>Comment<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>FPGA pinout. The FPGA vendor tool (Vivado) does some of the checks. It checks that clock signals are placed at clock pins, that selected I\/O types are compatible with the bank structure. Vivado can also check that not to much I\/O switching power per bank is used and can also calculate power consumption (with correct user input).<\/td>\n<\/tr>\n<tr>\n<td>Power calculations. The FPGA power is heavily dependent on how it is used. This can be estimated with the Vivado tool.<\/td>\n<\/tr>\n<tr>\n<td>Supply voltage quality. This requires simulations that are out of scope for this review.<\/td>\n<\/tr>\n<tr>\n<td>Power sequencing.<\/td>\n<\/tr>\n<tr>\n<td>Physical properties like PCB symbols, layout issues, thermal design and board area use.<\/td>\n<\/tr>\n<tr>\n<td>Production test or optimization for production.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>","category":{"@attributes":{"term":"AlphaBoard"}}},{"title":"Alpha Board","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/AlphaBoard","rel":"alternate"}},"published":"2016-12-15T22:39:00+00:00","updated":"2019-01-22T08:46:00+00:00","author":{"name":"Joachim Str\u00f6mbergson"},"id":"tag:wiki.cryptech.is,2016-12-15:\/AlphaBoard","summary":"<h2>Rev 02<\/h2>\n<h3>Components<\/h3>\n<ul>\n<li>ARM Processor:  <a href=\"http:\/\/www.st.com\/content\/st_com\/en\/products\/microcontrollers\/stm32-32-bit-arm-cortex-mcus\/stm32f4-series\/stm32f429-439.html\">STM32F429<\/a><\/li>\n<li>FPGA: <a href=\"http:\/\/www.xilinx.com\/products\/silicon-devices\/fpga\/artix-7.html\">Xilinx Artix-7 XC7A200T-1<\/a><\/li>\n<li>Tamper Circuit: <a href=\"http:\/\/www.atmel.com\/devices\/ATTINY828.aspx\">ATtiny828<\/a><\/li>\n<\/ul>\n<h3>Status LEDs<\/h3>\n<table>\n<thead>\n<tr>\n<th>ID<\/th>\n<th>Color<\/th>\n<th>Meaning<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>01<\/td>\n<td>Green<\/td>\n<td>ARM LED 2<\/td>\n<\/tr>\n<tr>\n<td>02<\/td>\n<td>Red<\/td>\n<td>ARM LED 4<\/td>\n<\/tr>\n<tr>\n<td>03<\/td>\n<td>Blue<\/td>\n<td>ARM LED 1<\/td>\n<\/tr>\n<tr>\n<td>04<\/td>\n<td>Yellow<\/td>\n<td>ARM LED 3<\/td>\n<\/tr>\n<tr>\n<td>05<\/td>\n<td>Yellow<\/td>\n<td>Application Access USB UART Rx<\/td>\n<\/tr>\n<tr>\n<td>06<\/td>\n<td>Green<\/td>\n<td>Application Access USB \u2026<\/td><\/tr><\/tbody><\/table>","content":"<h2>Rev 02<\/h2>\n<h3>Components<\/h3>\n<ul>\n<li>ARM Processor:  <a href=\"http:\/\/www.st.com\/content\/st_com\/en\/products\/microcontrollers\/stm32-32-bit-arm-cortex-mcus\/stm32f4-series\/stm32f429-439.html\">STM32F429<\/a><\/li>\n<li>FPGA: <a href=\"http:\/\/www.xilinx.com\/products\/silicon-devices\/fpga\/artix-7.html\">Xilinx Artix-7 XC7A200T-1<\/a><\/li>\n<li>Tamper Circuit: <a href=\"http:\/\/www.atmel.com\/devices\/ATTINY828.aspx\">ATtiny828<\/a><\/li>\n<\/ul>\n<h3>Status LEDs<\/h3>\n<table>\n<thead>\n<tr>\n<th>ID<\/th>\n<th>Color<\/th>\n<th>Meaning<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>01<\/td>\n<td>Green<\/td>\n<td>ARM LED 2<\/td>\n<\/tr>\n<tr>\n<td>02<\/td>\n<td>Red<\/td>\n<td>ARM LED 4<\/td>\n<\/tr>\n<tr>\n<td>03<\/td>\n<td>Blue<\/td>\n<td>ARM LED 1<\/td>\n<\/tr>\n<tr>\n<td>04<\/td>\n<td>Yellow<\/td>\n<td>ARM LED 3<\/td>\n<\/tr>\n<tr>\n<td>05<\/td>\n<td>Yellow<\/td>\n<td>Application Access USB UART Rx<\/td>\n<\/tr>\n<tr>\n<td>06<\/td>\n<td>Green<\/td>\n<td>Application Access USB UART Tx<\/td>\n<\/tr>\n<tr>\n<td>07<\/td>\n<td>Yellow<\/td>\n<td>Management Access USB UART Rx<\/td>\n<\/tr>\n<tr>\n<td>08<\/td>\n<td>Green<\/td>\n<td>Management Access USB UART Tx<\/td>\n<\/tr>\n<tr>\n<td>09<\/td>\n<td>Green<\/td>\n<td>AVR LED 2<\/td>\n<\/tr>\n<tr>\n<td>10<\/td>\n<td>Red<\/td>\n<td>AVR LED 4<\/td>\n<\/tr>\n<tr>\n<td>11<\/td>\n<td>Blue<\/td>\n<td>AVR LED 1<\/td>\n<\/tr>\n<tr>\n<td>12<\/td>\n<td>Yellow<\/td>\n<td>AVR LED 3<\/td>\n<\/tr>\n<tr>\n<td>13<\/td>\n<td>Red<\/td>\n<td>FPGA Config NOT DONE<\/td>\n<\/tr>\n<tr>\n<td>14<\/td>\n<td>Red<\/td>\n<td>FPGA LED 3<\/td>\n<\/tr>\n<tr>\n<td>15<\/td>\n<td>Green<\/td>\n<td>FPGA LED 1<\/td>\n<\/tr>\n<tr>\n<td>16<\/td>\n<td>Yellow<\/td>\n<td>FPGA LED 2<\/td>\n<\/tr>\n<tr>\n<td>17<\/td>\n<td>Blue<\/td>\n<td>FPGA LED 0. <a href=\"https:\/\/git.cryptech.is\/core\/comm\/fmc\/tree\/src\/rtl\/fmc_indicator.v\">Toggles with sys_clk when FMC is active.<\/a><\/td>\n<\/tr>\n<tr>\n<td>18<\/td>\n<td>Green<\/td>\n<td>Power OK<\/td>\n<\/tr>\n<\/tbody>\n<\/table>","category":{"@attributes":{"term":"AlphaBoard"}}},{"title":"Alpha Schematics","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/AlphaSchematics","rel":"alternate"}},"published":"2016-12-15T22:39:00+00:00","updated":"2016-12-15T22:39:00+00:00","author":{"name":"Cryptech Core Team"},"id":"tag:wiki.cryptech.is,2016-12-15:\/AlphaSchematics","summary":"<p>The Alpha schematics are almost finished!<\/p>\n<p>PDF and Eagle files available for download here in the <a href=\"https:\/\/git.cryptech.is\/hardware\/tree\/eagle\/alpha\/rev02\">hardware<\/a> repository.<\/p>\n<p><code>https:\/\/wiki.cryptech.is\/browser\/hardware\/eagle\/alpha\/rev02<\/code><\/p>\n<p>The schematics are based on the dev-bridge board that we made in the summer of 2015, which is why it is called rev02 \u2026<\/p>","content":"<p>The Alpha schematics are almost finished!<\/p>\n<p>PDF and Eagle files available for download here in the <a href=\"https:\/\/git.cryptech.is\/hardware\/tree\/eagle\/alpha\/rev02\">hardware<\/a> repository.<\/p>\n<p><code>https:\/\/wiki.cryptech.is\/browser\/hardware\/eagle\/alpha\/rev02<\/code><\/p>\n<p>The schematics are based on the dev-bridge board that we made in the summer of 2015, which is why it is called rev02.<\/p>\n<p>We are currently seeking review of the schematics to finalize them before starting layout. A log of various peoples review comments is kept <a href=\"https:\/\/wiki.cryptech.is\/AlphaReviewLog\">here<\/a>.<\/p>","category":{"@attributes":{"term":"AlphaBoard"}}},{"title":"CrypTech Alpha Board BOM and PCB design requirement sketch","link":{"@attributes":{"href":"https:\/\/wiki.cryptech.is\/AlphaBoardComponents","rel":"alternate"}},"published":"2015-03-09T00:00:00+00:00","updated":"2015-03-25T00:00:00+00:00","author":{"name":"Joachim Str\u00f6mbergson"},"id":"tag:wiki.cryptech.is,2015-03-09:\/AlphaBoardComponents","summary":"<p>This document contains a list of component level description and requirements for the Crypteh Alpha board.<br\/>\nThe document is to be used as a BOM (Bill Of Materials) and PCB design requirement description for discussing with PCB designers on what we want to have designed.<br\/>\nThe block diagram for the \u2026<\/p>","content":"<p>This document contains a list of component level description and requirements for the Crypteh Alpha board.<br\/>\nThe document is to be used as a BOM (Bill Of Materials) and PCB design requirement description for discussing with PCB designers on what we want to have designed.<br\/>\nThe block diagram for the Alpha board can be seen at: <a href=\"https:\/\/wiki.cryptech.is\/Hardware\">Hardware<\/a><\/p>\n<p>The Alpha board basically consists of three major sub systems:<br\/>\n1. <strong>The FPGA Sub System<\/strong><br\/>\n   Used to implement CrypTech crypto\/security cores accessible by the CPU as coprocessors.<br\/><\/p>\n<ol>\n<li>\n<p><strong>The CPU Sub System<\/strong><br\/>\n   Talks to host systems and handles incoming commands. Basically implements the application interface.\n   Controls the FPGA Sub System. The CPU Sub System is heavily inspired\/based on the CPU parts of the Novena and the iMX6 Rex boards.<br\/><\/p>\n<\/li>\n<li>\n<p><strong>The Tamper Detect Sub System<\/strong><br\/>\n   Responsible for implementing tamper detection and control\/alarm as a separate functionality from the CPU.\n   On the Alpha board this system is fairly simplistic. But we want to at least have a minor MCU that can run\n   independently on battery power and control the Master Key Memory (MKM). detect external events and generate\n   alarms. This allows us to start developing and reason about tamper detection and monitoring separately from the CPU.<\/p>\n<\/li>\n<\/ol>\n<p>The Alpha board should preferably be a single board with all three sub systems on the same board.<\/p>\n<p>We are currently using the <a href=\"http:\/\/www.kosagi.com\/w\/index.php?title=Novena_Main_Page\">Novena<\/a> board, and the Alpha board CPU Sub System functionality from is based on the Novena. We also have a trust in the <a href=\"http:\/\/www.imx6rex.com\/\">iMX6 Rex<\/a> board. Using the the Novena and\/or iMX6 Rex as basis for the Alpha board design might (should) be a good way forward.<\/p>\n<h3>Authors and timeline\/revision history<\/h3>\n<p>Joachim Str\u00f6mbergson, Fredrik Thulin<\/p>\n<ul>\n<li>2015-03-25: Updates from group and maillist discussions. Sync with the diagram.<\/li>\n<li>2015-03-16: Updates from group discussions.<\/li>\n<li>2015-03-09: Work started. Initial versions with headers for all blocks.<\/li>\n<\/ul>\n<h1>FPGA Sub System<\/h1>\n<h3>FPGA<\/h3>\n<p>The board should be equipped with a Xilinx Artix-7 200T FPGA device, more specifically XC7A200T FBG484 speed grade -3.<\/p>\n<ul>\n<li><a href=\"http:\/\/www.xilinx.com\/products\/silicon-devices\/fpga\/artix-7.html\">Xilinx Artix-7 XC7A200T FBG484.<\/a><br\/><\/li>\n<li><a href=\"http:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ds180_7Series_Overview.pdf\">Product family overview<\/a><br\/><\/li>\n<\/ul>\n<p>The FPGA pad layout should be compatible with the Xilinx Artix-7 FGG484 used by XC7A100T and XC7A75T.<\/p>\n<h3>FPGA Clocking and Reset<\/h3>\n<ul>\n<li>There should be a separate clock, fpga_clk, for the FPGA that starts providing a clock signal at power up. The base frequency for fpga_clk should be 50 MHz.<\/li>\n<li>There should be a separate reset circuitry for the FPGA that resets the FPGA at power up and make the FPGA read the configuration from the confguration memory.<\/li>\n<li>The ARM CPU should be able to reset the FPGA to force it reload the confiuration from configuration memory. The CPUY should be able to reset the FPGA by asserting a GPIO. The ability of the CPU to force reset should be possible to remove by removing a jumper.<\/li>\n<\/ul>\n<h3>FPGA CPU Interface<\/h3>\n<ul>\n<li>The FPGA is connected to the CPU using the i.MX6 EIM interface.<\/li>\n<li>The data width is 16 bits.<\/li>\n<li>The address width is 24 bits.<\/li>\n<li>The data bus and address bus should be separate buses between the CPU and the FPGA.<\/li>\n<li>The clock frequency of the EIM interface layout should support 66 MHz clock frequency.<\/li>\n<li>There should be at least three separate digital signals connected between the FPGA and GPIOs on the CPU to be able to send interrupt\/events from the FPGA to the CPU. Things like RSA operation completed to internal alarms. (Slow signals.)<\/li>\n<\/ul>\n<h3>FPGA Debug Interface<\/h3>\n<ul>\n<li>The FPGA JTAG interface should be available on a header. The header shall be compatible with the <a href=\"http:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ds593.pdf\">Xilinx Platform Cable USB II<\/a>.<\/li>\n<\/ul>\n<h3>FPGA Extras<\/h3>\n<ul>\n<li>8 LEDs connected to output pins on the FPGA. For general debug uses.<\/li>\n<li>4 LEDs connected to output pins on the FPGA. For heartbeat and status signalling.<\/li>\n<li>100-mil header with VCC+GND+8 pins connected to pins on the FPGA for general input\/output. Slow speed, 3v3 TTL. Some ESD protection would be considered good.<\/li>\n<\/ul>\n<h3>FPGA Configuration and Configuration Memory<\/h3>\n<ul>\n<li>The FPGA should read it's bitstream from the FPGA config memory by itself (Master mode).<\/li>\n<li>\n<p>The FPGA is connected to the config memory with an SPI interface.<\/p>\n<\/li>\n<li>\n<p>The ARM CPU should be able to download a bitstream into config memory by stealing the SPI interface.<\/p>\n<\/li>\n<li>\n<p>The ability to steal the SPI interface is implemented using a transparent MUX controlled by the CPU. The MUX control and the SPI interface to the MUX from the CPU should be possible to remove by removing jumper for the signals mux_ctrl, MISO, MOSI, MCLK.<\/p>\n<\/li>\n<li>\n<p>Suggestion for FPGA config memory is <a href=\"http:\/\/www.micron.com\/parts\/nor-flash\/serial-nor-flash\/m25p128-vme6gb\">M25P128 EEPROM from Micron<\/a>, with a jumper controlling the write-enable pin.<\/p>\n<\/li>\n<li>Suggested MUX is the Quad 2-channel Analog Switch: ON Semi. MC14551B <a href=\"http:\/\/www.onsemi.com\/pub_link\/Collateral\/MC14551B-D.PDF\">http:\/\/www.onsemi.com\/pub_link\/Collateral\/MC14551B-D.PDF<\/a><\/li>\n<\/ul>\n<h3>External RAM and Flash<\/h3>\n<p>No external RAM or Flash memories for FPGA application functionality shall be present and is connected to the FPGA on the Alpha board.<\/p>\n<h3>Master Key Memory<\/h3>\n<ul>\n<li>The Master Key Memory (MKM) is a serial SRAM memory.<\/li>\n<li>The MKM is connected to the FPGA with a SPI interface.\n  The MKM is connected to the Tamper Sub System with the same SPI interface.<\/li>\n<li>The FPGA can read and write to the memory.<\/li>\n<li>The Tamper Sub System controller can read and writeto the memory. Optionally the MISO input wire to the Tamper Sub System can be tied low by setting using a jumper. This should cause the tamper controller to only read zeros from the memory and thus only be able to write to the memory. The Tamper Sub System Controller has strict priority over the CPU. Basically an external switch between the memory, the controller and CPU.<\/li>\n<li>The MKM is powered by a separate power supply using a CR2032 cell battery. The VCC pin connected to the battery should be under control from the Tamper Sub System controller. A transistor or analog switch controlled by the Tamper Sub System controller.<\/li>\n<\/ul>\n<p>Suggested components for the MKM and the switch:<\/p>\n<ul>\n<li>Memory: Microchip serial SRAM. 23A640, 8 kByte, 8-TSSOP or 8-SOIC<\/li>\n<\/ul>\n<p><a href=\"http:\/\/ww1.microchip.com\/downloads\/en\/DeviceDoc\/22127a.pdf\">http:\/\/ww1.microchip.com\/downloads\/en\/DeviceDoc\/22127a.pdf<\/a><br\/><\/p>\n<ul>\n<li>Quad 2-channel Analog Switch: ON Semi. MC14551B<\/li>\n<\/ul>\n<p><a href=\"http:\/\/www.onsemi.com\/pub_link\/Collateral\/MC14551B-D.PDF\">http:\/\/www.onsemi.com\/pub_link\/Collateral\/MC14551B-D.PDF<\/a><\/p>\n<h3>Entropy Sources<\/h3>\n<ul>\n<li>The avalanche noise entropy source should be implemented according to <a href=\"https:\/\/wiki.cryptech.is\/AlphaBoardComponents\/AlphaBoardComponents\/alpha_board_noise_source.pdf\">existing schematics<\/a>.<\/li>\n<li>The noise source should have a shielding can and suitable ground plane etc. to keep radiation of entropy bits as low as possible.<\/li>\n<li>The \"12-15v stable\" VCC should be controllable by the FPGA (enable\/disable  controlled by output pin on FPGA) to increase life time of components.\n  Power requirements for this VCC is &lt; 100 mA (needs measuring, but probably &lt; 50 mA).<\/li>\n<\/ul>\n<h1>Processor Sub System<\/h1>\n<h3>CPU<\/h3>\n<p>The main CPU is a ST Microelectronics STM32F429BIT6 Cortex-M4 based MCU running at 180 MHz. The package used is the 208 pin LQFP.<\/p>\n<ul>\n<li><a href=\"http:\/\/www.st.com\/st-web-ui\/static\/active\/en\/resource\/technical\/document\/reference_manual\/DM00031020.pdf\">Reference Manual<\/a> (pdf)<\/li>\n<li><a href=\"http:\/\/www.st.com\/st-web-ui\/static\/active\/en\/resource\/technical\/document\/datasheet\/DM00077036.pdf\">Product Specification<\/a> (pdf)<\/li>\n<li><a href=\"http:\/\/www.st.com\/st-web-ui\/static\/active\/en\/resource\/technical\/document\/datasheet\/DM00077036.pdf\">Data Sheet<\/a> (pdf)<\/li>\n<\/ul>\n<h3>Host Interface<\/h3>\n<ul>\n<li>USB interface. USB 2.0 Full Speed compliant.<\/li>\n<li>USB interface implemented using an external USB-UART interface chip connected to a high speed (3 Mbps capable) UART interface on the CPU.<\/li>\n<li>Suggested USB-UART component:<\/li>\n<li>http:\/\/www.ftdichip.com\/Support\/Documents\/DataSheets\/ICs\/DS_FT232H.pdf<\/li>\n<li>LQPF48 packaging<\/li>\n<\/ul>\n<h3>Authenticator, Management and Backup Interface<\/h3>\n<ul>\n<li>USB interface. USB 2.0 Full Speed compliant.<\/li>\n<li>USB interface implemented using an external USB-UART interface chip connected to a high speed (3 Mbps capable) UART interface on the CPU.<\/li>\n<li>Suggested USB-UART component:<\/li>\n<li>http:\/\/www.ftdichip.com\/Support\/Documents\/DataSheets\/ICs\/DS_FT232H.pdf<\/li>\n<li>LQPF48 packaging<\/li>\n<\/ul>\n<h3>External Storage<\/h3>\n<ul>\n<li>SD Card connected as Micro SD card with 4 bit data interface (like the Novena.)<\/li>\n<li>Support for at least 2 GByte.<\/li>\n<\/ul>\n<h3>External RAM<\/h3>\n<p>The STM32 CPU supports two separate SDRAM banks. We use both of them with as big SDRAM chips we can find for each bank. The chip used is 64 MByte for a total of 128 Mbyte RAM.<\/p>\n<ul>\n<li><a href=\"http:\/\/www.issi.com\/WW\/pdf\/42-45R-S-32160F.pdf\">ISSI IS45S32160F 64 MByte SDRAM with 32 bit data interface<\/a><\/li>\n<\/ul>\n<h3>Real Time Clock<\/h3>\n<ul>\n<li>Battery backed RTC with calendar\/date information.\n  Connected to the CPU via serial, SPI or other interface.<\/li>\n<li>Suggested chip: Microchip MCP79411 or MCP79412 connected to the CPU via I2C.\n  <a href=\"http:\/\/www.microchip.com\/wwwproducts\/Devices.aspx?product=MCP79411\">http:\/\/www.microchip.com\/wwwproducts\/Devices.aspx?product=MCP79411<\/a><br\/>\n  <a href=\"http:\/\/ww1.microchip.com\/downloads\/en\/DeviceDoc\/20002266G.pdf\">http:\/\/ww1.microchip.com\/downloads\/en\/DeviceDoc\/20002266G.pdf<\/a><br\/>\n  This chip requires an external 32 kHz crystal.<\/li>\n<li>Note: these chips contain per chip unique IDs as well as small EEPROM memory that can be memory protected.<\/li>\n<\/ul>\n<h3>Keystore<\/h3>\n<ul>\n<li>The keystore memory is a non volatile memory (NVRAM, EEPROM, Flash) with size of at least 8 MByte<\/li>\n<li>The keystore memory is connected to the CPU via a separate SPI interface.<\/li>\n<\/ul>\n<h3>CPU Debug port<\/h3>\n<ul>\n<li>CPU JTAG on header.<\/li>\n<\/ul>\n<h3>CPU Misc<\/h3>\n<ul>\n<li>Four LEDs conneced to the GPIOs on the CPU to allow heartbeat as well as status and debug signalling.<\/li>\n<li>We want 8 general I\/Os with direction controlled by the CPU. The I\/O:s should be present on a header. One purpose for these I\/O:s is to connect:<\/li>\n<li>Keypad and LCD display<\/li>\n<li>Smartcart reader via I2C<\/li>\n<li>Bitbanged serial port for debugging<\/li>\n<\/ul>\n<p>We may implement this keypad, smartcard reader and display using a simple MCU based board.<\/p>\n<h3>CPU Interfaces Needed<\/h3>\n<p>SPI Interfaces<\/p>\n<ul>\n<li>FPGA Config memory<\/li>\n<li>Key storage memory<\/li>\n<li>Master Key memory<\/li>\n<\/ul>\n<p>FPGA Interface<\/p>\n<ul>\n<li>EIM interface<\/li>\n<\/ul>\n<p>Asynch serial ports (UARTs)<\/p>\n<ul>\n<li>Host interface (high speed)<\/li>\n<li>Management interface (high speed)<\/li>\n<li>Tamper Sub System<\/li>\n<\/ul>\n<p>Memory Interfaces<\/p>\n<ul>\n<li>DDR3<\/li>\n<li>External SD Flash memory<\/li>\n<\/ul>\n<p>GPIOs<\/p>\n<ul>\n<li>3 signals from FPGA to CPU for signalling<\/li>\n<li>1 signal from CPU to FPGA reset circuit to force reset<\/li>\n<li>1 signal from CPU to FPGA confgig mem mux for control<\/li>\n<li>3 signals from Tamper Sub System controller to CPU<\/li>\n<\/ul>\n<h1>Tamper Sub System<\/h1>\n<p>The Tamper Sub System on the Alpha Board is simplistic and does not do a lot of detection. But the sub system should be there to allow us to test and develop tamper detection mechanisms.<\/p>\n<h3>Tamper Sub System Controller<\/h3>\n<ul>\n<li>A simple 8-bit MCU. Atmel AVR.<\/li>\n<li>Suggested chip: ATTINY828R-AU. Has 28 GPIOs which is definitely more than we've used for this design.<\/li>\n<li>The Tamper Detection Sub System Controlller may need a separate 32 kHz crystal for periodical wake up.\n  (The MCU should be able to wake up based on internal clock source.)<\/li>\n<li>The JTAG interface for debug and firmware download should be accessible via a header.<\/li>\n<li>The MCU should at least have four LEDs under GPIO control to allow heartbeat, status and debug signalling.<\/li>\n<\/ul>\n<h3>CPU interface<\/h3>\n<ul>\n<li>A simple serial (UART) interface between the CPU and the controller. The serial interface can be removed by removing jumpers.<\/li>\n<li>One or a couple separate signals for event signalling from the Tamper Detection Sub System to the CPU Sub System. Slow speed 3V3 LVTTL.<\/li>\n<\/ul>\n<h3>Tamper Detection Mechanisms<\/h3>\n<ul>\n<li>A separate push button connected to the controller.<\/li>\n<li>Possibly using the internal temperature detection in the MCU.<\/li>\n<li>At least four digital input pins on a header for four different digital (HIGH) tamper detection mechanisms.<\/li>\n<li>At least two digital output pins on a header for four different digital (HIGH) tamper alarms.<\/li>\n<\/ul>\n<h3>Tamper Power Supply<\/h3>\n<ul>\n<li>Battery backed. CR2032 cell battery.<\/li>\n<\/ul>\n<h1>Board Form Factor and Power Supply<\/h1>\n<h2>Form factor<\/h2>\n<p>Reasonable small to easily fit all functionality\nHoles to allow mounting the boards using board distances.<\/p>\n<h2>Power Supply<\/h2>\n<p>Power Supply similar to the Power Supply on the Novena.\n7-19V nominal range. 2.5A typical. Max 3A at 12V.<\/p>\n<p>The board is powered from 18V (or 24V) DC from a standard external power supply.\nIt should be possible to power the board with a external 110V AC at 60 Hz and 230V AC at 50 Hz.<\/p>\n<p>The on board power supply block should provide a number of voltage supplies needed by the board. We need at least 5V, 3.3V, 2.5V 1.8V, 1.375V.\nWe also need a stable, low noise 12V voltage supply to power the Cryptech Avalanche noise source.<\/p>\n<p>The board designer should provide information about the power consumtion for the board. What is the current required at 12V?<\/p>","category":{"@attributes":{"term":"AlphaBoard"}}}]}