USENIX conference on Hot topics in parallelism, May 26, 2011
Crunching large graphs is the basis of many emerging applications, such as social network analysi... more Crunching large graphs is the basis of many emerging applications, such as social network analysis and bioinformatics. Graph analytics algorithms exhibit little locality and therefore present significant performance challenges. Hardware multithreading systems (e.g., Cray XMT) show that with enough concurrency, we can tolerate long latencies. Unfortunately, this solution is not available with commodity parts. Our goal is to develop a latency-tolerant system built out of commodity parts and mostly in software. The proposed system includes a runtime that supports a large number of lightweight contexts, full-bit synchronization and a memory manager that provides a high-latency but high-bandwidth global shared memory. This paper lays out the vision for our system and justifies its feasibility with a performance analysis of the runtime for latency tolerance.
IEEE Transactions on Pattern Analysis and Machine Intelligence, Mar 1, 1987
We describe the current state of a system that recognizes printed text of various fonts and sizes... more We describe the current state of a system that recognizes printed text of various fonts and sizes for the Roman alphabet. The system combines several techniques in order to improve the overall recognition rate. Thinning and shape extraction are performed directly on a graph of the run-leiigth encoding of a binary image. The resulting strokes and other shapes are mapped, using a shape-clustering approach, into binary features which are then fed into a statistical Bayesian classifier. Large-scale trials have shown better than 97 percent top choice correct performance on mixtures of six dissimilar fonts, and over 99 percent on most single fonts, over a range of point sizes. Certain remaining confusion classes are disambiguated through contour analysis, and characters suspected of being merged are broken aiid reclassified. Finally, layout and linguistic context are applied. The results are illustrated by sample pages.
Motivation: Biological system behaviors are often the outcome of complex interactions among a lar... more Motivation: Biological system behaviors are often the outcome of complex interactions among a large number of cells and their biotic and abiotic environment. Computational biologists attempt to understand, predict and manipulate biological system behavior through mathematical modeling and computer simulation. Discrete agentbased modeling (in combination with high-resolution grids to model the extracellular environment) is a popular approach for building biological system models. However, the computational complexity of this approach forces computational biologists to resort to coarser resolution approaches to simulate large biological systems. Highperformance parallel computers have the potential to address the computing challenge, but writing efficient software for parallel computers is difficult and time-consuming. Results: We have developed Biocellion, a high-performance software framework, to solve this computing challenge using parallel computers. To support a wide range of multicellular biological system models, Biocellion asks users to provide their model specifics by filling the function body of pre-defined model routines. Using Biocellion, modelers without parallel computing expertise can efficiently exploit parallel computers with less effort than writing sequential programs from scratch. We simulate cell sorting, microbial patterning and a bacterial system in soil aggregate as case studies. Availability and implementation: Biocellion runs on x86 compatible systems with the 64 bit Linux operating system and is freely available for academic use. Visit http://biocellion.com for additional information.
Preston Briggs is a Senior Engineer at Reservoir Labs and an Affiliate Professor in Computer Scie... more Preston Briggs is a Senior Engineer at Reservoir Labs and an Affiliate Professor in Computer Science and Engineering at the University of Washington. He received a PhD in computer science from Rice University in 1992. [email protected] The rising importance of data-intensive applications has fueled the growth of a plethora of distributed computing frameworks, including Hadoop, Spark, and GraphLab. We have developed a system called Grappa [1, 2] to aid programmers in developing new frameworks. Grappa provides a distributed shared memory abstraction to hide complexity from the programmer, and takes advantage of parallelism in the data to hide remote access latency and to trade latency for more performance. These techniques allow it to outperform existing frameworks by up to an order of magnitude.
Previous theories on computing functions of moving data have assumed either that motion is predet... more Previous theories on computing functions of moving data have assumed either that motion is predetermined or that information about it is provided on-line: changes to data values are immediately available to the computational device. As a consequence, the models associated with these theories neglect data acquisition costs. In many computer application problems, data acquisition costs are comparable to, or may even surpass, those of computation. Lacking an applicable computational theory, these problems have been solved in the past by ad hoc methods. This work identifies and studies the general class of Data in Motion problems: those requiring the repeated computation of a function of data following arbitrary motion and having significant acquisition costs. The thesis statement is that data acquisition costs can be reduced by using old data, acquired when computing the function previously, to determine which current data values to obtain. For the purpose of studying the limitations o...
We develop a series of quicksort algorithms for the Sequent Symmetry shared memory parallel compu... more We develop a series of quicksort algorithms for the Sequent Symmetry shared memory parallel computer. By employing a novel yet simple parallel splitting algorithm and dynamic scheduling we are able to achieve a speedup of 13 with 16 processors over the performance of sequential quicksort on one processor. This work provides experimental evidence that asynchronous algorithms’ more uniform usage of shared resources may make them less susceptible to bottlenecks on real machines. Introduction: On sequential processors, Quicksort is one of the most e cient algorithms for sorting large arrays of data [Hoa62]. Three factors are eminently responsible for its speed: locality of memory references, a tight inner loop, and, on average, a small number of comparisons. Locality ensures both that cache prefetching can be exploited and that paging is minimal. Because a high proportion of the inner loop operations are comparisons, the computational overhead per comparison is small. Even though some o...
The broad environmental, societal and animal welfare issues associated with large-scale animal pr... more The broad environmental, societal and animal welfare issues associated with large-scale animal protein production are well-documented, and cultivated meat represents a potentially more sustainable alternative protein form to conventional production methods. Some believe cultivated meat is years away from commercial success; however, computational modeling has real potential to reduce the timeline for commercial roll-out. In June, 2019, a diverse group of stakeholders attended the inaugural Cultivated Meat Modeling Consortium meeting in Seattle, Washington to develop a multiscale modeling framework for cultivated meat manufacturing. This whitepaper was created from the extensive brainstorming that occurred during the meeting and afterwards. The early stage framework presented here is meant only as a beginning, and our hope is that this paper will drive future discussions and generate more collaborations that maximize the utility of computational modeling in the areas outlined here and beyond.
Skin is our primary barrier to the outside world, protecting us from physical, biological and che... more Skin is our primary barrier to the outside world, protecting us from physical, biological and chemical threats. Developing innovative products that preserve and improve skin barrier function requires a thorough understanding of the mechanisms underlying barrier response to topical applications. In many fields, computer simulations already facilitate understanding, thus accelerating innovation. Simulations of software models allow scientists to test hypothesized mechanisms by comparing predicted results to physical observations. They also enable virtual product optimization, without physical experiments, once mechanisms have been validated. The physical accessibility and abundant knowledge of skin structure makes it a prime candidate for computational modeling. In this article, we describe a computational multiscale multicellular skin model used to simulate growth and response of the epidermal barrier. The model integrates several modeling styles and mathematical frameworks including...
This paper describes the processor scheduling issues specific to the Tera MTA (Multi Threaded Arc... more This paper describes the processor scheduling issues specific to the Tera MTA (Multi Threaded Architecture) computer system and presents solutions to classic scheduling problems. The Tera MTA exploits parallelism at all levels, from fine-grained instruction-level parallelism within a single processor to parallel programming across processors, to multiprogramming among several applications simultaneously. Consequently, processor scheduling occurs at many levels, and managing these levels poses unique and challenging scheduling concerns. We describe the processor scheduling algorithms of the user level runtime and operating system and describe the issues relevant to each. Many of the issues encountered and solutions proposed are novel, given the multithreaded, multiprogrammed nature of our architecture.
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming, 2006
While the high-performance computing world is dominated by distributed memory computer systems, a... more While the high-performance computing world is dominated by distributed memory computer systems, applications that require random access into large shared data structures continue to motivate development of ever larger shared-memory parallel computers such as Cray's MTA and SGI's Altix systems. To support scalable application performance on such architectures, the memory allocator must be able to satisfy requests at a rate proportional to system size. For example, a 40 processor Cray MTA-2 can experience over 5000 concurrent requests, one from each of its 128 streams per processor. Cray's Eldorado, to be built upon the same network as Sandia's 10,000 processor Red Storm system, will sport thousands of multithreaded processors leading to hundreds of thousands of concurrent requests. In this paper, we present MAMA, a scalable shared-memory allocator designed to service any rate of concurrent requests. MAMA is distinguished from prior work on shared-memory allocators in that it employs software combining to aggregate requests serviced by a single heap structure: Hoard and MTA malloc necessitate repetition of the underlying heap data structures in proportion to processor count. Unlike Hoard, MAMA does not exploit processorlocal data structures, limiting its applicability today to systems that sustain high utilization in the presence of global references such as Cray's MTA systems. We believe MAMA's relevance to other shared-memory systems will grow as they become increasingly multithreaded and, consequently, more tolerant of references to non-local memory. We show not only that MAMA scales on Cray MTA systems, but also that it delivers absolute performance competitive with allocators employing heap repetition. In addition, we demonstrate that performance of repetition-based allocators does not scale under heavy loads. We also argue more generally that methods using repetition alone to support concurrency are subject to an impractical tradeoff of scalability against space consumption: when scaled up to meet increasing concurrency demands, repetition-based allocators necessarily house unused space p 2 quadratic in the number of processors p. Hierarchical structure may reduce this to p log p, but in building large-scale shared-memory parallel computers, unused memory more than linear in p is unacceptable. MAMA, in con-Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee.
Programs that simulate complex-structure deformation scale poorly on most vector multiprocessors ... more Programs that simulate complex-structure deformation scale poorly on most vector multiprocessors and MPPs. The authors worked on an alternative architecture-the Tera MTA-and tested performance results for a model crash problem using LS-DYNA code
Large-scale parallel discrete event simulations of massive networks, such as the Internet, are &q... more Large-scale parallel discrete event simulations of massive networks, such as the Internet, are "Grand Challenge" problems: packet level simulation of even a small fraction of the Internet would consume the resources of the most powerful computers available. We reimplement the SSF scalable simulation framework so we can run large-scale network simulations originally written for DaSSF. Our implementation, CraySSF, is designed for the Cray-MTA, a multithreaded supercomputer architecture developed specifically to address large-scale computations of the kind that are not easily distributed. We describe the architecture, implementation issues, and preliminary performance results on a variety of (stock) serial and parallel architectures.
Proceedings of the 2nd conference on Computing frontiers, 2005
This paper introduces Eldorado, a third generation multithreaded architecture. Previous Cray mult... more This paper introduces Eldorado, a third generation multithreaded architecture. Previous Cray multithreaded systems were plagued by unreliable hardware and high costs. Eldorado corrects these problems by using many parts built for other commercial systems. Its compute processor is a 500 MHZ multithreaded processor architecturally similar to the MTA-2 processor; but its interconnection network, I/O subsystem, and service processors are borrowed from other Cray systems. Eldorado retains the programming model, operating system, and tools of the MTA-2. It has the same capability as the MTA-2 to tolerate latencies and achieve high performance on programs that run poorly on SMP clusters. We present several programming examples to illustrate performance and scalability in the presence of high memory and synchronization latencies.
This paper describes the scheduling issues specic to the Tera MTA high performance shared memory ... more This paper describes the scheduling issues specic to the Tera MTA high performance shared memory multithreaded multiprocessor and presents solutions to classic scheduling problems. The Tera MTA exploits parallelism at all levels, from ne-grained instruction-level parallelism within a single processor to parallel programming across processors, to multiprogramming among several applications simultaneously. Consequently, scheduling of resources occurs at many levels, and managing these resources poses unique and challenging scheduling concerns. This paper outlines the scheduling algorithms of the user level runtime and operating system and describes the issues relevant to each. Many of the issues encountered and solutions proposed are novel, given the multithreaded, multiprogrammed nature of our architecture. In particular, we present an algorithm for swapping a set of tasks to and from memory that achieves minimal overhead, largely independent of the order in which tasks are swapped.
Proceedings of the 1997 ACM/IEEE conference on Supercomputing (CDROM) - Supercomputing '97, 1997
The development o f T era's MTA system was unusual. It respected the need for fast hardware and l... more The development o f T era's MTA system was unusual. It respected the need for fast hardware and large shared memory , facilitating execution of the most demanding parallel application programs. But at the same time, it met the need for a clean mac hine model enabling calculated compiler optimizations and easy programming and the need for no vel architectural features necessary to support fast parallel system software. From its inception, system and application needs have molded the MTA architecture. The result is a system that o ers high performance and ease of programming b y virtue not only of fast physical hardware and at shared memory , but also of the streamlined software systems that well utilize the features of the architecture intended to support them.
ABSTRACT We develop a series of quicksort algorithms for the Sequent Symmetry shared memory paral... more ABSTRACT We develop a series of quicksort algorithms for the Sequent Symmetry shared memory parallel computer. By employing a novel yet simple parallel splitting algorithm and dynamic scheduling we are able to achieve a speedup of 13 with 16 processors over the performance of sequential quicksort on one processor. This work provides experimental evidence that asynchronous algorithms’ more uniform usage of shared resources may make them less susceptible to bottlenecks on real machines.
IEEE Transactions on Pattern Analysis and Machine Intelligence, 1987
We describe the current state of a system that recognizes printed text of various fonts and sizes... more We describe the current state of a system that recognizes printed text of various fonts and sizes for the Roman alphabet. The system combines several techniques in order to improve the overall recognition rate. Thinning and shape extraction are performed directly on a graph of the run-leiigth encoding of a binary image. The resulting strokes and other shapes are mapped, using a shape-clustering approach, into binary features which are then fed into a statistical Bayesian classifier. Large-scale trials have shown better than 97 percent top choice correct performance on mixtures of six dissimilar fonts, and over 99 percent on most single fonts, over a range of point sizes. Certain remaining confusion classes are disambiguated through contour analysis, and characters suspected of being merged are broken aiid reclassified. Finally, layout and linguistic context are applied. The results are illustrated by sample pages.
USENIX conference on Hot topics in parallelism, May 26, 2011
Crunching large graphs is the basis of many emerging applications, such as social network analysi... more Crunching large graphs is the basis of many emerging applications, such as social network analysis and bioinformatics. Graph analytics algorithms exhibit little locality and therefore present significant performance challenges. Hardware multithreading systems (e.g., Cray XMT) show that with enough concurrency, we can tolerate long latencies. Unfortunately, this solution is not available with commodity parts. Our goal is to develop a latency-tolerant system built out of commodity parts and mostly in software. The proposed system includes a runtime that supports a large number of lightweight contexts, full-bit synchronization and a memory manager that provides a high-latency but high-bandwidth global shared memory. This paper lays out the vision for our system and justifies its feasibility with a performance analysis of the runtime for latency tolerance.
IEEE Transactions on Pattern Analysis and Machine Intelligence, Mar 1, 1987
We describe the current state of a system that recognizes printed text of various fonts and sizes... more We describe the current state of a system that recognizes printed text of various fonts and sizes for the Roman alphabet. The system combines several techniques in order to improve the overall recognition rate. Thinning and shape extraction are performed directly on a graph of the run-leiigth encoding of a binary image. The resulting strokes and other shapes are mapped, using a shape-clustering approach, into binary features which are then fed into a statistical Bayesian classifier. Large-scale trials have shown better than 97 percent top choice correct performance on mixtures of six dissimilar fonts, and over 99 percent on most single fonts, over a range of point sizes. Certain remaining confusion classes are disambiguated through contour analysis, and characters suspected of being merged are broken aiid reclassified. Finally, layout and linguistic context are applied. The results are illustrated by sample pages.
Motivation: Biological system behaviors are often the outcome of complex interactions among a lar... more Motivation: Biological system behaviors are often the outcome of complex interactions among a large number of cells and their biotic and abiotic environment. Computational biologists attempt to understand, predict and manipulate biological system behavior through mathematical modeling and computer simulation. Discrete agentbased modeling (in combination with high-resolution grids to model the extracellular environment) is a popular approach for building biological system models. However, the computational complexity of this approach forces computational biologists to resort to coarser resolution approaches to simulate large biological systems. Highperformance parallel computers have the potential to address the computing challenge, but writing efficient software for parallel computers is difficult and time-consuming. Results: We have developed Biocellion, a high-performance software framework, to solve this computing challenge using parallel computers. To support a wide range of multicellular biological system models, Biocellion asks users to provide their model specifics by filling the function body of pre-defined model routines. Using Biocellion, modelers without parallel computing expertise can efficiently exploit parallel computers with less effort than writing sequential programs from scratch. We simulate cell sorting, microbial patterning and a bacterial system in soil aggregate as case studies. Availability and implementation: Biocellion runs on x86 compatible systems with the 64 bit Linux operating system and is freely available for academic use. Visit http://biocellion.com for additional information.
Preston Briggs is a Senior Engineer at Reservoir Labs and an Affiliate Professor in Computer Scie... more Preston Briggs is a Senior Engineer at Reservoir Labs and an Affiliate Professor in Computer Science and Engineering at the University of Washington. He received a PhD in computer science from Rice University in 1992. [email protected] The rising importance of data-intensive applications has fueled the growth of a plethora of distributed computing frameworks, including Hadoop, Spark, and GraphLab. We have developed a system called Grappa [1, 2] to aid programmers in developing new frameworks. Grappa provides a distributed shared memory abstraction to hide complexity from the programmer, and takes advantage of parallelism in the data to hide remote access latency and to trade latency for more performance. These techniques allow it to outperform existing frameworks by up to an order of magnitude.
Previous theories on computing functions of moving data have assumed either that motion is predet... more Previous theories on computing functions of moving data have assumed either that motion is predetermined or that information about it is provided on-line: changes to data values are immediately available to the computational device. As a consequence, the models associated with these theories neglect data acquisition costs. In many computer application problems, data acquisition costs are comparable to, or may even surpass, those of computation. Lacking an applicable computational theory, these problems have been solved in the past by ad hoc methods. This work identifies and studies the general class of Data in Motion problems: those requiring the repeated computation of a function of data following arbitrary motion and having significant acquisition costs. The thesis statement is that data acquisition costs can be reduced by using old data, acquired when computing the function previously, to determine which current data values to obtain. For the purpose of studying the limitations o...
We develop a series of quicksort algorithms for the Sequent Symmetry shared memory parallel compu... more We develop a series of quicksort algorithms for the Sequent Symmetry shared memory parallel computer. By employing a novel yet simple parallel splitting algorithm and dynamic scheduling we are able to achieve a speedup of 13 with 16 processors over the performance of sequential quicksort on one processor. This work provides experimental evidence that asynchronous algorithms’ more uniform usage of shared resources may make them less susceptible to bottlenecks on real machines. Introduction: On sequential processors, Quicksort is one of the most e cient algorithms for sorting large arrays of data [Hoa62]. Three factors are eminently responsible for its speed: locality of memory references, a tight inner loop, and, on average, a small number of comparisons. Locality ensures both that cache prefetching can be exploited and that paging is minimal. Because a high proportion of the inner loop operations are comparisons, the computational overhead per comparison is small. Even though some o...
The broad environmental, societal and animal welfare issues associated with large-scale animal pr... more The broad environmental, societal and animal welfare issues associated with large-scale animal protein production are well-documented, and cultivated meat represents a potentially more sustainable alternative protein form to conventional production methods. Some believe cultivated meat is years away from commercial success; however, computational modeling has real potential to reduce the timeline for commercial roll-out. In June, 2019, a diverse group of stakeholders attended the inaugural Cultivated Meat Modeling Consortium meeting in Seattle, Washington to develop a multiscale modeling framework for cultivated meat manufacturing. This whitepaper was created from the extensive brainstorming that occurred during the meeting and afterwards. The early stage framework presented here is meant only as a beginning, and our hope is that this paper will drive future discussions and generate more collaborations that maximize the utility of computational modeling in the areas outlined here and beyond.
Skin is our primary barrier to the outside world, protecting us from physical, biological and che... more Skin is our primary barrier to the outside world, protecting us from physical, biological and chemical threats. Developing innovative products that preserve and improve skin barrier function requires a thorough understanding of the mechanisms underlying barrier response to topical applications. In many fields, computer simulations already facilitate understanding, thus accelerating innovation. Simulations of software models allow scientists to test hypothesized mechanisms by comparing predicted results to physical observations. They also enable virtual product optimization, without physical experiments, once mechanisms have been validated. The physical accessibility and abundant knowledge of skin structure makes it a prime candidate for computational modeling. In this article, we describe a computational multiscale multicellular skin model used to simulate growth and response of the epidermal barrier. The model integrates several modeling styles and mathematical frameworks including...
This paper describes the processor scheduling issues specific to the Tera MTA (Multi Threaded Arc... more This paper describes the processor scheduling issues specific to the Tera MTA (Multi Threaded Architecture) computer system and presents solutions to classic scheduling problems. The Tera MTA exploits parallelism at all levels, from fine-grained instruction-level parallelism within a single processor to parallel programming across processors, to multiprogramming among several applications simultaneously. Consequently, processor scheduling occurs at many levels, and managing these levels poses unique and challenging scheduling concerns. We describe the processor scheduling algorithms of the user level runtime and operating system and describe the issues relevant to each. Many of the issues encountered and solutions proposed are novel, given the multithreaded, multiprogrammed nature of our architecture.
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming, 2006
While the high-performance computing world is dominated by distributed memory computer systems, a... more While the high-performance computing world is dominated by distributed memory computer systems, applications that require random access into large shared data structures continue to motivate development of ever larger shared-memory parallel computers such as Cray's MTA and SGI's Altix systems. To support scalable application performance on such architectures, the memory allocator must be able to satisfy requests at a rate proportional to system size. For example, a 40 processor Cray MTA-2 can experience over 5000 concurrent requests, one from each of its 128 streams per processor. Cray's Eldorado, to be built upon the same network as Sandia's 10,000 processor Red Storm system, will sport thousands of multithreaded processors leading to hundreds of thousands of concurrent requests. In this paper, we present MAMA, a scalable shared-memory allocator designed to service any rate of concurrent requests. MAMA is distinguished from prior work on shared-memory allocators in that it employs software combining to aggregate requests serviced by a single heap structure: Hoard and MTA malloc necessitate repetition of the underlying heap data structures in proportion to processor count. Unlike Hoard, MAMA does not exploit processorlocal data structures, limiting its applicability today to systems that sustain high utilization in the presence of global references such as Cray's MTA systems. We believe MAMA's relevance to other shared-memory systems will grow as they become increasingly multithreaded and, consequently, more tolerant of references to non-local memory. We show not only that MAMA scales on Cray MTA systems, but also that it delivers absolute performance competitive with allocators employing heap repetition. In addition, we demonstrate that performance of repetition-based allocators does not scale under heavy loads. We also argue more generally that methods using repetition alone to support concurrency are subject to an impractical tradeoff of scalability against space consumption: when scaled up to meet increasing concurrency demands, repetition-based allocators necessarily house unused space p 2 quadratic in the number of processors p. Hierarchical structure may reduce this to p log p, but in building large-scale shared-memory parallel computers, unused memory more than linear in p is unacceptable. MAMA, in con-Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee.
Programs that simulate complex-structure deformation scale poorly on most vector multiprocessors ... more Programs that simulate complex-structure deformation scale poorly on most vector multiprocessors and MPPs. The authors worked on an alternative architecture-the Tera MTA-and tested performance results for a model crash problem using LS-DYNA code
Large-scale parallel discrete event simulations of massive networks, such as the Internet, are &q... more Large-scale parallel discrete event simulations of massive networks, such as the Internet, are "Grand Challenge" problems: packet level simulation of even a small fraction of the Internet would consume the resources of the most powerful computers available. We reimplement the SSF scalable simulation framework so we can run large-scale network simulations originally written for DaSSF. Our implementation, CraySSF, is designed for the Cray-MTA, a multithreaded supercomputer architecture developed specifically to address large-scale computations of the kind that are not easily distributed. We describe the architecture, implementation issues, and preliminary performance results on a variety of (stock) serial and parallel architectures.
Proceedings of the 2nd conference on Computing frontiers, 2005
This paper introduces Eldorado, a third generation multithreaded architecture. Previous Cray mult... more This paper introduces Eldorado, a third generation multithreaded architecture. Previous Cray multithreaded systems were plagued by unreliable hardware and high costs. Eldorado corrects these problems by using many parts built for other commercial systems. Its compute processor is a 500 MHZ multithreaded processor architecturally similar to the MTA-2 processor; but its interconnection network, I/O subsystem, and service processors are borrowed from other Cray systems. Eldorado retains the programming model, operating system, and tools of the MTA-2. It has the same capability as the MTA-2 to tolerate latencies and achieve high performance on programs that run poorly on SMP clusters. We present several programming examples to illustrate performance and scalability in the presence of high memory and synchronization latencies.
This paper describes the scheduling issues specic to the Tera MTA high performance shared memory ... more This paper describes the scheduling issues specic to the Tera MTA high performance shared memory multithreaded multiprocessor and presents solutions to classic scheduling problems. The Tera MTA exploits parallelism at all levels, from ne-grained instruction-level parallelism within a single processor to parallel programming across processors, to multiprogramming among several applications simultaneously. Consequently, scheduling of resources occurs at many levels, and managing these resources poses unique and challenging scheduling concerns. This paper outlines the scheduling algorithms of the user level runtime and operating system and describes the issues relevant to each. Many of the issues encountered and solutions proposed are novel, given the multithreaded, multiprogrammed nature of our architecture. In particular, we present an algorithm for swapping a set of tasks to and from memory that achieves minimal overhead, largely independent of the order in which tasks are swapped.
Proceedings of the 1997 ACM/IEEE conference on Supercomputing (CDROM) - Supercomputing '97, 1997
The development o f T era's MTA system was unusual. It respected the need for fast hardware and l... more The development o f T era's MTA system was unusual. It respected the need for fast hardware and large shared memory , facilitating execution of the most demanding parallel application programs. But at the same time, it met the need for a clean mac hine model enabling calculated compiler optimizations and easy programming and the need for no vel architectural features necessary to support fast parallel system software. From its inception, system and application needs have molded the MTA architecture. The result is a system that o ers high performance and ease of programming b y virtue not only of fast physical hardware and at shared memory , but also of the streamlined software systems that well utilize the features of the architecture intended to support them.
ABSTRACT We develop a series of quicksort algorithms for the Sequent Symmetry shared memory paral... more ABSTRACT We develop a series of quicksort algorithms for the Sequent Symmetry shared memory parallel computer. By employing a novel yet simple parallel splitting algorithm and dynamic scheduling we are able to achieve a speedup of 13 with 16 processors over the performance of sequential quicksort on one processor. This work provides experimental evidence that asynchronous algorithms’ more uniform usage of shared resources may make them less susceptible to bottlenecks on real machines.
IEEE Transactions on Pattern Analysis and Machine Intelligence, 1987
We describe the current state of a system that recognizes printed text of various fonts and sizes... more We describe the current state of a system that recognizes printed text of various fonts and sizes for the Roman alphabet. The system combines several techniques in order to improve the overall recognition rate. Thinning and shape extraction are performed directly on a graph of the run-leiigth encoding of a binary image. The resulting strokes and other shapes are mapped, using a shape-clustering approach, into binary features which are then fed into a statistical Bayesian classifier. Large-scale trials have shown better than 97 percent top choice correct performance on mixtures of six dissimilar fonts, and over 99 percent on most single fonts, over a range of point sizes. Certain remaining confusion classes are disambiguated through contour analysis, and characters suspected of being merged are broken aiid reclassified. Finally, layout and linguistic context are applied. The results are illustrated by sample pages.
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