... Using FPGA Devices Anitha R.1 * Assistant Professor, SENSE, VIT University, Vellore - 632014,... more ... Using FPGA Devices Anitha R.1 * Assistant Professor, SENSE, VIT University, Vellore - 632014, Tamil Nadu, India. [email protected] +91-9994700025 Bagyaveereswaran V.2 Assistant Professor (Sr), SELECT, VIT University, Vellore - 632014, Tamil Nadu, India. ...
2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015], 2015
The Vedic Multiplier and the Reversible Logic Gates has Designed and implemented in the multiply ... more The Vedic Multiplier and the Reversible Logic Gates has Designed and implemented in the multiply and Accumulate Unit (MAC) and that is shown in this paper. A Vedic multiplier is designed by using Urdhava Triyagbhayam sutra and the adder design is done by using reversible logic gate. Reversible logics are also the fundamental requirement for the emerging field of Quantum computing. The Vedic multiplier is used for the multiplication unit so as to reduce partial products and to get high performance and lesser area .The reversible logic is used to get less power. The MAC is designed in Verilog HDL and the simulation is done in Xilinx 14.2 and synthesis is done using Xilinx. The chip design for the proposed MAC is also carried out.
International Journal of VLSI Design & Communication Systems, Sep 30, 2011
The developing an Application Specific Integrated Circuits (ASICs) will cost very high, the circu... more The developing an Application Specific Integrated Circuits (ASICs) will cost very high, the circuits should be proved and then it would be optimized before implementation. Multiplication which is the basic building block for several DSP processors, Image processing and many other. The Braun multipliers can easily be implemented using Field Programmable Gate Array (FPGA) devices. This research presented the comparative study of Spartan-3E, Virtex-4, Virtex-5 and Virtex-6 Low Power FPGA devices. The implementation of Braun multipliers and its bypassing techniques is done using Verilog HDL. We are proposing that adder block which we implemented our design (fast addition) and we compared the results of that so that our proposed method is effective when compare to the conventional design. There is the reduction in the resources like delay LUTs, number of slices used. Results are showed and it is verified using the Spartan-3E, Virtex-4 and Virtex-5 devices. The Virtex-5 FPGA has shown the good performance as compared to Spartan-3E and Virtex-4 FPGA devices.
International Journal of VLSI Design & Communication Systems, Sep 30, 2011
The developing an Application Specific Integrated Circuits (ASICs) will cost very high, the circu... more The developing an Application Specific Integrated Circuits (ASICs) will cost very high, the circuits should be proved and then it would be optimized before implementation. Multiplication which is the basic building block for several DSP processors, Image processing and many other. The Braun multipliers can easily be implemented using Field Programmable Gate Array (FPGA) devices. This research presented the comparative study of Spartan-3E, Virtex-4, Virtex-5 and Virtex-6 Low Power FPGA devices. The implementation of Braun multipliers and its bypassing techniques is done using Verilog HDL. We are proposing that adder block which we implemented our design (fast addition) and we compared the results of that so that our proposed method is effective when compare to the conventional design. There is the reduction in the resources like delay LUTs, number of slices used. Results are showed and it is verified using the Spartan-3E, Virtex-4 and Virtex-5 devices. The Virtex-5 FPGA has shown the good performance as compared to Spartan-3E and Virtex-4 FPGA devices.
The major building blocks in Digital Signal
Processing (DSP) applications like FIR filters, Fast ... more The major building blocks in Digital Signal Processing (DSP) applications like FIR filters, Fast Fourier Transform (FFT), Squaring and Cubing circuits etc. are the multipliers. In all the DSP applications which use multipliers, multipliers consume most of the power. Hence, there is a need to develop to low-power multipliers. In this paper, various bypassing techniques such as Row Bypassing, Column Bypassing, Two-dimensional Bypassing, Row and Column Bypassing and Low cost Bypassing techniques have been applied to a signed array multiplier such as Baugh Wooley Multiplier and comparison among them have been made. These bypassing techniques will reduce the switching activity, thus the dynamic power and hence the total power will be reduced. A comparative study is presented in this paper among 4x4, 8x8, 16x16 and 32x32 Baugh Wooley Multipliers and its architectural modifications. The delay of the multipliers can be reduced by replacing the Ripple carry adder in the last stage of multipliers with fast adders like Carry Look ahead adder and Kogge stone adder. Verilog HDL is used to code all the designs. All the multiplier designs are simulated and synthesized using Xilinx ISE 13.2 simulator for different FPGA families like Spartan-3E, Virtex-4, Virtex-5 and Virtex-6 Lower Power and a comparison is made for different FPGA devices and also synthesized using RTL Compiler from Cadence in 90nm technology.
In this work we have designed the Wallace tree multiplier at transistor level. In
most of the mul... more In this work we have designed the Wallace tree multiplier at transistor level. In most of the multipliers XOR gate is a key component. The optimization is done at gate level by using the 6T XOR gate instead of conventional CMOS gate. A power gating technique is also used to reduce the leakage power in the design. The simulation was carried out in CADENCE virtuoso with 90nm technology. And the result showed a reduction in area and power of the multiplier.
The Vedic Multiplier and the Reversible Logic
Gates has Designed and implemented in the multiply ... more The Vedic Multiplier and the Reversible Logic Gates has Designed and implemented in the multiply and Accumulate Unit (MAC) and that is shown in this paper. A Vedic multiplier is designed by using Urdhava Triyagbhayam sutra and the adder design is done by using reversible logic gate. Reversible logics are also the fundamental requirement for the emerging field of Quantum computing. The Vedic multiplier is used for the multiplication unit so as to reduce partial products and to get high performance and lesser area .The reversible logic is used to get less power. The MAC is designed in Verilog HDL and the simulation is done in Modelsim, Xilinx 14.2 and synthesis is done in both RTL compiler using cadence as well as Xilinx. The chip design for the proposed MAC is also carried out.
The developing an Application Specific Integrated Circuits (ASICs) will cost very high, the circu... more The developing an Application Specific Integrated Circuits (ASICs) will cost very high, the circuits should be proved and then it would be optimized before implementation. Multiplication which is the basic building block for several DSP processors, Image processing and many other. The Braun multipliers can easily be implemented using Field Programmable Gate Array (FPGA) devices. This research presented the comparative study of Spartan-3E, Virtex-4, Virtex-5 and Virtex-6 Low Power FPGA devices. The implementation of Braun multipliers and its bypassing techniques is done using Verilog HDL. We are proposing that adder block which we implemented our design (fast addition) and we compared the results of that so that our proposed method is effective when compare to the conventional design. There is the reduction in the resources like delay LUTs, number of slices used. Results are showed and it is verified using the Spartan-3E, Virtex-4 and Virtex-5 devices. The Virtex-5 FPGA has shown the good performance as compared to Spartan-3E and Virtex-4 FPGA devices.
... Using FPGA Devices Anitha R.1 * Assistant Professor, SENSE, VIT University, Vellore - 632014,... more ... Using FPGA Devices Anitha R.1 * Assistant Professor, SENSE, VIT University, Vellore - 632014, Tamil Nadu, India. [email protected] +91-9994700025 Bagyaveereswaran V.2 Assistant Professor (Sr), SELECT, VIT University, Vellore - 632014, Tamil Nadu, India. ...
2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015], 2015
The Vedic Multiplier and the Reversible Logic Gates has Designed and implemented in the multiply ... more The Vedic Multiplier and the Reversible Logic Gates has Designed and implemented in the multiply and Accumulate Unit (MAC) and that is shown in this paper. A Vedic multiplier is designed by using Urdhava Triyagbhayam sutra and the adder design is done by using reversible logic gate. Reversible logics are also the fundamental requirement for the emerging field of Quantum computing. The Vedic multiplier is used for the multiplication unit so as to reduce partial products and to get high performance and lesser area .The reversible logic is used to get less power. The MAC is designed in Verilog HDL and the simulation is done in Xilinx 14.2 and synthesis is done using Xilinx. The chip design for the proposed MAC is also carried out.
International Journal of VLSI Design & Communication Systems, Sep 30, 2011
The developing an Application Specific Integrated Circuits (ASICs) will cost very high, the circu... more The developing an Application Specific Integrated Circuits (ASICs) will cost very high, the circuits should be proved and then it would be optimized before implementation. Multiplication which is the basic building block for several DSP processors, Image processing and many other. The Braun multipliers can easily be implemented using Field Programmable Gate Array (FPGA) devices. This research presented the comparative study of Spartan-3E, Virtex-4, Virtex-5 and Virtex-6 Low Power FPGA devices. The implementation of Braun multipliers and its bypassing techniques is done using Verilog HDL. We are proposing that adder block which we implemented our design (fast addition) and we compared the results of that so that our proposed method is effective when compare to the conventional design. There is the reduction in the resources like delay LUTs, number of slices used. Results are showed and it is verified using the Spartan-3E, Virtex-4 and Virtex-5 devices. The Virtex-5 FPGA has shown the good performance as compared to Spartan-3E and Virtex-4 FPGA devices.
International Journal of VLSI Design & Communication Systems, Sep 30, 2011
The developing an Application Specific Integrated Circuits (ASICs) will cost very high, the circu... more The developing an Application Specific Integrated Circuits (ASICs) will cost very high, the circuits should be proved and then it would be optimized before implementation. Multiplication which is the basic building block for several DSP processors, Image processing and many other. The Braun multipliers can easily be implemented using Field Programmable Gate Array (FPGA) devices. This research presented the comparative study of Spartan-3E, Virtex-4, Virtex-5 and Virtex-6 Low Power FPGA devices. The implementation of Braun multipliers and its bypassing techniques is done using Verilog HDL. We are proposing that adder block which we implemented our design (fast addition) and we compared the results of that so that our proposed method is effective when compare to the conventional design. There is the reduction in the resources like delay LUTs, number of slices used. Results are showed and it is verified using the Spartan-3E, Virtex-4 and Virtex-5 devices. The Virtex-5 FPGA has shown the good performance as compared to Spartan-3E and Virtex-4 FPGA devices.
The major building blocks in Digital Signal
Processing (DSP) applications like FIR filters, Fast ... more The major building blocks in Digital Signal Processing (DSP) applications like FIR filters, Fast Fourier Transform (FFT), Squaring and Cubing circuits etc. are the multipliers. In all the DSP applications which use multipliers, multipliers consume most of the power. Hence, there is a need to develop to low-power multipliers. In this paper, various bypassing techniques such as Row Bypassing, Column Bypassing, Two-dimensional Bypassing, Row and Column Bypassing and Low cost Bypassing techniques have been applied to a signed array multiplier such as Baugh Wooley Multiplier and comparison among them have been made. These bypassing techniques will reduce the switching activity, thus the dynamic power and hence the total power will be reduced. A comparative study is presented in this paper among 4x4, 8x8, 16x16 and 32x32 Baugh Wooley Multipliers and its architectural modifications. The delay of the multipliers can be reduced by replacing the Ripple carry adder in the last stage of multipliers with fast adders like Carry Look ahead adder and Kogge stone adder. Verilog HDL is used to code all the designs. All the multiplier designs are simulated and synthesized using Xilinx ISE 13.2 simulator for different FPGA families like Spartan-3E, Virtex-4, Virtex-5 and Virtex-6 Lower Power and a comparison is made for different FPGA devices and also synthesized using RTL Compiler from Cadence in 90nm technology.
In this work we have designed the Wallace tree multiplier at transistor level. In
most of the mul... more In this work we have designed the Wallace tree multiplier at transistor level. In most of the multipliers XOR gate is a key component. The optimization is done at gate level by using the 6T XOR gate instead of conventional CMOS gate. A power gating technique is also used to reduce the leakage power in the design. The simulation was carried out in CADENCE virtuoso with 90nm technology. And the result showed a reduction in area and power of the multiplier.
The Vedic Multiplier and the Reversible Logic
Gates has Designed and implemented in the multiply ... more The Vedic Multiplier and the Reversible Logic Gates has Designed and implemented in the multiply and Accumulate Unit (MAC) and that is shown in this paper. A Vedic multiplier is designed by using Urdhava Triyagbhayam sutra and the adder design is done by using reversible logic gate. Reversible logics are also the fundamental requirement for the emerging field of Quantum computing. The Vedic multiplier is used for the multiplication unit so as to reduce partial products and to get high performance and lesser area .The reversible logic is used to get less power. The MAC is designed in Verilog HDL and the simulation is done in Modelsim, Xilinx 14.2 and synthesis is done in both RTL compiler using cadence as well as Xilinx. The chip design for the proposed MAC is also carried out.
The developing an Application Specific Integrated Circuits (ASICs) will cost very high, the circu... more The developing an Application Specific Integrated Circuits (ASICs) will cost very high, the circuits should be proved and then it would be optimized before implementation. Multiplication which is the basic building block for several DSP processors, Image processing and many other. The Braun multipliers can easily be implemented using Field Programmable Gate Array (FPGA) devices. This research presented the comparative study of Spartan-3E, Virtex-4, Virtex-5 and Virtex-6 Low Power FPGA devices. The implementation of Braun multipliers and its bypassing techniques is done using Verilog HDL. We are proposing that adder block which we implemented our design (fast addition) and we compared the results of that so that our proposed method is effective when compare to the conventional design. There is the reduction in the resources like delay LUTs, number of slices used. Results are showed and it is verified using the Spartan-3E, Virtex-4 and Virtex-5 devices. The Virtex-5 FPGA has shown the good performance as compared to Spartan-3E and Virtex-4 FPGA devices.
Uploads
Papers by Anitha Ravi
Processing (DSP) applications like FIR filters, Fast Fourier
Transform (FFT), Squaring and Cubing circuits etc. are
the multipliers. In all the DSP applications which use
multipliers, multipliers consume most of the power. Hence,
there is a need to develop to low-power multipliers. In this
paper, various bypassing techniques such as Row
Bypassing, Column Bypassing, Two-dimensional
Bypassing, Row and Column Bypassing and Low cost
Bypassing techniques have been applied to a signed array
multiplier such as Baugh Wooley Multiplier and
comparison among them have been made. These bypassing
techniques will reduce the switching activity, thus the
dynamic power and hence the total power will be reduced.
A comparative study is presented in this paper among 4x4,
8x8, 16x16 and 32x32 Baugh Wooley Multipliers and its
architectural modifications. The delay of the multipliers
can be reduced by replacing the Ripple carry adder in the
last stage of multipliers with fast adders like Carry Look
ahead adder and Kogge stone adder. Verilog HDL is used
to code all the designs. All the multiplier designs are
simulated and synthesized using Xilinx ISE 13.2 simulator
for different FPGA families like Spartan-3E, Virtex-4,
Virtex-5 and Virtex-6 Lower Power and a comparison is
made for different FPGA devices and also synthesized
using RTL Compiler from Cadence in 90nm technology.
most of the multipliers XOR gate is a key component. The optimization is
done at gate level by using the 6T XOR gate instead of conventional CMOS
gate. A power gating technique is also used to reduce the leakage power in the
design. The simulation was carried out in CADENCE virtuoso with 90nm
technology. And the result showed a reduction in area and power of the
multiplier.
Gates has Designed and implemented in the multiply and
Accumulate Unit (MAC) and that is shown in this paper. A Vedic
multiplier is designed by using Urdhava Triyagbhayam sutra and
the adder design is done by using reversible logic gate. Reversible
logics are also the fundamental requirement for the emerging
field of Quantum computing. The Vedic multiplier is used for the
multiplication unit so as to reduce partial products and to get
high performance and lesser area .The reversible logic is used to
get less power. The MAC is designed in Verilog HDL and the
simulation is done in Modelsim, Xilinx 14.2 and synthesis is done
in both RTL compiler using cadence as well as Xilinx. The chip
design for the proposed MAC is also carried out.
Processing (DSP) applications like FIR filters, Fast Fourier
Transform (FFT), Squaring and Cubing circuits etc. are
the multipliers. In all the DSP applications which use
multipliers, multipliers consume most of the power. Hence,
there is a need to develop to low-power multipliers. In this
paper, various bypassing techniques such as Row
Bypassing, Column Bypassing, Two-dimensional
Bypassing, Row and Column Bypassing and Low cost
Bypassing techniques have been applied to a signed array
multiplier such as Baugh Wooley Multiplier and
comparison among them have been made. These bypassing
techniques will reduce the switching activity, thus the
dynamic power and hence the total power will be reduced.
A comparative study is presented in this paper among 4x4,
8x8, 16x16 and 32x32 Baugh Wooley Multipliers and its
architectural modifications. The delay of the multipliers
can be reduced by replacing the Ripple carry adder in the
last stage of multipliers with fast adders like Carry Look
ahead adder and Kogge stone adder. Verilog HDL is used
to code all the designs. All the multiplier designs are
simulated and synthesized using Xilinx ISE 13.2 simulator
for different FPGA families like Spartan-3E, Virtex-4,
Virtex-5 and Virtex-6 Lower Power and a comparison is
made for different FPGA devices and also synthesized
using RTL Compiler from Cadence in 90nm technology.
most of the multipliers XOR gate is a key component. The optimization is
done at gate level by using the 6T XOR gate instead of conventional CMOS
gate. A power gating technique is also used to reduce the leakage power in the
design. The simulation was carried out in CADENCE virtuoso with 90nm
technology. And the result showed a reduction in area and power of the
multiplier.
Gates has Designed and implemented in the multiply and
Accumulate Unit (MAC) and that is shown in this paper. A Vedic
multiplier is designed by using Urdhava Triyagbhayam sutra and
the adder design is done by using reversible logic gate. Reversible
logics are also the fundamental requirement for the emerging
field of Quantum computing. The Vedic multiplier is used for the
multiplication unit so as to reduce partial products and to get
high performance and lesser area .The reversible logic is used to
get less power. The MAC is designed in Verilog HDL and the
simulation is done in Modelsim, Xilinx 14.2 and synthesis is done
in both RTL compiler using cadence as well as Xilinx. The chip
design for the proposed MAC is also carried out.