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Venkata Sudhakar C.

Sree Vidyanikethan Engineering College, Electronics and Communications Engineering, Faculty Member

Sri Venkateswara University, Electronics & Communication, Faculty Member

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Dr. C.V.Sudhakar has been working as an Assistant Professor, Department of Electronics and Communication Engineering, Mohan Babu University (Erstwhile Sree Vidyanikethan Engineering College), Tirupati, Andhra Pradesh, India. He has 14 years of Teaching experience. His areas of interests are Machine Learning, Deep Learning, Signal and Image processing and VLSI Design. He has been awarded with Ph.D. degree in Department of Electronics and Communication Engineering, Sri Venkateswara University College of Engineering, Sri Venkateswara University, Tirupati, Andhra Pradesh, in 2024. He did M.Tech., in the specialization of Digital Systems and Computer Electronics in J.N.T.U.H. Kukatpally, JNTUH, Hyderabad, Telangana, India, in 2010. He Received B.Tech., Degree in Electronic Instrumentation and Control Engineering from Sri Venkateswara University, Tirupati, Andhra Pradesh, India, in 2006. He published several papers in reputed national and international journals with high impact factor. He attended and presented many research papers in various National and International conferences. He is a member in ISTE, IETE. He received international Academic Excellence Award in 2024 from International Institute of Organized Research (I2OR) India. He guided number of B.Tech students in their project work. He has been giving research guidance to M.Tech., students.
Phone: +91 6303257763
Address: Tirupati-517102, Andhra Pradesh, India

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University of Turku

Chitkara University

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Wawasan Open University

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Papers by Venkata Sudhakar C.

A Low-Noise AC coupled Instrumentation Amplifier for Recording Bio Signals

The human body is the source of many kinds of signals. These signals are called as bio signals. T... more The human body is the source of many kinds of signals. These signals are called as bio signals. These signals can be measured by placing an electrode in contact with the human body. These signals will be in the range of few mille volts and also the electrode will induce dc offset to the measured signals. These bio signals should be amplified for further analysis in biomedical applications. The bio signals will amplify by AC coupled instrumentation amplifier. The dc offset also suppressed by the AC coupled instrumentation amplifier. An AC coupled instrumentation amplifier is presented in this paper with low input interfered noise of ~20 and gain of 65 dB and CMRR of 142 dB with the total power consumption of 104pW.

DESIGN AND SYNTHESIS OF COMBINATIONAL CIRCUITS USING REVERSIBLE LOGIC

Reversible logic has become one of the recent emerging research pursuits contributing to the fiel... more Reversible logic has become one of the recent emerging research pursuits contributing to the field of low power dissipating circuit design in the past few years. Reversible logic find its owns applications in various fields which include quantum computing, nanotechnology, digital signal and image processing, optical computing, Low power VLSI etc., Decoders are one of the maximum essential circuit utilized in combinational logic. The whole design of combinational circuits like decoders, comparator, full adder, multiplexer are designed using Fredkin gate, CNOT, Peres gate and R-I gate which give better quantum cost when compared to other Reversible gates. The quantum cost and garbage outputs for combinational circuits in proposed designed has been compared with a previously existing design. The reversible logic circuits are designed and implemented using VHDL code and the simulation results are obtained in Xilinx ISE version 14.7.

A NOVEL DESIGN OF CSD RECODING WITH FAULT TOLERANT FULL ADDER

Canonic signed digit (CSD) involves very few non-zero bits, designing it for high speed and area ... more Canonic signed digit (CSD) involves very few non-zero bits, designing it for high speed and area optimization in VLSI based DSP architectures. The CSD has been designed with number of adders. Because of faults like struck at faults present in the adders during its operation, there may be a deviation in the expected results. It is very difficult to detect these faults in offline. So that, We proposed CSD with Fault tolerant Full Adder. The ordinary full adder performs addition of bits, but it is not able to detect and correct whenever the faults occurred during the operation. The proposed Fault tolerant Full Adder in CSD play important role to detect the faults with their exact location and also tolerate the faults. In this paper, we present high speed, FPGA fabric aware pipelined architectures for CSD recoding circuits using fault tolerant Full Adder starting from a two's complement number to redundant signed digit input.

An Extensive Projection to Create an Efficient Clock Specifications Based on Design Rule Violation Constraints

With shrinking technology nodes, the demand of more speed (frequency) and use of ultra-low power ... more With shrinking technology nodes, the demand of more speed (frequency) and use of ultra-low power has been increased. While trying to work on this we are forgetting that number of functionalities in a single chip is also increasing. To meet the market demand and pressure number of gates has been significantly increased on a single chip. The impact of crosstalk and SI delay increases as we move lower in technology nodes. Extra precautions need to be taken care in each stage of Physical Design(PD). Here Clock Tree Synthesis (CTS) plays a major role. For the CTS we need to give specification show to build clock tree to meet transition, latency and skew requirements. These spec generations depends upon timing constraints (SDC) as well as DRV constraints. Furthermore, I am proposing clock spec generation flow that will consider exception also and I will see how to fix DRV constraints effectively by manipulating the no. of buffers used. So it will control area being used as well as power for no. of chips. In this proposed method, to meet these constraints I will use TCL Scripting and IC Compiler to get the clear Clock specifications.

In situ measurement and management of soil, air, noise and water pollution in and around the Limestone mining area of Yerraguntla, YSR kadapa, Andhra Pradesh, India for the sustainable development

For emerging countries, mining has been a vital factor in employment, economic development, infra... more For emerging countries, mining has been a vital factor in employment, economic development, infrastructure, and supply of
essential raw materials for Nation’s Gross domestic product (GDP) growth. The Limestone mine industry is serving as a viable
route for economic transformation in India. Limestone exploration causes major damage to the environment at Yerraguntla
industrial zone, YSR Kadapa district, Andhra Pradesh, India. The main objective of this study is to evaluate the environmental
Pollution parameter that causes Air, Water, Noise, and Soil pollution in and around limestone quarries started in the early 1984.
The present study estimated Air Quality Index (AQI) as 76 based on the air quality sub-index approach using four pollutants
(PM10, PM2.5, SO2, NOx) for a period of 24 hrs by taking one sample per hour during the post monsoon. Water Quality Index
(WQI) obtained as 303.91 from fourteen physicochemical parameters (pH, EC, fluoride, Total alkalinity etc.) measured from
water samples. Soil quality was determined using four physicochemical parameters (pH, EC, WHC, Calcium and Magnesium)
from the soil samples collected from ten sampling stations. The obtained pH range was (7.6 to 9.4), EC of the soil was determined as 4,140 µs/cm, the water retention capacity of the soil, ranges from (17.68 to 97.68) %, and the Calcium (Ca2+) and
Magnesium (Mg2+) ranged from 74.5 to 272.75 mEq/L. Noise levels were determined as 76.64 dB in the mine’s, 58.16 dB in the
cement industry, and 52.285 dB in the mine surrounding villages. This study can help mining sector management’s in developing a sustainable Environmental Management frame work to meet the world sustainable development goals (SDGs).

Design and Simulation of an Efficient Vedic Booth Multiplier

A new multiplier design using the combination of modified booth's recoding algorithm and Vedic ma... more A new multiplier design using the combination of modified booth's recoding algorithm and Vedic mathematics is presented in this paper. The basic Vedic multiplication algorithm requires multipliers to perform multiplication internally i.e, vertically and crosswise. If we use normal multipliers as an internal multiplier in Vedic it's performance is high but it consumes much power. The proposed Vedic multiplier design uses modified booth's recoding algorithm to perform internal multiplication. The proposed multiplier design gives high performance and consumes less power .the simulation and synthesis of the design is carried out using quartus II 9.1 tool.

Study, Implementation and Comparison of Different Multipliers Based on Array, Vedic and KCM using Squarer Mathematics using EDA Tools

As Multiplication dominates the execution time of the most Digital Signal Processing algorithms, ... more As Multiplication dominates the execution time of the most Digital Signal Processing algorithms, so there is a need of high speed multiplier. This paper presents the detailed study of different multipliers based on Array Multiplier, Constant coefficient multiplication (KCM) and multiplication based on Vedic mathematics. Where square values are stored in a ROM. However, implementation of memory results in higher power consumption. This paper proposes an alternative scheme to find out the square with reduced size of memory. Prominently, squares of n bit numbers are found out using a ROM containing the squares of n/2 bit numbers. Additionally, the proposed scheme can be used as a squaring algorithm which is useful in many DSP applications like Image Compression, Decoding, Demodulation, Adaptive Modulation, Least Mean Squaring, etc... All these multipliers are coded in Verilog HDL (Hardware Description Language synthesized in EDA tool Xilinx_ISE10.1. All multipliers are then compared based on LUTs (Look up table) and path delays.

EFFICIENT MULTIOUTPUT CARRY LOOK-AHEAD ADDERS

Addition is the fundamental operation for any VLSI processors or Digital Signal Processing (DSP).... more Addition is the fundamental operation for any VLSI processors or Digital Signal Processing (DSP). In this paper we present an efficient implementation of a 16-bit Manchester carry chain (MCC) adder using an enhanced multiple output domino logic. In adder circuits the main drawback is propagation delay and to overcome this drawback using domino logic. In this paper 4-bit, 8-bit and 16-bit adders are been designed and power, delay and area are measured using TANNER tool, and then compared with the conventional adder. The experimental results reveal that the proposed adders achieve delay, power and area reductions for Multi bit addition.

Design and Simulation of Three State Bootstrapped Sample and Hold Circuit

In modern era, the development of high resolution ADCs proves to be crucial task. The design of s... more In modern era, the development of high resolution ADCs proves to be crucial task. The design of sample and hold circuit is also sensitive to the design of ADC. This paper describes the design of the three state bootstrapped sample and hold circuit which can be used for three levels of logic values in the Analog-to-digital converters. The simulation is done in HSPICE Synopsis Tool and is verified for performance improvement. The bootstrapped sample and hold circuit proves to be nearly 60% higher for power delay product.

Design of High Speed Vedic Square by using Vedic Multiplication Techniques

Digital signal processors (DSPs) are very important in various engineering disciplines. Faster ad... more Digital signal processors (DSPs) are very important in various engineering disciplines. Faster additions and multiplications are of extreme importance in DSP for convolution, discrete Fourier transforms, digital filters,etc. As in all the arithmetic operations, it is the squaring which is most important in finding the transforms or the inverse transforms in signal processing. The squaring operation occupies most of the computing time, therefore it is necessary to concentrate on the improvement of speed with which. Urdhava Triyakbhyam algorithm of ancient Indian Vedic Mathematics is utilized to improve its efficiency. This is a highly modular design in which smaller blocks can be used to build higher blocks. Vedic square is designed by using Verilog HDL coding and compared the performance with the modified Wallace tree in terms of time delay and area occupied on the Xilinx Spartan xc3s500e-5fg320.

Performance Analysis of Aola Technique for Wireless Communication

In wireless communication, multiplexing & multiple access concept is most important. In most comm... more In wireless communication, multiplexing & multiple access concept is most important. In most communication systems require, sharing of channels. In Multiple Access techniques types such as FDMA, TDMA, CDMA, & OFDM. OFDM based transmission system uses CP in an MB-OFDM symbol in order to maintain the orthogonality of Trasmission.Present days ultra-wideband systems use multi-band OFDM techniques for transmission in application like wireless personal area network(WPAN). UWB based system are power limited. cp introduces correlations in the transmitted data sequence &by using ZP suffix will have a flat psd. In the receiver ZP removal require use of a technique called as OLA. In this proposed, method we are implementing a rayleighpading channel placed by AWGN channel, adding ZP to increase the efficiency changing modulation technique for OFDM system. The simulation results shows the better results compared to the previous technique.

Design and Implementation of a Memory for Joint Improvement of Error Tolerance and Access Efficiency

The on-chip memory becomes increasingly exposed to the dual challenges of device-level reliabilit... more The on-chip memory becomes increasingly exposed to the dual challenges of device-level reliability degradation and architecture-level performance gap. We propose to exploit the inherent memory soft redundancy for on-chip memory design. Due to the mismatch between fixed cache line size and runtime variations in memory spatial locality, many irrelevant data are fetched into the memory thereby wasting memory spaces. The proposed soft-redundancy allocated memory detects and utilizes these memory spaces for jointly achieving efficient memory access and effective error control. We design an CRC & ECC with error correction techniques by making use of standard Ethernet (004C11DB7H) polynomial and compare with each other, which will be implemented in FPGA proposed system design which take care of the Cache and memory by rechecking the cache when a miss is identified and help in effective functionality of the system and finally we compare which method will give good results in terms of cost and reliability.

Land use Land cover change Assessment at Cement Industrial area using Landsat data-hybrid classification in part of YSR Kadapa District, Andhra Pradesh, India

India is the world's second-largest cement manufacturer. It is a significant contributor to the I... more India is the world's second-largest cement manufacturer. It is a significant contributor to the Indian economy's GDP. Kadapa district is one of Andhra Pradesh's largest cement producers. Limestone and cement plant sediment and mine have local, regional, and global impacts on soil, vegetation, and water and air quality. As a result, mapping and change evaluation of the mining area are critical for the sustainability of the cement industry. With today's advancements in remote sensing technology, mapping the Earth's characteristics, observing environmental changes, and controlling natural resources become more efficient with less human efforts than conventional methods. Proposed work focused on land environment temporal change assessment in YSR kadapa district, Andhra Pradesh, India over a period from 1991 to 2019. The results of Landsat-5/7/8 image Hybrid classification using ERDAS IMAGINE and ArcGIS over the study area 684KM 2 showing an overall accuracy 92 % and kappa index 0.9 in comparison to conventional methods of classification.

Delineation and evaluation of the captive limestone mining area change and its influence on the environment using multispectral satellite images for industrial long-term sustainability

Dynamics in Limestone mining sites are usually subjected to spatiotemporal land cover change, whi... more Dynamics in Limestone mining sites are usually subjected to spatiotemporal land cover change, which has a longterm impact on the land and environment. The objectives of this article are mapping demarcation, and transformation assessment of active captive limestone mines and their impact assessment on the environment at the Yerraguntla cement industrial region in YSR Kadapa district, Andhra Pradesh, India from the year 2006-2019 using Remote Sensing & Geographical Information System (RS&GIS). In this research work, first, the Normalized Differential Vegetation Index (NDVI) is computed, second NDVI image is resampled using NDVI threshold values, and the Nearest-Neighbor sampling method uses the QGIS raster calculator, which produces the mines area of 469.92 ha with Sentinel-2A MSI and 555.39 ha with Landsat-8(OLI) which is evaluated with delineated high resolution (~1m/pixels) Google Earth image (486.47 ha) from Google Earth Pro (freeware) and industry reports (487.10 ha) in 2019. Third active mines are demarcated using NDVI breakpoints. Results found that the limestone Mining area increased by 206.10% from 2006 to 2019, with Producer's Accuracy (PA), User's Accuracy (UA), and Kappa coefficients of 98.82%, 92.79%, and 0.92 in 2019, and 96.74%, 85.17 %t, and 0.82 in 2006. The compatibility between Landsat-8 and Sentinel-2A NDVI images is determined with Pearson's correlation coefficient (PCC) of 0.84 in 2019. In 2019, a linear negative Regression slope was revealed between NDVI & LST with a Correlation coefficient of 0.248, indicating negative environmental influences and vegetation control on LST. This research will aid industry and environmental engineers in comprehending the effects of limestone mine changes on LST and proposing an environmentally acceptable land-environmental management plan for longterm sustainability.

Satellite Image Based Spatio-Temporal Variation Assessment in Captive Limestone Mines for Long-Term Viability

Land use and Land cover mapping are crucial applications for planning and disaster mitigation as ... more Land use and Land cover mapping are crucial applications for planning and disaster mitigation as well as prevention. Such mapping is possible via satellite imagery. Every pixel in the training set must be labelled in order to employ machine learning techniques combined with image analysis for such land cover mapping. This paper mainly concentrates on the mining sector for assessing sustainable land environmental management plans. Google Earth mapping is one of the most efficient, economical, and reliable methods for better understanding of spatial and temporal changes of limestone mining area with less human efforts. High-resolution Google Earth images are used in assessing the temporal changes of the Limestone mine area in Kadapa district from 2011 to 2020. Google Earth Pro open-source software was used to extract images of captive limestone mines, which were then clipped using a polygon tool to aid in the creation of a land-use region occupied by the active mining area. It was found that the active mining area variation rate is in the Dalmia Cement Limestone mine is 308.49% which is the highest

Land use/Land Cover Change Assessment of Ysr Kadapa District, Andhra Pradesh, India using Irs Resourcesat-1/2 Liss Iii Multi-Temporal Open Source Data

LULC change assessment by the Remote sensing Technology helps in understanding land dynamics effe... more LULC change assessment by the Remote sensing Technology helps in understanding land dynamics effectively compared to conventional field inspection methods. This study provides the spatio-temporal dynamics of LULC classes in the Kadapa District, Andhra Pradesh, India. IRS Resourcesat-1/2 LISS III Multi-Temporal remote sensed data, from Bhuvan-Indian Geo-platform of ISRO is intended to assessment the changes in the study area during the years 2005-2006, 2011-2012 and 2015-2016 over tenure of 10 years. At the end the study area claasified into five major classes namely Built-up, Agriculture, Forest, Wastelands and waterbodies using ERDAS Imagine 2015. The results indicate net change and rate of change of LULC classes over the period of 10 years. Net change in Built-up land is 89.91%(167.12 km 2), Net change (decreased) in Agriculture land is 3.76% (256.05km 2), Net increment in the Forest land is 2.39 %(114.83km 2), Wastelands decreased by 2.92 %(79.09km 2), and waterbodies increased by 6.28% (52.9 km 2).

A Low-Noise AC coupled Instrumentation Amplifier for Recording Bio Signals

The human body is the source of many kinds of signals. These signals are called as bio signals. T... more The human body is the source of many kinds of signals. These signals are called as bio signals. These signals can be measured by placing an electrode in contact with the human body. These signals will be in the range of few mille volts and also the electrode will induce dc offset to the measured signals. These bio signals should be amplified for further analysis in biomedical applications. The bio signals will amplify by AC coupled instrumentation amplifier. The dc offset also suppressed by the AC coupled instrumentation amplifier. An AC coupled instrumentation amplifier is presented in this paper with low input interfered noise of ~20 and gain of 65 dB and CMRR of 142 dB with the total power consumption of 104pW.

DESIGN AND SYNTHESIS OF COMBINATIONAL CIRCUITS USING REVERSIBLE LOGIC

Reversible logic has become one of the recent emerging research pursuits contributing to the fiel... more Reversible logic has become one of the recent emerging research pursuits contributing to the field of low power dissipating circuit design in the past few years. Reversible logic find its owns applications in various fields which include quantum computing, nanotechnology, digital signal and image processing, optical computing, Low power VLSI etc., Decoders are one of the maximum essential circuit utilized in combinational logic. The whole design of combinational circuits like decoders, comparator, full adder, multiplexer are designed using Fredkin gate, CNOT, Peres gate and R-I gate which give better quantum cost when compared to other Reversible gates. The quantum cost and garbage outputs for combinational circuits in proposed designed has been compared with a previously existing design. The reversible logic circuits are designed and implemented using VHDL code and the simulation results are obtained in Xilinx ISE version 14.7.

A NOVEL DESIGN OF CSD RECODING WITH FAULT TOLERANT FULL ADDER

Canonic signed digit (CSD) involves very few non-zero bits, designing it for high speed and area ... more Canonic signed digit (CSD) involves very few non-zero bits, designing it for high speed and area optimization in VLSI based DSP architectures. The CSD has been designed with number of adders. Because of faults like struck at faults present in the adders during its operation, there may be a deviation in the expected results. It is very difficult to detect these faults in offline. So that, We proposed CSD with Fault tolerant Full Adder. The ordinary full adder performs addition of bits, but it is not able to detect and correct whenever the faults occurred during the operation. The proposed Fault tolerant Full Adder in CSD play important role to detect the faults with their exact location and also tolerate the faults. In this paper, we present high speed, FPGA fabric aware pipelined architectures for CSD recoding circuits using fault tolerant Full Adder starting from a two's complement number to redundant signed digit input.

An Extensive Projection to Create an Efficient Clock Specifications Based on Design Rule Violation Constraints

With shrinking technology nodes, the demand of more speed (frequency) and use of ultra-low power ... more With shrinking technology nodes, the demand of more speed (frequency) and use of ultra-low power has been increased. While trying to work on this we are forgetting that number of functionalities in a single chip is also increasing. To meet the market demand and pressure number of gates has been significantly increased on a single chip. The impact of crosstalk and SI delay increases as we move lower in technology nodes. Extra precautions need to be taken care in each stage of Physical Design(PD). Here Clock Tree Synthesis (CTS) plays a major role. For the CTS we need to give specification show to build clock tree to meet transition, latency and skew requirements. These spec generations depends upon timing constraints (SDC) as well as DRV constraints. Furthermore, I am proposing clock spec generation flow that will consider exception also and I will see how to fix DRV constraints effectively by manipulating the no. of buffers used. So it will control area being used as well as power for no. of chips. In this proposed method, to meet these constraints I will use TCL Scripting and IC Compiler to get the clear Clock specifications.

In situ measurement and management of soil, air, noise and water pollution in and around the Limestone mining area of Yerraguntla, YSR kadapa, Andhra Pradesh, India for the sustainable development

For emerging countries, mining has been a vital factor in employment, economic development, infra... more For emerging countries, mining has been a vital factor in employment, economic development, infrastructure, and supply of
essential raw materials for Nation’s Gross domestic product (GDP) growth. The Limestone mine industry is serving as a viable
route for economic transformation in India. Limestone exploration causes major damage to the environment at Yerraguntla
industrial zone, YSR Kadapa district, Andhra Pradesh, India. The main objective of this study is to evaluate the environmental
Pollution parameter that causes Air, Water, Noise, and Soil pollution in and around limestone quarries started in the early 1984.
The present study estimated Air Quality Index (AQI) as 76 based on the air quality sub-index approach using four pollutants
(PM10, PM2.5, SO2, NOx) for a period of 24 hrs by taking one sample per hour during the post monsoon. Water Quality Index
(WQI) obtained as 303.91 from fourteen physicochemical parameters (pH, EC, fluoride, Total alkalinity etc.) measured from
water samples. Soil quality was determined using four physicochemical parameters (pH, EC, WHC, Calcium and Magnesium)
from the soil samples collected from ten sampling stations. The obtained pH range was (7.6 to 9.4), EC of the soil was determined as 4,140 µs/cm, the water retention capacity of the soil, ranges from (17.68 to 97.68) %, and the Calcium (Ca2+) and
Magnesium (Mg2+) ranged from 74.5 to 272.75 mEq/L. Noise levels were determined as 76.64 dB in the mine’s, 58.16 dB in the
cement industry, and 52.285 dB in the mine surrounding villages. This study can help mining sector management’s in developing a sustainable Environmental Management frame work to meet the world sustainable development goals (SDGs).

Design and Simulation of an Efficient Vedic Booth Multiplier

A new multiplier design using the combination of modified booth's recoding algorithm and Vedic ma... more A new multiplier design using the combination of modified booth's recoding algorithm and Vedic mathematics is presented in this paper. The basic Vedic multiplication algorithm requires multipliers to perform multiplication internally i.e, vertically and crosswise. If we use normal multipliers as an internal multiplier in Vedic it's performance is high but it consumes much power. The proposed Vedic multiplier design uses modified booth's recoding algorithm to perform internal multiplication. The proposed multiplier design gives high performance and consumes less power .the simulation and synthesis of the design is carried out using quartus II 9.1 tool.

Study, Implementation and Comparison of Different Multipliers Based on Array, Vedic and KCM using Squarer Mathematics using EDA Tools

As Multiplication dominates the execution time of the most Digital Signal Processing algorithms, ... more As Multiplication dominates the execution time of the most Digital Signal Processing algorithms, so there is a need of high speed multiplier. This paper presents the detailed study of different multipliers based on Array Multiplier, Constant coefficient multiplication (KCM) and multiplication based on Vedic mathematics. Where square values are stored in a ROM. However, implementation of memory results in higher power consumption. This paper proposes an alternative scheme to find out the square with reduced size of memory. Prominently, squares of n bit numbers are found out using a ROM containing the squares of n/2 bit numbers. Additionally, the proposed scheme can be used as a squaring algorithm which is useful in many DSP applications like Image Compression, Decoding, Demodulation, Adaptive Modulation, Least Mean Squaring, etc... All these multipliers are coded in Verilog HDL (Hardware Description Language synthesized in EDA tool Xilinx_ISE10.1. All multipliers are then compared based on LUTs (Look up table) and path delays.

EFFICIENT MULTIOUTPUT CARRY LOOK-AHEAD ADDERS

Addition is the fundamental operation for any VLSI processors or Digital Signal Processing (DSP).... more Addition is the fundamental operation for any VLSI processors or Digital Signal Processing (DSP). In this paper we present an efficient implementation of a 16-bit Manchester carry chain (MCC) adder using an enhanced multiple output domino logic. In adder circuits the main drawback is propagation delay and to overcome this drawback using domino logic. In this paper 4-bit, 8-bit and 16-bit adders are been designed and power, delay and area are measured using TANNER tool, and then compared with the conventional adder. The experimental results reveal that the proposed adders achieve delay, power and area reductions for Multi bit addition.

Design and Simulation of Three State Bootstrapped Sample and Hold Circuit

In modern era, the development of high resolution ADCs proves to be crucial task. The design of s... more In modern era, the development of high resolution ADCs proves to be crucial task. The design of sample and hold circuit is also sensitive to the design of ADC. This paper describes the design of the three state bootstrapped sample and hold circuit which can be used for three levels of logic values in the Analog-to-digital converters. The simulation is done in HSPICE Synopsis Tool and is verified for performance improvement. The bootstrapped sample and hold circuit proves to be nearly 60% higher for power delay product.

Design of High Speed Vedic Square by using Vedic Multiplication Techniques

Digital signal processors (DSPs) are very important in various engineering disciplines. Faster ad... more Digital signal processors (DSPs) are very important in various engineering disciplines. Faster additions and multiplications are of extreme importance in DSP for convolution, discrete Fourier transforms, digital filters,etc. As in all the arithmetic operations, it is the squaring which is most important in finding the transforms or the inverse transforms in signal processing. The squaring operation occupies most of the computing time, therefore it is necessary to concentrate on the improvement of speed with which. Urdhava Triyakbhyam algorithm of ancient Indian Vedic Mathematics is utilized to improve its efficiency. This is a highly modular design in which smaller blocks can be used to build higher blocks. Vedic square is designed by using Verilog HDL coding and compared the performance with the modified Wallace tree in terms of time delay and area occupied on the Xilinx Spartan xc3s500e-5fg320.

Performance Analysis of Aola Technique for Wireless Communication

In wireless communication, multiplexing & multiple access concept is most important. In most comm... more In wireless communication, multiplexing & multiple access concept is most important. In most communication systems require, sharing of channels. In Multiple Access techniques types such as FDMA, TDMA, CDMA, & OFDM. OFDM based transmission system uses CP in an MB-OFDM symbol in order to maintain the orthogonality of Trasmission.Present days ultra-wideband systems use multi-band OFDM techniques for transmission in application like wireless personal area network(WPAN). UWB based system are power limited. cp introduces correlations in the transmitted data sequence &by using ZP suffix will have a flat psd. In the receiver ZP removal require use of a technique called as OLA. In this proposed, method we are implementing a rayleighpading channel placed by AWGN channel, adding ZP to increase the efficiency changing modulation technique for OFDM system. The simulation results shows the better results compared to the previous technique.

Design and Implementation of a Memory for Joint Improvement of Error Tolerance and Access Efficiency

The on-chip memory becomes increasingly exposed to the dual challenges of device-level reliabilit... more The on-chip memory becomes increasingly exposed to the dual challenges of device-level reliability degradation and architecture-level performance gap. We propose to exploit the inherent memory soft redundancy for on-chip memory design. Due to the mismatch between fixed cache line size and runtime variations in memory spatial locality, many irrelevant data are fetched into the memory thereby wasting memory spaces. The proposed soft-redundancy allocated memory detects and utilizes these memory spaces for jointly achieving efficient memory access and effective error control. We design an CRC & ECC with error correction techniques by making use of standard Ethernet (004C11DB7H) polynomial and compare with each other, which will be implemented in FPGA proposed system design which take care of the Cache and memory by rechecking the cache when a miss is identified and help in effective functionality of the system and finally we compare which method will give good results in terms of cost and reliability.

Land use Land cover change Assessment at Cement Industrial area using Landsat data-hybrid classification in part of YSR Kadapa District, Andhra Pradesh, India

India is the world's second-largest cement manufacturer. It is a significant contributor to the I... more India is the world's second-largest cement manufacturer. It is a significant contributor to the Indian economy's GDP. Kadapa district is one of Andhra Pradesh's largest cement producers. Limestone and cement plant sediment and mine have local, regional, and global impacts on soil, vegetation, and water and air quality. As a result, mapping and change evaluation of the mining area are critical for the sustainability of the cement industry. With today's advancements in remote sensing technology, mapping the Earth's characteristics, observing environmental changes, and controlling natural resources become more efficient with less human efforts than conventional methods. Proposed work focused on land environment temporal change assessment in YSR kadapa district, Andhra Pradesh, India over a period from 1991 to 2019. The results of Landsat-5/7/8 image Hybrid classification using ERDAS IMAGINE and ArcGIS over the study area 684KM 2 showing an overall accuracy 92 % and kappa index 0.9 in comparison to conventional methods of classification.

Delineation and evaluation of the captive limestone mining area change and its influence on the environment using multispectral satellite images for industrial long-term sustainability

Dynamics in Limestone mining sites are usually subjected to spatiotemporal land cover change, whi... more Dynamics in Limestone mining sites are usually subjected to spatiotemporal land cover change, which has a longterm impact on the land and environment. The objectives of this article are mapping demarcation, and transformation assessment of active captive limestone mines and their impact assessment on the environment at the Yerraguntla cement industrial region in YSR Kadapa district, Andhra Pradesh, India from the year 2006-2019 using Remote Sensing & Geographical Information System (RS&GIS). In this research work, first, the Normalized Differential Vegetation Index (NDVI) is computed, second NDVI image is resampled using NDVI threshold values, and the Nearest-Neighbor sampling method uses the QGIS raster calculator, which produces the mines area of 469.92 ha with Sentinel-2A MSI and 555.39 ha with Landsat-8(OLI) which is evaluated with delineated high resolution (~1m/pixels) Google Earth image (486.47 ha) from Google Earth Pro (freeware) and industry reports (487.10 ha) in 2019. Third active mines are demarcated using NDVI breakpoints. Results found that the limestone Mining area increased by 206.10% from 2006 to 2019, with Producer's Accuracy (PA), User's Accuracy (UA), and Kappa coefficients of 98.82%, 92.79%, and 0.92 in 2019, and 96.74%, 85.17 %t, and 0.82 in 2006. The compatibility between Landsat-8 and Sentinel-2A NDVI images is determined with Pearson's correlation coefficient (PCC) of 0.84 in 2019. In 2019, a linear negative Regression slope was revealed between NDVI & LST with a Correlation coefficient of 0.248, indicating negative environmental influences and vegetation control on LST. This research will aid industry and environmental engineers in comprehending the effects of limestone mine changes on LST and proposing an environmentally acceptable land-environmental management plan for longterm sustainability.

Satellite Image Based Spatio-Temporal Variation Assessment in Captive Limestone Mines for Long-Term Viability

Land use and Land cover mapping are crucial applications for planning and disaster mitigation as ... more Land use and Land cover mapping are crucial applications for planning and disaster mitigation as well as prevention. Such mapping is possible via satellite imagery. Every pixel in the training set must be labelled in order to employ machine learning techniques combined with image analysis for such land cover mapping. This paper mainly concentrates on the mining sector for assessing sustainable land environmental management plans. Google Earth mapping is one of the most efficient, economical, and reliable methods for better understanding of spatial and temporal changes of limestone mining area with less human efforts. High-resolution Google Earth images are used in assessing the temporal changes of the Limestone mine area in Kadapa district from 2011 to 2020. Google Earth Pro open-source software was used to extract images of captive limestone mines, which were then clipped using a polygon tool to aid in the creation of a land-use region occupied by the active mining area. It was found that the active mining area variation rate is in the Dalmia Cement Limestone mine is 308.49% which is the highest

Land use/Land Cover Change Assessment of Ysr Kadapa District, Andhra Pradesh, India using Irs Resourcesat-1/2 Liss Iii Multi-Temporal Open Source Data

LULC change assessment by the Remote sensing Technology helps in understanding land dynamics effe... more LULC change assessment by the Remote sensing Technology helps in understanding land dynamics effectively compared to conventional field inspection methods. This study provides the spatio-temporal dynamics of LULC classes in the Kadapa District, Andhra Pradesh, India. IRS Resourcesat-1/2 LISS III Multi-Temporal remote sensed data, from Bhuvan-Indian Geo-platform of ISRO is intended to assessment the changes in the study area during the years 2005-2006, 2011-2012 and 2015-2016 over tenure of 10 years. At the end the study area claasified into five major classes namely Built-up, Agriculture, Forest, Wastelands and waterbodies using ERDAS Imagine 2015. The results indicate net change and rate of change of LULC classes over the period of 10 years. Net change in Built-up land is 89.91%(167.12 km 2), Net change (decreased) in Agriculture land is 3.76% (256.05km 2), Net increment in the Forest land is 2.39 %(114.83km 2), Wastelands decreased by 2.92 %(79.09km 2), and waterbodies increased by 6.28% (52.9 km 2).