Ieee Transactions on Circuits and Systems Ii Express Briefs, 2010
To the best of the authors' knowledge, this is the first brief that implements a complete automat... more To the best of the authors' knowledge, this is the first brief that implements a complete automatic fingerprint-based authentication system (AFAS) application under a dynamically partial self-reconfigurable field-programmable gate array (FPGA). The main benefits of this implementation are the acceleration of the processing reached by the parallelism inherent to the hardware design, the high level of integration, the consequent security and reliability improvements provided by the usage of a system-on-programmable-chip device that is able to embed the main components of the application in a single chip, and the low cost achieved by the whole system due to the reconfigurability performance featured by the suggested FPGA. All these factors result in an outstanding system that is able to authenticate the identity of any user by means of those distinctive characteristics available in fingerprints. This brief reveals the advantages of run-time reconfigurable hardware in the implementation of those embedded systems demanding real-time performance at low cost. The minimization of the reconfiguration overhead by means of the proper sizing of the reconfigurable region in the FPGA and the design of a hardware configuration controller that is able to reach the maximum configuration rates allowed by the technology (3.2 Gb/s) are key factors to succeed in the development of the embedded AFAS application. The proposed system, which is implemented by means of hardware-software co-design techniques under a Virtex4 XC4VLX25 FPGA working at 100 MHz, is able to overcome in one order of magnitude the execution time performance achieved by a personal computer platform based on an Intel Core2Duo microprocessor running at 1.83 GHz.
Fuzzy Logic is, nowadays, a control technique widely extended in nonlinear system applications. T... more Fuzzy Logic is, nowadays, a control technique widely extended in nonlinear system applications. This work adds a new point-of-view to the continuous efforts in search of an optimized hardware-software co-design of a dual-input single-output fuzzy logic controller (FLC). Our approach breaks up with the classical three-stage implementation process fuzzification, rule inference and defuzzification cores to focus it on directly synthesizing the resultant control surface. An innovative design methodology is defined by firstly splitting the total area in rectangular sectors to, afterwards, model each of them by second-order polynomial functions. The algorithm is finally embedded in a MCU-FPGA platform to achieve a balanced cost-performance solution inspired by such efficient concepts in terms of runtime and silicon-area as parallel processing and dynamic partial reconfiguration, respectively. The result is a universal FLC where the control surface is parameterized and handled through a simple data file appended to the design bitstream in the way of initialized SRAM memory. This HW/SW architecture therefore provides a general-purpose solution able to customize whichever fuzzy application by only updating the data that model the particular control surface segmented in rectangular sectors.
Most partitioning algorithms have been developed for conventional programmable logic (especially ... more Most partitioning algorithms have been developed for conventional programmable logic (especially FPGAs), being their main goal the minimisation of the signals constituting the interface (cutsize) between partitions, while balancing partition sizes. New families of dynamic reconfigurable programmable logic (DRPL) offer new possibilities to improve functional density of circuits, but traditional partitioning techniques are not able to exploit the novel features offered by these devices. A new family of partitioning techniques for DRPL should be developed, being its main goal the maximisation of the functional density on balanced partition sizes. This paper presents a new partitioning algorithm based on a temporal separation of the system functionality. As our experimental results will show, the algorithm is able to benefit from the dynamic reconfiguration properties of FPGA devices.
This paper will describe a systematic method to map synchronous digital systems into Dynamically ... more This paper will describe a systematic method to map synchronous digital systems into Dynamically Reconfigurable Logic, as the FIPSOC device. The method is based on a temporal bipartitioning technique able to separate the functionality of a static implementation in two temporal independence hardware contexts. As the experimental results show, the method capable of improving the functional density of the dynamic implementation with respect to the static one.
Resumen La computación reconfigurable tiende, cada vez más, a fusionarse con el codiseño hardware... more Resumen La computación reconfigurable tiende, cada vez más, a fusionarse con el codiseño hardware-software (HW-SW) en el ámbito del desarrollo de aplicaciones embebidas que exigen alta complejidad de procesado, tiempo real y bajo coste. Ambas técnicas de diseño están presentes en la programación de un dispositivo system-on-chip (SoC), el cual combina aspectos SW a través de un microcontrolador (MCU) de propósito general y aspectos de HW flexible mediante un dispositivo lógico FPGA reconfigurable. Este trabajo aborda la implementación de un sistema automático de reconocimiento biométrico de huella dactilar fundamentado en estas dos técnicas de diseño. Se pretende alcanzar una eficiente arquitectura HW-SW que se adapte a la aplicación con un correcto balance entre área (coste) y tiempo (prestaciones).
Resumen. En este trabajo se presenta la experiencia didáctica desarrollada por los profesores de ... more Resumen. En este trabajo se presenta la experiencia didáctica desarrollada por los profesores de la Universidad Politécnica de Cataluña y la Universidad Rovira i Virgili con relación a los dispositivos FPGA (Field Programmable Gate Array) y su actual aplicación tecnológica. En este sentido se expone un conjunto de experiencias prácti-cas que permiten al estudiante profundizar en el diseño del sistemas de instrumenta-ción y control basados en dispositivos FPGA's. Las experiencias presentadas forman parte del contenido de la asignatura "Sistemas Digitales de Instrumentación y Con-trol" que se oferta actualmente como asignatura optativa en la Escuela Politécnica Superior de Ingeniería de Vilanova y la Geltrú (UPC).
El presente artículo muestra la implementación de una unidad en coma flotante (FPU) que actúa com... more El presente artículo muestra la implementación de una unidad en coma flotante (FPU) que actúa como coprocesador dentro de un sistema auto-reconfigurable dinámicamente. La FPU tiene capacidad para resolver operaciones básicas como la suma, la resta, el producto, el cociente, la raíz cuadrada, la inversa y el cuadrado. Además, dispone de un registro en el que se almacena el último resultado obtenido con la intención de utilizarlo como operador en el siguiente cálculo, de modo que se reducen los accesos a los buses de comunicación en la resolución de las operaciones matemáticas. El diseño emplea Microblaze como microprocesador del sistema y su implementación se ha realizado sobre una FPGA Spartan 3 de bajo coste. El artículo muestra resultados experimentales en relación al área total ocupada, así como los tiempos de ejecución obtenidos con un ejemplo particular basado en un algoritmo de CORDIC resuelto en coma flotante. Peer Reviewed Postprint (author’s final draft)
Resumen Este artículo presenta un procedimiento simple para la obtención de la clave criptográfic... more Resumen Este artículo presenta un procedimiento simple para la obtención de la clave criptográfica del algoritmo AES ejecutado sobre MicroBlaze. La clave se obtiene analizando la correlación estadística que existe entre ésta y el consumo del dispositivo hardware que ejecuta el propio algoritmo. El trabajo también muestra como las contramedidas clásicas de enmascarado del texto plano son únicamente eficientes frente ataques de primer orden. Los resultados experimentales muestran diferentes ataques realizados sobre varios bloques del algoritmo, y concluyen que es posible obtener la clave criptográfica tomando un número de trazas de corriente inferior a 40.
Proceedings of the First NASA/DoD Workshop on Evolvable Hardware, 1999
In this paper we shall address the physical implementation of self-repairing and evolvable hardwa... more In this paper we shall address the physical implementation of self-repairing and evolvable hardware strategies. These alternatives will be enabled by the specific dynamic reconfiguration capabilities included in a new family of FPGA devices, called FIPSOC (Field programmable System On a Chip). The main features of these devices are given by the integration on a single chip of a dynamically
In this paper we address the problems posed when Artificial Neural Networks models are implemente... more In this paper we address the problems posed when Artificial Neural Networks models are implemented in programmable digital hardware. Within this context, we shall especially emphasise the realisation of the arithmetic operators required by these models, since it constitutes the main constraint (due to the required amount of resources) found when they are to be translated into physical hardware. The
Proceedings of the Seventh International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 2000
In this paper we shall address the possibility of incorporating a new degree of freedom in the de... more In this paper we shall address the possibility of incorporating a new degree of freedom in the design of electronic systems. It consists of providing the ability to evolve its internal meso-structure while in operation. This new design strategy is allowed by the features included in a new family of FPGA devices, which is called FIPSOC (Field Programmable System On a Chip). Besides a programmable digital section composed of an array of LUT-like configurable cells, the device includes a configurable analog part and a general purpose microcontroller. Furthermore, the configuration scheme used for the programmable digital section allows for an efficient and fast realisation of dynamic reconfiguration principles. As we shall show in this paper, these properties offer two new on-line hardware evolution strategies, giving rise to what we have called virtual meso-structures.
In this paper we shall address the paradigms of evolutionary and selfrepairing hardware using a n... more In this paper we shall address the paradigms of evolutionary and selfrepairing hardware using a new family of programmable devices, called FIPSOC (Field Programmable System On a Chip). The most salient feature of these devices is the integration on a single chip of a programmable digital section, a programmable analog section and a general-purpose microcontroller. Furthermore, the programmable digital section has been designed including a flexible and fast dynamic reconfiguration scheme. These properties provide an efficient framework for tackling the specific features posed by the emerging field of evolutionary computation. We shall demonstrate this fact by means of two different case studies: a self-repairing strategy for digital systems, suitable for applications in environments exposed to radiation, and an efficient implementation scheme for evolving parallel cellular machines.
1999 7th IEEE International Conference on Emerging Technologies and Factory Automation. Proceedings ETFA '99 (Cat. No.99TH8467), 1999
FIPSOC (field programmable system on chip) is a novel device shown to be suitable for rapid proto... more FIPSOC (field programmable system on chip) is a novel device shown to be suitable for rapid prototyping of electronic systems. After a description of its architecture and associated development tools, its distinguishing features are highlighted. In particular, integration of a microprocessor, programmable logic and configurable analog channels in the same chip provides a monolithic platform with capability to prototype complete
ABSTRACT This paper will explain a systematic technique for the implementation of a synchronous c... more ABSTRACT This paper will explain a systematic technique for the implementation of a synchronous circuit into the DRFPGA (dynamic reconfigurable FPGA) included in the FIPSOC devices, taking advantage of their properties of dynamic reconfiguration. The circuit to be implemented is partitioned using a set of temporal bipartitioning rules, and each partition is mapped on a separated context, sharing both contexts the same hardware resources. The time-multiplexed execution of both contexts constitutes a virtual circuit.
Abstraet: Engineering applications often demand high-performance processors to carry out specific... more Abstraet: Engineering applications often demand high-performance processors to carry out specific compute-intensive tasks. This work describes the hardwaresoftware co-design of the CORDIC (Coordinate Rotation Digital Computer) algorithm, all embedded in a system-on-chip device. This platform, based on an 8bit RISC microcontroller and a dynamically reconfigurable FPGA, makes feasible the efficient implementation of the shift-add algorithm through a 32-bit fixed-point trigonometric computer that evolves on-the-fly to process functions as sin(z), cos(z), atan(y/x) and sqrt(x2+r). Its balanced architecture -a low-cost processor extended by a dedicated slave coprocessor to accelerate the calculus -reaches significant improvements in throughput over conventional software-oriented solutions usually inspired on powerful 32-bit stand-alone microprocessors.
This work aims to pave the way for an efficient open system architecture applied to embedded elec... more This work aims to pave the way for an efficient open system architecture applied to embedded electronic applications to manage the processing of computationally complex algorithms at real-time and low-cost. The target is to define a standard architecture able to enhance the performance-cost trade-off delivered by other alternatives nowadays in the market like general-purpose multi-core processors. Our approach, sustained by
Most biometrics systems are implemented on high performance microprocessors executing complex alg... more Most biometrics systems are implemented on high performance microprocessors executing complex algorithms on software. In order to develop a low-cost and high-speed coprocessor, floating-point computations have been substituted by fixed-point ones, and a pipeline scheme has been developed.
Proceedings of the IEEE International Symposium on Industrial Electronics, 2005. ISIE 2005., 2005
Nature has provided human beings unique and different each one in relation to the others; even &a... more Nature has provided human beings unique and different each one in relation to the others; even 'identical' twins have infinite differences between them. Every individual has his own biological characteristics that allow him to be distinguished from the rest of the humanity. In recent years, biometrics and computer technology have joined together in order to improve the security in everyday
2007 International Conference on Field Programmable Logic and Applications, 2007
The uniqueness of human fingerprints has been accepted by the scientific community since long tim... more The uniqueness of human fingerprints has been accepted by the scientific community since long time ago. Proof of this is the fact that, among all physiological characteristics, fingerprints are the oldest and most deeply used signs of identity for personal recognition. However up to date, the development of an automatic fingerprint-based human authentication system is an open research problem. Most of the difficulties rely on the complexity and the high computational power needed to develop a fingerprint matching algorithm reliable enough to guarantee the accuracy of the result even when only low-quality fingerprint impressions are available from the users. In order to deal with the processing power requested by the system, an application-specific hardware accelerator developed by means of hardware-software co-design techniques is suggested in this work for the fingerprint alignment stage. The hardware processor permits to speed up the alignment phase and to reach real-time performance, which is not guaranteed when developing the same algorithm under a purely-software platform.
Ieee Transactions on Circuits and Systems Ii Express Briefs, 2010
To the best of the authors' knowledge, this is the first brief that implements a complete automat... more To the best of the authors' knowledge, this is the first brief that implements a complete automatic fingerprint-based authentication system (AFAS) application under a dynamically partial self-reconfigurable field-programmable gate array (FPGA). The main benefits of this implementation are the acceleration of the processing reached by the parallelism inherent to the hardware design, the high level of integration, the consequent security and reliability improvements provided by the usage of a system-on-programmable-chip device that is able to embed the main components of the application in a single chip, and the low cost achieved by the whole system due to the reconfigurability performance featured by the suggested FPGA. All these factors result in an outstanding system that is able to authenticate the identity of any user by means of those distinctive characteristics available in fingerprints. This brief reveals the advantages of run-time reconfigurable hardware in the implementation of those embedded systems demanding real-time performance at low cost. The minimization of the reconfiguration overhead by means of the proper sizing of the reconfigurable region in the FPGA and the design of a hardware configuration controller that is able to reach the maximum configuration rates allowed by the technology (3.2 Gb/s) are key factors to succeed in the development of the embedded AFAS application. The proposed system, which is implemented by means of hardware-software co-design techniques under a Virtex4 XC4VLX25 FPGA working at 100 MHz, is able to overcome in one order of magnitude the execution time performance achieved by a personal computer platform based on an Intel Core2Duo microprocessor running at 1.83 GHz.
Fuzzy Logic is, nowadays, a control technique widely extended in nonlinear system applications. T... more Fuzzy Logic is, nowadays, a control technique widely extended in nonlinear system applications. This work adds a new point-of-view to the continuous efforts in search of an optimized hardware-software co-design of a dual-input single-output fuzzy logic controller (FLC). Our approach breaks up with the classical three-stage implementation process fuzzification, rule inference and defuzzification cores to focus it on directly synthesizing the resultant control surface. An innovative design methodology is defined by firstly splitting the total area in rectangular sectors to, afterwards, model each of them by second-order polynomial functions. The algorithm is finally embedded in a MCU-FPGA platform to achieve a balanced cost-performance solution inspired by such efficient concepts in terms of runtime and silicon-area as parallel processing and dynamic partial reconfiguration, respectively. The result is a universal FLC where the control surface is parameterized and handled through a simple data file appended to the design bitstream in the way of initialized SRAM memory. This HW/SW architecture therefore provides a general-purpose solution able to customize whichever fuzzy application by only updating the data that model the particular control surface segmented in rectangular sectors.
Most partitioning algorithms have been developed for conventional programmable logic (especially ... more Most partitioning algorithms have been developed for conventional programmable logic (especially FPGAs), being their main goal the minimisation of the signals constituting the interface (cutsize) between partitions, while balancing partition sizes. New families of dynamic reconfigurable programmable logic (DRPL) offer new possibilities to improve functional density of circuits, but traditional partitioning techniques are not able to exploit the novel features offered by these devices. A new family of partitioning techniques for DRPL should be developed, being its main goal the maximisation of the functional density on balanced partition sizes. This paper presents a new partitioning algorithm based on a temporal separation of the system functionality. As our experimental results will show, the algorithm is able to benefit from the dynamic reconfiguration properties of FPGA devices.
This paper will describe a systematic method to map synchronous digital systems into Dynamically ... more This paper will describe a systematic method to map synchronous digital systems into Dynamically Reconfigurable Logic, as the FIPSOC device. The method is based on a temporal bipartitioning technique able to separate the functionality of a static implementation in two temporal independence hardware contexts. As the experimental results show, the method capable of improving the functional density of the dynamic implementation with respect to the static one.
Resumen La computación reconfigurable tiende, cada vez más, a fusionarse con el codiseño hardware... more Resumen La computación reconfigurable tiende, cada vez más, a fusionarse con el codiseño hardware-software (HW-SW) en el ámbito del desarrollo de aplicaciones embebidas que exigen alta complejidad de procesado, tiempo real y bajo coste. Ambas técnicas de diseño están presentes en la programación de un dispositivo system-on-chip (SoC), el cual combina aspectos SW a través de un microcontrolador (MCU) de propósito general y aspectos de HW flexible mediante un dispositivo lógico FPGA reconfigurable. Este trabajo aborda la implementación de un sistema automático de reconocimiento biométrico de huella dactilar fundamentado en estas dos técnicas de diseño. Se pretende alcanzar una eficiente arquitectura HW-SW que se adapte a la aplicación con un correcto balance entre área (coste) y tiempo (prestaciones).
Resumen. En este trabajo se presenta la experiencia didáctica desarrollada por los profesores de ... more Resumen. En este trabajo se presenta la experiencia didáctica desarrollada por los profesores de la Universidad Politécnica de Cataluña y la Universidad Rovira i Virgili con relación a los dispositivos FPGA (Field Programmable Gate Array) y su actual aplicación tecnológica. En este sentido se expone un conjunto de experiencias prácti-cas que permiten al estudiante profundizar en el diseño del sistemas de instrumenta-ción y control basados en dispositivos FPGA's. Las experiencias presentadas forman parte del contenido de la asignatura "Sistemas Digitales de Instrumentación y Con-trol" que se oferta actualmente como asignatura optativa en la Escuela Politécnica Superior de Ingeniería de Vilanova y la Geltrú (UPC).
El presente artículo muestra la implementación de una unidad en coma flotante (FPU) que actúa com... more El presente artículo muestra la implementación de una unidad en coma flotante (FPU) que actúa como coprocesador dentro de un sistema auto-reconfigurable dinámicamente. La FPU tiene capacidad para resolver operaciones básicas como la suma, la resta, el producto, el cociente, la raíz cuadrada, la inversa y el cuadrado. Además, dispone de un registro en el que se almacena el último resultado obtenido con la intención de utilizarlo como operador en el siguiente cálculo, de modo que se reducen los accesos a los buses de comunicación en la resolución de las operaciones matemáticas. El diseño emplea Microblaze como microprocesador del sistema y su implementación se ha realizado sobre una FPGA Spartan 3 de bajo coste. El artículo muestra resultados experimentales en relación al área total ocupada, así como los tiempos de ejecución obtenidos con un ejemplo particular basado en un algoritmo de CORDIC resuelto en coma flotante. Peer Reviewed Postprint (author’s final draft)
Resumen Este artículo presenta un procedimiento simple para la obtención de la clave criptográfic... more Resumen Este artículo presenta un procedimiento simple para la obtención de la clave criptográfica del algoritmo AES ejecutado sobre MicroBlaze. La clave se obtiene analizando la correlación estadística que existe entre ésta y el consumo del dispositivo hardware que ejecuta el propio algoritmo. El trabajo también muestra como las contramedidas clásicas de enmascarado del texto plano son únicamente eficientes frente ataques de primer orden. Los resultados experimentales muestran diferentes ataques realizados sobre varios bloques del algoritmo, y concluyen que es posible obtener la clave criptográfica tomando un número de trazas de corriente inferior a 40.
Proceedings of the First NASA/DoD Workshop on Evolvable Hardware, 1999
In this paper we shall address the physical implementation of self-repairing and evolvable hardwa... more In this paper we shall address the physical implementation of self-repairing and evolvable hardware strategies. These alternatives will be enabled by the specific dynamic reconfiguration capabilities included in a new family of FPGA devices, called FIPSOC (Field programmable System On a Chip). The main features of these devices are given by the integration on a single chip of a dynamically
In this paper we address the problems posed when Artificial Neural Networks models are implemente... more In this paper we address the problems posed when Artificial Neural Networks models are implemented in programmable digital hardware. Within this context, we shall especially emphasise the realisation of the arithmetic operators required by these models, since it constitutes the main constraint (due to the required amount of resources) found when they are to be translated into physical hardware. The
Proceedings of the Seventh International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 2000
In this paper we shall address the possibility of incorporating a new degree of freedom in the de... more In this paper we shall address the possibility of incorporating a new degree of freedom in the design of electronic systems. It consists of providing the ability to evolve its internal meso-structure while in operation. This new design strategy is allowed by the features included in a new family of FPGA devices, which is called FIPSOC (Field Programmable System On a Chip). Besides a programmable digital section composed of an array of LUT-like configurable cells, the device includes a configurable analog part and a general purpose microcontroller. Furthermore, the configuration scheme used for the programmable digital section allows for an efficient and fast realisation of dynamic reconfiguration principles. As we shall show in this paper, these properties offer two new on-line hardware evolution strategies, giving rise to what we have called virtual meso-structures.
In this paper we shall address the paradigms of evolutionary and selfrepairing hardware using a n... more In this paper we shall address the paradigms of evolutionary and selfrepairing hardware using a new family of programmable devices, called FIPSOC (Field Programmable System On a Chip). The most salient feature of these devices is the integration on a single chip of a programmable digital section, a programmable analog section and a general-purpose microcontroller. Furthermore, the programmable digital section has been designed including a flexible and fast dynamic reconfiguration scheme. These properties provide an efficient framework for tackling the specific features posed by the emerging field of evolutionary computation. We shall demonstrate this fact by means of two different case studies: a self-repairing strategy for digital systems, suitable for applications in environments exposed to radiation, and an efficient implementation scheme for evolving parallel cellular machines.
1999 7th IEEE International Conference on Emerging Technologies and Factory Automation. Proceedings ETFA '99 (Cat. No.99TH8467), 1999
FIPSOC (field programmable system on chip) is a novel device shown to be suitable for rapid proto... more FIPSOC (field programmable system on chip) is a novel device shown to be suitable for rapid prototyping of electronic systems. After a description of its architecture and associated development tools, its distinguishing features are highlighted. In particular, integration of a microprocessor, programmable logic and configurable analog channels in the same chip provides a monolithic platform with capability to prototype complete
ABSTRACT This paper will explain a systematic technique for the implementation of a synchronous c... more ABSTRACT This paper will explain a systematic technique for the implementation of a synchronous circuit into the DRFPGA (dynamic reconfigurable FPGA) included in the FIPSOC devices, taking advantage of their properties of dynamic reconfiguration. The circuit to be implemented is partitioned using a set of temporal bipartitioning rules, and each partition is mapped on a separated context, sharing both contexts the same hardware resources. The time-multiplexed execution of both contexts constitutes a virtual circuit.
Abstraet: Engineering applications often demand high-performance processors to carry out specific... more Abstraet: Engineering applications often demand high-performance processors to carry out specific compute-intensive tasks. This work describes the hardwaresoftware co-design of the CORDIC (Coordinate Rotation Digital Computer) algorithm, all embedded in a system-on-chip device. This platform, based on an 8bit RISC microcontroller and a dynamically reconfigurable FPGA, makes feasible the efficient implementation of the shift-add algorithm through a 32-bit fixed-point trigonometric computer that evolves on-the-fly to process functions as sin(z), cos(z), atan(y/x) and sqrt(x2+r). Its balanced architecture -a low-cost processor extended by a dedicated slave coprocessor to accelerate the calculus -reaches significant improvements in throughput over conventional software-oriented solutions usually inspired on powerful 32-bit stand-alone microprocessors.
This work aims to pave the way for an efficient open system architecture applied to embedded elec... more This work aims to pave the way for an efficient open system architecture applied to embedded electronic applications to manage the processing of computationally complex algorithms at real-time and low-cost. The target is to define a standard architecture able to enhance the performance-cost trade-off delivered by other alternatives nowadays in the market like general-purpose multi-core processors. Our approach, sustained by
Most biometrics systems are implemented on high performance microprocessors executing complex alg... more Most biometrics systems are implemented on high performance microprocessors executing complex algorithms on software. In order to develop a low-cost and high-speed coprocessor, floating-point computations have been substituted by fixed-point ones, and a pipeline scheme has been developed.
Proceedings of the IEEE International Symposium on Industrial Electronics, 2005. ISIE 2005., 2005
Nature has provided human beings unique and different each one in relation to the others; even &a... more Nature has provided human beings unique and different each one in relation to the others; even 'identical' twins have infinite differences between them. Every individual has his own biological characteristics that allow him to be distinguished from the rest of the humanity. In recent years, biometrics and computer technology have joined together in order to improve the security in everyday
2007 International Conference on Field Programmable Logic and Applications, 2007
The uniqueness of human fingerprints has been accepted by the scientific community since long tim... more The uniqueness of human fingerprints has been accepted by the scientific community since long time ago. Proof of this is the fact that, among all physiological characteristics, fingerprints are the oldest and most deeply used signs of identity for personal recognition. However up to date, the development of an automatic fingerprint-based human authentication system is an open research problem. Most of the difficulties rely on the complexity and the high computational power needed to develop a fingerprint matching algorithm reliable enough to guarantee the accuracy of the result even when only low-quality fingerprint impressions are available from the users. In order to deal with the processing power requested by the system, an application-specific hardware accelerator developed by means of hardware-software co-design techniques is suggested in this work for the fingerprint alignment stage. The hardware processor permits to speed up the alignment phase and to reach real-time performance, which is not guaranteed when developing the same algorithm under a purely-software platform.
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Papers by Enrique Canto