2018 16th IEEE International New Circuits and Systems Conference (NEWCAS), 2018
In this work we present a novel architecture for a soft-decision Reed-Solomon LCC decoder. In our... more In this work we present a novel architecture for a soft-decision Reed-Solomon LCC decoder. In our decoder the data sorted and stored in the Multiplicity Assignment stage are different from other authors’ work. We present architectures for the Syndrome Update and Symbol Modification blocks that are adapted to the proposed sorting stage. We present implementation results for ASIC and FPGA that show that this architecture can reach high performance and low latency when compared with similar decoders. For example, in ASIC, our decoder requires 40% less area than a specific state-of-the-art decoder, while still has 40% higher throughput and 0.07 dB coding gain over that decoder.
2004 IEEE 15th International Symposium on Personal, Indoor and Mobile Radio Communications (IEEE Cat. No.04TH8754)
This paper deals with the design and implementation of a frame, time and frequency synchronizer f... more This paper deals with the design and implementation of a frame, time and frequency synchronizer for both Hiperlan/2 and IEEE 802.11a WLAN standards. In a packet oriented system, to perform a quick and correct synchronization it is critical to avoid severe bit error rate degradation. So, the design of this subsystem is one of the most challenging tasks to be
A realização deste trabalho tornou-se possível devido a colaboração primordial do nosso pai, Deus... more A realização deste trabalho tornou-se possível devido a colaboração primordial do nosso pai, Deus, que está no comando de tudo, sendo autor e consumador de nossa capacidade intelectual. Aos meus amados pais José Cardoso Taveira e Jeruza de Paula Taveira, pela transmissão exacerbada de carinho, amor e motivação durante minha formação acadêmica. As minhas apreciadas irmãs Ana Lídia de Paula Taveira Henriques e Lidiane de Paula Taveira, pela compreensão na minha ausência em momentos especiais da nossa vida. a . Dr a . Ana Patrícia Bastos Peixoto e Prof o . Dr. Tiago Almeida de Oliveira, pela expressiva competência, disposição e auxílio durante a elaboração deste trabalho. Aos membros da banca examinadora formada pelo Prof o . Dr. Ricardo Alves de Olinda e Prof a . Wanessa Weridiana da Luz Freitas por participarem como interlocutores desse trabalho, contribuindo assim para o enriquecimento teórico do mesmo. Aos meus amigos, do Curso Bacharelado em Estatística, em especial, Rosendo Chagas, Fábio Sandro Dos Santos, Leomir Ferreira Sousa pelo constante apoio e estímulo transmitido durante a construção das atividades teóricas e práticas do trabalho em epígrafe. A todos o meu sincero agradecimento. Alguns estudos tem mostrado relação positiva e moderada entre a dimensão do crânio e a inteligência medida nos seres humanos. Para tanto, várias variáveis devem ser levadas em consideração na obtenção de tais afirmações. Uma das possibilidades de avaliação das caracteristicas inerentes a estes casos pode ser o uso da análise de regressão múltipla, a qual é utilizada quando se tem o interesse de estudar relações entre uma variável resposta, sobre outras variáveis que influenciam no seu comportamento. Com isso, o objetivo desse trabalho foi verificar se existe relação entre o tamanho do cérebro e o nível de inteligência realizado com dados provenientes de uma pesquisa contendo 40 estudantes do curso de psicologia, com o intuito de ajustar um modelo de regressão linear que melhor se apropriasse aos dados. Realizou-se o teste F de Snedecor e o teste t de Student, para identificar e selecionar o modelo mais adequado, além do critério de informação de Akaike. Após o ajuste do modelo, utilizou-se o fator de inflação de variância e o método de seleção de variáveis Stepwise para identificar quais variáveis independentes eram significativas para representar a variável dependente nível de inteligência. Em seguida, verificou-se as pressuposições e constatou-se por meio dos testes que o modelo ajustado é confiável. O modelo ajustado conteve as variáveis regressoras gênero, pontuação de coeficiente de inteligência de desempenho com base no quatro Wechsler (PIQ), altura.
2005 13th European Signal Processing Conference, 2005
In this paper the performance and implementation cost of three different fine time synchronizatio... more In this paper the performance and implementation cost of three different fine time synchronization algorithms have been evaluated for their use in WLANs. In order to evaluate the performance, the residual time offset after fine time synchronization have been calculated. A hardware structure has been proposed for each algorithm and some simplifications are added that reduce the hardware cost without performance reduction. A Virtex II FPGA device has been selected as a target technology for the implementation. The results indicate that a cross-correlation algorithm with only 28 coefficients achieves the lowest hardware cost with similar performance with respect to the others algorithms.
Quantum processors need to improve their reliability to scale up the number of qubits and increas... more Quantum processors need to improve their reliability to scale up the number of qubits and increase the number of algorithms that can execute. To reduce the logical error rate of the quantum systems, the use of error correction codes and decoders has been established as a low-cost and feasible approach, with good results from a theoretical perspective, for mid and long-term architectures. While most of the authors are focused on the algorithms to improve the correction capability of quantum computers, without taking into account a fundamental implementation aspect for their deployment in a real system, i.e., their latency must be bounded to avoid the qubit decoherence, only a few propose hardware architectures and they just include time estimations of their decoding latency. However, a real implementation has not been shown yet. In this work, we analyze from the point of view of hardware implementation two algorithmic options based on quantum low-density parity-check (QLDPC) codes: a) belief propagation min-sum decoders combined with codes with good error-floor behavior and b) belief propagation min-sum decoders concatenated with ordered statistics decoders (OSDs) for codes with early error-floor. The bounds for the maximum clock frequency required by the decoders to decode within the qubit coherence time are established as a parameter to show if a practical implementation is possible with the present or near future FPGA technology. Furthermore, real implementation results for a Xilinx FPGA device are provided, showing that some solutions can meet the timing constraints set up by the state-of-the-art quantum processors.
Recently, Half-Cycle Nyquist Subcarrier Modulation (HC-SCM) was proposed to achieve high spectral... more Recently, Half-Cycle Nyquist Subcarrier Modulation (HC-SCM) was proposed to achieve high spectral efficiency in intensity-modulator direct-detection optical links. This paper shows that the HC-SCM scheme has a high computational load and proposes the rational Oversampled Subcarrier Modulation (OVS-SCM) as a computational efficient alternative that, furthermore, improves the spectral efficiency. The presented experimental results show that our 256-QAM proposal allows to transmit below the hard-decision forward error correction, with a throughput of 17.8 Gb/s in a 2.5 GHz bandwidth, and a spectral efficiency of 7.2 b/s/Hz, through 20 km of single-mode optical fiber.
This paper presents the hardware architecture of an OFDM receiver suitable for optical communicat... more This paper presents the hardware architecture of an OFDM receiver suitable for optical communications. The receiver has been implemented in an FPGA device and used to demonstrate experimentally an optical OFDM transmission in a passive optical link with a directly modulated DFB laser and DAC/ADC at 5 GS/s. A bit rate of 20.37 Gb/s is achieved using an OFDM signal with subcarrier modulation format up to 512-QAM, it has been successfully transmitted over 10 km SSMF with a spectral efficiency of 8.38 bit/s/Hz.
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018
This work presents a Low-Complexity Chase (LCC) Decoder for Reed-Solomon (RS) codes, which uses a... more This work presents a Low-Complexity Chase (LCC) Decoder for Reed-Solomon (RS) codes, which uses a novel method for the selection of test vectors that is based on the analysis of the symbol error probabilities derived from simulations. Our results show that the same performance as the classical LCC is achieved with a lower number of test vectors. For example, the amount of test vectors is reduced by half and by 1/16 for the RS(255,239) and RS(255,129) codes, respectively. We provide evidence that the proposed method is suitable for RS codes with different rates and Galois Fields. In order to demonstrate that the proposed method results in a reduction of the complexity of the decoder, we also present a hardware architecture for an RS(255,239) decoder that uses 16 test vectors. This decoder achieves a coding gain of 0.56 dB at FER=10 −6 compared to hard-decision decoding, which is higher than that of an η=5 LCC. The implementation results in ASIC show that a throughput of 3.6 Gbps can be reached in a 90 nm process and 29.1 KXORs are required. The implementation results in Virtex-7 FPGA devices show that the decoder reaches 2.5 Gbps and requires 5085 LUTs.
The transmission rate in current passive optical networks can be increased by employing Orthogona... more The transmission rate in current passive optical networks can be increased by employing Orthogonal Frequency Division Multiplexing (OFDM) modulation. The computational kernel of this modulation is the fast Fourier transform (FFT) operator, which has to achieve a very high throughput in order to be used in optical networks. This paper presents the implementation in an FPGA device of a variable-length FFT that can be configured in run-time to compute different FFT lengths between 16 and 1024 points. The FFT reaches a throughput of 10 GS/s in a Virtex-7 485T-3 FPGA device and was used to implement a 20 Gb/s optical OFDM receiver.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017
The computation of the arctangent of a complex number, i.e. the atan2 function, is frequently nee... more The computation of the arctangent of a complex number, i.e. the atan2 function, is frequently needed in hardware systems that could profit from an optimized operator. In the present work we present a novel method to compute the atan2 function and a hardware architecture for its implementation. The method is based on a First Stage that performs a coarse approximation of the atan2 function and a Second Stage that improves the output accuracy by means of a look-up table. We present results for fixedpoint implementations in an FPGA device, all of them guaranteeing last-bit-accuracy, which provide an advantage in latency, speed and use of resources, when compared with well-established fixed-point options.
This paper presents a study of the suitability for FPGA design of full custom based CORDIC implem... more This paper presents a study of the suitability for FPGA design of full custom based CORDIC implementations. Since all these methods are based on redundant arithmetic, the FPGA implementation of the required operators to perform the different CORDIC methods has been evaluated. Efficient mappings on FPGA have been performed leading to the fastest implementations. It is concluded that the redundant arithmetic operators require a 4 to 5 times larger area than the conventional architecture and the speed advantages of the full custom design has been lost. That is due to the longer routing delays caused by the increase of the fan-out and the number of nets. Therefore, the redundant arithmetic based CORDIC methods are not suitable for FPGA implementation, and the conventional two's complement architecture leads to the best performance.
In this paper, a set of operators suitable for digit-serial FIR filtering is presented. The canon... more In this paper, a set of operators suitable for digit-serial FIR filtering is presented. The canonical and inverted forms are studied. In each of these structures both the symmetrical and anti-symmetrical particular cases are also covered. All circuits have been implemented using an EPF10K50 Altera FPGA. Main results show that the canonical form presents the less occupation and the higher throughput. The 8-tap filter versions implemented can be applied in real-time processing with sample rate ranging up to 7MHz using the bit-serial versions and up to 25 MHz with the bit-parallel ones.
ABSTRACT This paper presents an implementation in FPGA of a MIMO-OFDM Zero Forcing decoder based ... more ABSTRACT This paper presents an implementation in FPGA of a MIMO-OFDM Zero Forcing decoder based on QR decomposition. The implemented decoder uses CORDIC in its algorithm, and works under the HIPERLAN/2 and IEEE802.11a standards specifications.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016
Non-binary LDPC codes outperform its binary counterparts in different scenarios. However, they re... more Non-binary LDPC codes outperform its binary counterparts in different scenarios. However, they require a considerable increase in complexity, especially in the check-node processor, for high-order Galois fields higher than GF(16). To overcome this drawback, we propose an approximation for the Trellis Min-Max algorithm which allows us to reduce the number of exchanged messages between check node and variable node compared to previous proposals from literature. On the other hand, we reduce the complexity in the check-node processor, keeping the parallel computation of messages. We implemented a layered scheduled decoder, based on this algorithm, in a 90nm CMOS technology for the (837,723) NB-LDPC code over GF(32) and the (1536,1344) over GF(64), achieving an area saving of 16% and 36% for the check-node and 10% and 12% for the whole decoder, respectively. The throughput is 1.07 Gbps and 1.26 Gbps, which outperforms the state-of-the-art of high-rate decoders with high GF order from literature.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016
This paper presents a novel algorithm based on Trellis Min-Max for decoding NB-LDPC codes. This d... more This paper presents a novel algorithm based on Trellis Min-Max for decoding NB-LDPC codes. This decoder reduces the number of messages exchanged between check node and variable node processors, which decreases the storage resources and the wiring congestion and, thus, increases the throughput of the decoder. Our Frame Error Rate (FER) performance simulations show that the proposed algorithm has a negligible performance loss for high-rate codes with GF(16) and GF(32), and a performance loss smaller than 0.07dB for high-rate codes over GF(64). Additionally, a layered decoder architecture is presented and implemented on a 90nm CMOS process for the following high-rate NB-LDPC codes: (2304, 2048) over GF( ), (837, 726) over GF(32) and (1536, 1344) over GF (64). In all cases the achieved throughput is higher than 1Gbps.
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015
A high-speed non-binary LDPC decoder based on Trellis Min-Max algorithm with layered schedule is ... more A high-speed non-binary LDPC decoder based on Trellis Min-Max algorithm with layered schedule is presented. The proposed approach compresses the check-node output messages into a reduced set, decreasing the number of messages sent to the variable node. Additionally, the memory resources from the layered architecture are reduced. The proposed decoder was implemented for the (2304,2048) NB-LDPC code over GF( ) on a Virtex-7 FPGA and in a 90 nm CMOS process. Our implementation outperforms state-of-the-art NB-LDPC decoder implementations for both technologies, achieving a throughput of 630 and 965 Mbps, respectively.
2018 16th IEEE International New Circuits and Systems Conference (NEWCAS), 2018
In this work we present a novel architecture for a soft-decision Reed-Solomon LCC decoder. In our... more In this work we present a novel architecture for a soft-decision Reed-Solomon LCC decoder. In our decoder the data sorted and stored in the Multiplicity Assignment stage are different from other authors’ work. We present architectures for the Syndrome Update and Symbol Modification blocks that are adapted to the proposed sorting stage. We present implementation results for ASIC and FPGA that show that this architecture can reach high performance and low latency when compared with similar decoders. For example, in ASIC, our decoder requires 40% less area than a specific state-of-the-art decoder, while still has 40% higher throughput and 0.07 dB coding gain over that decoder.
2004 IEEE 15th International Symposium on Personal, Indoor and Mobile Radio Communications (IEEE Cat. No.04TH8754)
This paper deals with the design and implementation of a frame, time and frequency synchronizer f... more This paper deals with the design and implementation of a frame, time and frequency synchronizer for both Hiperlan/2 and IEEE 802.11a WLAN standards. In a packet oriented system, to perform a quick and correct synchronization it is critical to avoid severe bit error rate degradation. So, the design of this subsystem is one of the most challenging tasks to be
A realização deste trabalho tornou-se possível devido a colaboração primordial do nosso pai, Deus... more A realização deste trabalho tornou-se possível devido a colaboração primordial do nosso pai, Deus, que está no comando de tudo, sendo autor e consumador de nossa capacidade intelectual. Aos meus amados pais José Cardoso Taveira e Jeruza de Paula Taveira, pela transmissão exacerbada de carinho, amor e motivação durante minha formação acadêmica. As minhas apreciadas irmãs Ana Lídia de Paula Taveira Henriques e Lidiane de Paula Taveira, pela compreensão na minha ausência em momentos especiais da nossa vida. a . Dr a . Ana Patrícia Bastos Peixoto e Prof o . Dr. Tiago Almeida de Oliveira, pela expressiva competência, disposição e auxílio durante a elaboração deste trabalho. Aos membros da banca examinadora formada pelo Prof o . Dr. Ricardo Alves de Olinda e Prof a . Wanessa Weridiana da Luz Freitas por participarem como interlocutores desse trabalho, contribuindo assim para o enriquecimento teórico do mesmo. Aos meus amigos, do Curso Bacharelado em Estatística, em especial, Rosendo Chagas, Fábio Sandro Dos Santos, Leomir Ferreira Sousa pelo constante apoio e estímulo transmitido durante a construção das atividades teóricas e práticas do trabalho em epígrafe. A todos o meu sincero agradecimento. Alguns estudos tem mostrado relação positiva e moderada entre a dimensão do crânio e a inteligência medida nos seres humanos. Para tanto, várias variáveis devem ser levadas em consideração na obtenção de tais afirmações. Uma das possibilidades de avaliação das caracteristicas inerentes a estes casos pode ser o uso da análise de regressão múltipla, a qual é utilizada quando se tem o interesse de estudar relações entre uma variável resposta, sobre outras variáveis que influenciam no seu comportamento. Com isso, o objetivo desse trabalho foi verificar se existe relação entre o tamanho do cérebro e o nível de inteligência realizado com dados provenientes de uma pesquisa contendo 40 estudantes do curso de psicologia, com o intuito de ajustar um modelo de regressão linear que melhor se apropriasse aos dados. Realizou-se o teste F de Snedecor e o teste t de Student, para identificar e selecionar o modelo mais adequado, além do critério de informação de Akaike. Após o ajuste do modelo, utilizou-se o fator de inflação de variância e o método de seleção de variáveis Stepwise para identificar quais variáveis independentes eram significativas para representar a variável dependente nível de inteligência. Em seguida, verificou-se as pressuposições e constatou-se por meio dos testes que o modelo ajustado é confiável. O modelo ajustado conteve as variáveis regressoras gênero, pontuação de coeficiente de inteligência de desempenho com base no quatro Wechsler (PIQ), altura.
2005 13th European Signal Processing Conference, 2005
In this paper the performance and implementation cost of three different fine time synchronizatio... more In this paper the performance and implementation cost of three different fine time synchronization algorithms have been evaluated for their use in WLANs. In order to evaluate the performance, the residual time offset after fine time synchronization have been calculated. A hardware structure has been proposed for each algorithm and some simplifications are added that reduce the hardware cost without performance reduction. A Virtex II FPGA device has been selected as a target technology for the implementation. The results indicate that a cross-correlation algorithm with only 28 coefficients achieves the lowest hardware cost with similar performance with respect to the others algorithms.
Quantum processors need to improve their reliability to scale up the number of qubits and increas... more Quantum processors need to improve their reliability to scale up the number of qubits and increase the number of algorithms that can execute. To reduce the logical error rate of the quantum systems, the use of error correction codes and decoders has been established as a low-cost and feasible approach, with good results from a theoretical perspective, for mid and long-term architectures. While most of the authors are focused on the algorithms to improve the correction capability of quantum computers, without taking into account a fundamental implementation aspect for their deployment in a real system, i.e., their latency must be bounded to avoid the qubit decoherence, only a few propose hardware architectures and they just include time estimations of their decoding latency. However, a real implementation has not been shown yet. In this work, we analyze from the point of view of hardware implementation two algorithmic options based on quantum low-density parity-check (QLDPC) codes: a) belief propagation min-sum decoders combined with codes with good error-floor behavior and b) belief propagation min-sum decoders concatenated with ordered statistics decoders (OSDs) for codes with early error-floor. The bounds for the maximum clock frequency required by the decoders to decode within the qubit coherence time are established as a parameter to show if a practical implementation is possible with the present or near future FPGA technology. Furthermore, real implementation results for a Xilinx FPGA device are provided, showing that some solutions can meet the timing constraints set up by the state-of-the-art quantum processors.
Recently, Half-Cycle Nyquist Subcarrier Modulation (HC-SCM) was proposed to achieve high spectral... more Recently, Half-Cycle Nyquist Subcarrier Modulation (HC-SCM) was proposed to achieve high spectral efficiency in intensity-modulator direct-detection optical links. This paper shows that the HC-SCM scheme has a high computational load and proposes the rational Oversampled Subcarrier Modulation (OVS-SCM) as a computational efficient alternative that, furthermore, improves the spectral efficiency. The presented experimental results show that our 256-QAM proposal allows to transmit below the hard-decision forward error correction, with a throughput of 17.8 Gb/s in a 2.5 GHz bandwidth, and a spectral efficiency of 7.2 b/s/Hz, through 20 km of single-mode optical fiber.
This paper presents the hardware architecture of an OFDM receiver suitable for optical communicat... more This paper presents the hardware architecture of an OFDM receiver suitable for optical communications. The receiver has been implemented in an FPGA device and used to demonstrate experimentally an optical OFDM transmission in a passive optical link with a directly modulated DFB laser and DAC/ADC at 5 GS/s. A bit rate of 20.37 Gb/s is achieved using an OFDM signal with subcarrier modulation format up to 512-QAM, it has been successfully transmitted over 10 km SSMF with a spectral efficiency of 8.38 bit/s/Hz.
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018
This work presents a Low-Complexity Chase (LCC) Decoder for Reed-Solomon (RS) codes, which uses a... more This work presents a Low-Complexity Chase (LCC) Decoder for Reed-Solomon (RS) codes, which uses a novel method for the selection of test vectors that is based on the analysis of the symbol error probabilities derived from simulations. Our results show that the same performance as the classical LCC is achieved with a lower number of test vectors. For example, the amount of test vectors is reduced by half and by 1/16 for the RS(255,239) and RS(255,129) codes, respectively. We provide evidence that the proposed method is suitable for RS codes with different rates and Galois Fields. In order to demonstrate that the proposed method results in a reduction of the complexity of the decoder, we also present a hardware architecture for an RS(255,239) decoder that uses 16 test vectors. This decoder achieves a coding gain of 0.56 dB at FER=10 −6 compared to hard-decision decoding, which is higher than that of an η=5 LCC. The implementation results in ASIC show that a throughput of 3.6 Gbps can be reached in a 90 nm process and 29.1 KXORs are required. The implementation results in Virtex-7 FPGA devices show that the decoder reaches 2.5 Gbps and requires 5085 LUTs.
The transmission rate in current passive optical networks can be increased by employing Orthogona... more The transmission rate in current passive optical networks can be increased by employing Orthogonal Frequency Division Multiplexing (OFDM) modulation. The computational kernel of this modulation is the fast Fourier transform (FFT) operator, which has to achieve a very high throughput in order to be used in optical networks. This paper presents the implementation in an FPGA device of a variable-length FFT that can be configured in run-time to compute different FFT lengths between 16 and 1024 points. The FFT reaches a throughput of 10 GS/s in a Virtex-7 485T-3 FPGA device and was used to implement a 20 Gb/s optical OFDM receiver.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017
The computation of the arctangent of a complex number, i.e. the atan2 function, is frequently nee... more The computation of the arctangent of a complex number, i.e. the atan2 function, is frequently needed in hardware systems that could profit from an optimized operator. In the present work we present a novel method to compute the atan2 function and a hardware architecture for its implementation. The method is based on a First Stage that performs a coarse approximation of the atan2 function and a Second Stage that improves the output accuracy by means of a look-up table. We present results for fixedpoint implementations in an FPGA device, all of them guaranteeing last-bit-accuracy, which provide an advantage in latency, speed and use of resources, when compared with well-established fixed-point options.
This paper presents a study of the suitability for FPGA design of full custom based CORDIC implem... more This paper presents a study of the suitability for FPGA design of full custom based CORDIC implementations. Since all these methods are based on redundant arithmetic, the FPGA implementation of the required operators to perform the different CORDIC methods has been evaluated. Efficient mappings on FPGA have been performed leading to the fastest implementations. It is concluded that the redundant arithmetic operators require a 4 to 5 times larger area than the conventional architecture and the speed advantages of the full custom design has been lost. That is due to the longer routing delays caused by the increase of the fan-out and the number of nets. Therefore, the redundant arithmetic based CORDIC methods are not suitable for FPGA implementation, and the conventional two's complement architecture leads to the best performance.
In this paper, a set of operators suitable for digit-serial FIR filtering is presented. The canon... more In this paper, a set of operators suitable for digit-serial FIR filtering is presented. The canonical and inverted forms are studied. In each of these structures both the symmetrical and anti-symmetrical particular cases are also covered. All circuits have been implemented using an EPF10K50 Altera FPGA. Main results show that the canonical form presents the less occupation and the higher throughput. The 8-tap filter versions implemented can be applied in real-time processing with sample rate ranging up to 7MHz using the bit-serial versions and up to 25 MHz with the bit-parallel ones.
ABSTRACT This paper presents an implementation in FPGA of a MIMO-OFDM Zero Forcing decoder based ... more ABSTRACT This paper presents an implementation in FPGA of a MIMO-OFDM Zero Forcing decoder based on QR decomposition. The implemented decoder uses CORDIC in its algorithm, and works under the HIPERLAN/2 and IEEE802.11a standards specifications.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016
Non-binary LDPC codes outperform its binary counterparts in different scenarios. However, they re... more Non-binary LDPC codes outperform its binary counterparts in different scenarios. However, they require a considerable increase in complexity, especially in the check-node processor, for high-order Galois fields higher than GF(16). To overcome this drawback, we propose an approximation for the Trellis Min-Max algorithm which allows us to reduce the number of exchanged messages between check node and variable node compared to previous proposals from literature. On the other hand, we reduce the complexity in the check-node processor, keeping the parallel computation of messages. We implemented a layered scheduled decoder, based on this algorithm, in a 90nm CMOS technology for the (837,723) NB-LDPC code over GF(32) and the (1536,1344) over GF(64), achieving an area saving of 16% and 36% for the check-node and 10% and 12% for the whole decoder, respectively. The throughput is 1.07 Gbps and 1.26 Gbps, which outperforms the state-of-the-art of high-rate decoders with high GF order from literature.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016
This paper presents a novel algorithm based on Trellis Min-Max for decoding NB-LDPC codes. This d... more This paper presents a novel algorithm based on Trellis Min-Max for decoding NB-LDPC codes. This decoder reduces the number of messages exchanged between check node and variable node processors, which decreases the storage resources and the wiring congestion and, thus, increases the throughput of the decoder. Our Frame Error Rate (FER) performance simulations show that the proposed algorithm has a negligible performance loss for high-rate codes with GF(16) and GF(32), and a performance loss smaller than 0.07dB for high-rate codes over GF(64). Additionally, a layered decoder architecture is presented and implemented on a 90nm CMOS process for the following high-rate NB-LDPC codes: (2304, 2048) over GF( ), (837, 726) over GF(32) and (1536, 1344) over GF (64). In all cases the achieved throughput is higher than 1Gbps.
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015
A high-speed non-binary LDPC decoder based on Trellis Min-Max algorithm with layered schedule is ... more A high-speed non-binary LDPC decoder based on Trellis Min-Max algorithm with layered schedule is presented. The proposed approach compresses the check-node output messages into a reduced set, decreasing the number of messages sent to the variable node. Additionally, the memory resources from the layered architecture are reduced. The proposed decoder was implemented for the (2304,2048) NB-LDPC code over GF( ) on a Virtex-7 FPGA and in a 90 nm CMOS process. Our implementation outperforms state-of-the-art NB-LDPC decoder implementations for both technologies, achieving a throughput of 630 and 965 Mbps, respectively.
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Papers by Javier Valls