This paper proposes a complete hardware solution for embedded systems that fully protects off-chi... more This paper proposes a complete hardware solution for embedded systems that fully protects off-chip memory. Our security core is based on one-time pad (OTP) encryption and a CRC32 integrity check module. These modules safeguard external memories for embedded processors against a series of well-known attacks, including replay attacks, spoofing attacks and relocation attacks. The implementation limits memory space overhead to about 18.75% and reduces memory latency from 14 cycles for a alternate approach to 3 clock cycles. A FPGA-based implementation of the security core has been completed to gauge the security overhead and to compare our approach with existing solutions.
Nowadays, security is a key constraint in MPSoC development as many critical and secret informati... more Nowadays, security is a key constraint in MPSoC development as many critical and secret information can be stored and manipulated within these systems. One strategic point of a bus-based MPSoC is the communication architecture as all data goes through it. Most solutions are currently built at the software level; we believe hardware enhancements also play a major role in system protection. Our approach relies on low complexity distributed security filters connected to all critical IPs of the system. Implementations on a Xilinx xc6vlx240t Virtex-6 FPGA show a latency decrease of 33 % compared to existing efforts while a reconfigurable version of such security services gives a 37% area overhead on a simple dual-processor case study with a 33% latency decrease on a sample image processing application.
Nous présentons une architecture matérielle et logicielle ainsi qu'une implémentation de protocol... more Nous présentons une architecture matérielle et logicielle ainsi qu'une implémentation de protocole réseau destinées à la reconfiguration dynamique partielle de FPGA dans le but d'obtenir des systèmes "ultra-légers reconfigurables à distance". Ces systèmes sont destinés aux applications embarquées ayant très peu de ressources matérielles et tirant profit d'architectures dédiées. Ils sont fondés sur un simple FPGA associé à son contrôleur réseau, et ne requièrent pas de mémoires externes pour stocker le code de l'exécutif temps réel, ni les tampons mémoires des protocoles de communication. Nos mesures prouvent que nos systèmes ultra-légers atteignent des débits de reconfiguration au moins dix fois plus rapides que les meilleurs actuels.
In the scope of the RNRT A3S project, we are addressing the issue of a priori verifying right at ... more In the scope of the RNRT A3S project, we are addressing the issue of a priori verifying right at the architectural design stage, the adequacy of waveform applications deployment on a hardware platform through the verification of functional requirement and architectural features (timing, latency, bandwidth, …). Even if this issue is transversal to various domains, we are specifically addressing the software radio domain. The result of such a project will be a set of UML tools being able to predict by comparing the UML models if a waveform will execute properly on a specific platform in terms of performances, those tools will be implemented in a UML toolbox for demonstration and validation purposes.
This paper describes a co-design course that is performed within the Université de Bretagne Sud i... more This paper describes a co-design course that is performed within the Université de Bretagne Sud in Lorient, France. The objective of this course is to improve the students embedded system design skills through a pedagogical application. The course starts with a lecture about general concepts and tools in the domain of Electronic System Level design. Two axis are followed: firstly co-design and high level synthesis concepts are presented and secondly new architectures offered by embedded systems are described. Throughout this course, a lab provides the students with practical experiences in designing HW systems and SW tasks. The students explore different architecture alternatives, implement them and evaluate impact of their choices in terms of performance and flexibility. Finally, a design contest concludes the course. The main objective is to design the fastest allele search embedded system.
To answer to the security needs of modern military communication systems, this paper presents a m... more To answer to the security needs of modern military communication systems, this paper presents a multi-core architecture for cryptographic processors. This architecture is especially designed for use in multi-channel Software Defined Radio devices. It provides support for GCM, CCM, CTR and other block cipher modes applied to AES algorithm. It can reach a maximum throughput of nearly 2 Gbps.
This paper proposes a complete hardware solution for embedded systems that fully protects off-chi... more This paper proposes a complete hardware solution for embedded systems that fully protects off-chip memory. Our security core is based on one-time pad (OTP) encryption and a CRC32 integrity check module. These modules safeguard external memories for embedded processors against a series of well-known attacks, including replay attacks, spoofing attacks and relocation attacks. The implementation limits memory space overhead to about 18.75% and reduces memory latency from 14 cycles for a alternate approach to 3 clock cycles. A FPGA-based implementation of the security core has been completed to gauge the security overhead and to compare our approach with existing solutions.
Nowadays, security is a key constraint in MPSoC development as many critical and secret informati... more Nowadays, security is a key constraint in MPSoC development as many critical and secret information can be stored and manipulated within these systems. One strategic point of a bus-based MPSoC is the communication architecture as all data goes through it. Most solutions are currently built at the software level; we believe hardware enhancements also play a major role in system protection. Our approach relies on low complexity distributed security filters connected to all critical IPs of the system. Implementations on a Xilinx xc6vlx240t Virtex-6 FPGA show a latency decrease of 33 % compared to existing efforts while a reconfigurable version of such security services gives a 37% area overhead on a simple dual-processor case study with a 33% latency decrease on a sample image processing application.
Nous présentons une architecture matérielle et logicielle ainsi qu'une implémentation de protocol... more Nous présentons une architecture matérielle et logicielle ainsi qu'une implémentation de protocole réseau destinées à la reconfiguration dynamique partielle de FPGA dans le but d'obtenir des systèmes "ultra-légers reconfigurables à distance". Ces systèmes sont destinés aux applications embarquées ayant très peu de ressources matérielles et tirant profit d'architectures dédiées. Ils sont fondés sur un simple FPGA associé à son contrôleur réseau, et ne requièrent pas de mémoires externes pour stocker le code de l'exécutif temps réel, ni les tampons mémoires des protocoles de communication. Nos mesures prouvent que nos systèmes ultra-légers atteignent des débits de reconfiguration au moins dix fois plus rapides que les meilleurs actuels.
In the scope of the RNRT A3S project, we are addressing the issue of a priori verifying right at ... more In the scope of the RNRT A3S project, we are addressing the issue of a priori verifying right at the architectural design stage, the adequacy of waveform applications deployment on a hardware platform through the verification of functional requirement and architectural features (timing, latency, bandwidth, …). Even if this issue is transversal to various domains, we are specifically addressing the software radio domain. The result of such a project will be a set of UML tools being able to predict by comparing the UML models if a waveform will execute properly on a specific platform in terms of performances, those tools will be implemented in a UML toolbox for demonstration and validation purposes.
This paper describes a co-design course that is performed within the Université de Bretagne Sud i... more This paper describes a co-design course that is performed within the Université de Bretagne Sud in Lorient, France. The objective of this course is to improve the students embedded system design skills through a pedagogical application. The course starts with a lecture about general concepts and tools in the domain of Electronic System Level design. Two axis are followed: firstly co-design and high level synthesis concepts are presented and secondly new architectures offered by embedded systems are described. Throughout this course, a lab provides the students with practical experiences in designing HW systems and SW tasks. The students explore different architecture alternatives, implement them and evaluate impact of their choices in terms of performance and flexibility. Finally, a design contest concludes the course. The main objective is to design the fastest allele search embedded system.
To answer to the security needs of modern military communication systems, this paper presents a m... more To answer to the security needs of modern military communication systems, this paper presents a multi-core architecture for cryptographic processors. This architecture is especially designed for use in multi-channel Software Defined Radio devices. It provides support for GCM, CCM, CTR and other block cipher modes applied to AES algorithm. It can reach a maximum throughput of nearly 2 Gbps.
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Papers by Guy Gogniat