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The Network-on-Chip (NoC) provides a viable solution to bus-contention problems in classical Multi/Many core architectures. However, NoC complex design requires particular attention to support the execution of real-time workloads. In fact, it is necessary to take into account task-to-core allocation and inter-task communication, so that all timing constraints are respected. The problem is more complex when considering task-to-main-memory communication, as the main memory is off-chip and usually connected to the network edges, within the 2D-Mesh topology, which generates a particular additional pattern of traffic. In this paper, we tackle these problems by considering the allocation of tasks and inter-taskcommunications, and memory-to-task communications (modeled using Directed Acyclic Graphs DAGs) at the same time, rather than separating them, as it has been addressed in the literature of real-time systems. This problem is highly combinatorial, therefore our approach transforms it at each step, to a simpler problem until reaching the classical single-core scheduling problem. The goal is to find a trade-off between the problem combinatorial explosion and the loss of generality when simplifying the problem. We study the effectiveness of the proposed approaches using a large set of synthetic experiments.

Three‐dimensional Network‐on‐Chip (3D NoC) is a promising solution for solving 2D NoC problems while optimizing the system's performance. Mapping applications in 3D NoC is a crucial step as it has a significant impact on overall system performance. Moreover, multi‐task supported processing elements (PEs) are needed to run multiple applications and provide more scalability. Most of the existing 3D mapping approaches consider only the single‐task platform. In this paper, we propose an efficient multi‐task mapping algorithm targeting regular 3D NoC that allows an incremental mapping and parallel execution of many applications onto different partitions on the 3D NoC. The proposed mapping algorithm is composed of three main steps aiming to reduce the communications overhead, exploiting the benefits of vertical links and improving the performances. The algorithm has been evaluated with various random and realistic benchmarks and compared with existing mapping algorithms for 3D NoC. Th...

This paper describes a new Spiral Dynamic Task Mapping heuristic for mapping applications onto NoC-based Heterogeneous MPSoC. The heuristic proposed in this paper attempts to map the tasks of an applications that are most related to each other in spiral manner and to find the best possible path load that minimizes the communication overhead. In this context, we have realized a simulation environment for experimental evaluations to map applications with varying number of tasks onto an 8x8 NoC-based Heterogeneous MPSoCs platform, we demonstrate that the new mapping heuristics with the new modified dijkstra routing algorithm proposed are capable of reducing the total execution time and energy consumption of applications when compared to state-of the-art run-time mapping heuristics reported in the literature.

To fulfill the need of intensive embedded computations, architects have proposed Network-on-Chip based Multi-Processor Systems-on-Chip. Applications exploit the distinct features of the different types of processors in Multi-Processor Systems-on-Chip to optimize the performance metrics: overall execution time, energy consumption, resource usage, etc. Application designers often map statically the tasks on the processors. This static mapping cannot handle many kinds of applications such as those with dynamic workloads and one must use dynamic mapping when several applications run concurrently. As such, there has been an increased need for defining and developing simulation software for carrying out a simulation of the proposed dynamic Mapping heuristics to the NoC-based MPSoC architectures. In this paper, we present DynMapNoCSIM, a JAVA based Dynamic Mapping simulator for NoC-based MPSoC architecture, which builds upon the objectoriented modular design of the NoC-based MPSoC architecture components. Here we demonstrate the use of our proposed simulator by providing a conceptual detail. We have also presented all the features offered. Finally, we have validated the outputs of DynMapNoCSIM with the studies of existing and proposed Dynamic mapping strategies.

Multi-processor system-on-chip (MPSoC) has emerged as a solution to address the increased computational requirements of modern applications. The network-on-chip (NoC) has been introduced as a power-efficient and scalable communication infrastructure between processors. One important phase in architectural exploration in NoC-based MPSoC is the communications mapping. Mapping parallelised communications of tasks onto these MPSoCs can be done either by static or dynamic routing. Static communication mapping strategies find the fixed placement of communications like XY routing and hence, these are not suitable to achieve high overall performance. The number of tasks or applications executing in MPSoC platform can exceed the available resources, requiring multi-tasking platform. In this paper, we propose a newly dynamic communications mapping strategy for efficient communication between the PEs of MPSoC, where each PE support multiple tasks and shared memory is used for the communications between the tasks mapped in the same PE. The strategy considers efficient placement of communications in order to optimise the overall performance. Experimental results show that the proposed mapping approach provides significant performance improvements when compared to those using static routing.

This paper presents Real-Time Network-on-chip-based architecture Analysis and Simulation tool (ReTiNAS), with a special focus on real-time communications. It allows fast and precise exploration of real-time design choices onto NoC architectures. ReTiNAS is an event-based simulator written in Python. It implements different real-time communication protocols and tracks the communications within the NoC at cycle level. Its modularity allows activating and deactivating different NoC components and easily extending the implemented protocols for more customized simulations and analysis. Further, we use ReTiNAS to perform a comparative study of analysis and simulation for different communication protocols using a wide set of synthetic experiments.

HAL is a multi-disciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L’archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d’enseignement et de recherche français ou étrangers, des laboratoires publics ou privés. Placement Dynamique D’Applications Embarquées Intensives sur des Réseaux de Processeurs sur Puce Mohammed Kamal Benhaoua

Deferred-preemption model has been proposed as a compromise between fully preemptive and non-preemptive systems: on one hand they reduce the cache related preemption delays; on the other hand they introduce a small blocking time to higher priority tasks. In this paper, we investigate the problem of allocating a set of real-time tasks with fixed-preemption points onto an identical multi-core platform. We first propose enumerative and branch-and-bound optimal algorithms, along with techniques to reduce their execution time. Further, we propose a set of heuristics to solve the same problem. We demonstrate the performances of the proposed approaches by the means of a large set of synthetic experiments.

The Network-on-Chip (NoC) is an alternative pattern that is considered as an emerging technology for distributed embedded systems. The traditional use of multi-cores in computing increase the calculation performance; but affect the network communication causing congestion on nodes which therefore decrease the global performance of the NoC. To alleviate this problematic phenomenon, several strategies were implemented, to reduce or prevent the occurrence of congestion, such as network status metrics, new routing algorithm, packets injection control, and switching strategies. In this paper, we carried out a study on congestion in a 2D mesh network, through various detailed simulations. Our focus was on the most used congestion metrics in NoC. According to our experiments and performed simulations under different traffic scenarios, we found that these metrics are less representative, less significant and yet they do not give a true overview of reading within the NoC nodes at a given cyc...

In this paper, we propose a new packing strategy to<br> find a free resource for run-time mapping of application tasks to<br> NoC-based Heterogeneous MPSoC. The proposed strategy minimizes<br> the task mapping time in addition to placing the communicating tasks<br> close to each other. To evaluate our approach, a comparative study is<br> carried out for a platform containing single task supported PEs.<br> Experiments show that our strategy provides better results when<br> compared to latest dynamic mapping strategies reported in the<br> literature.

Neuromorphic architectures are one of the most promising architectures to significantly reduce the energy consumption of tomorrow's computers. These architectures are inspired by the behaviour of the brain at a fairly precise level and consist of artificial Spiking Neural Networks (SNNs). To optimise the implementation of these architectures, we propose in this paper a novel progressive network compression and reinforcement technique based on two functions, progressive pruning and dynamic synaptic weight reinforcement used after each training batch. The proposed approach delivers a highly compressed network (up to 75 % of compression rate) while preserving the network performance when tested with MNIST.

In this paper, we address the problem of analyzing the behavior of a set of real-time tasks on a Network-on-chipbased (NoC) architecture. Our approach is to transform the allocation of tasks and communications within a NoC into a classical real-time allocation problem. It provides an extension of classical bin-packing heuristics to allocate a set of real-time applications modeled using a directed acyclic graphs (DAGs) to a set of processors interconnected through a NoC. The paper describes the schedulability analysis, including allocation and communication. It provides also a comparative study of different allocation and communication algorithms and presents accordingly a set of promising research insights.

La résolution des requêtes Top-k est un problème important et difficile dans les systèmes large échelle. Cette résolution se fait par agrégation afin d'optimiser la recherche et de manipuler moins de quantités de données. Dans cet article, nous présentons un nouvel algorithme dans le but de résoudre ce type de problème efficacement. Notre algorithme est composé de trois phases et ne définit qu'un seul seuil, à la différence des autres algorithmes déjà existants. Les simulations sur des collections de données réelles et la comparaison avec des algorithmes très connus montrent que notre solution est très compétitive et plus rapide en temps d'exécution.

The resolution of the Top-k queries is an important and a difficult problem in the large scale systems. Aggregation is the best way to solve this type of queries. It reduces substantially the amount of exchanged data and optimizes the search task. In this paper, we present a new algorithm with the aim of solving this type of problem efficiently. Our algorithm consists of three phases and defines only one threshold, unlike the other already existing algorithms. The simulations on real datasets and the comparison with some other algorithms show that our solution is very competitive. MOTS-CLÉS : agrégation, requêtes Top-k, fonction monotone, seuil, phase, listes triées.

The main objective of this paper is to secure a cross-layer, energy efficient MAC protocol (CL-MAC) dedicated to delay sensitive wireless sensor networks (WSN) for detecting and avoiding wormhole attack. CL-MAC protocol is the result of our previous research works for which the security aspects have not been taken into consideration during its design stage. To formally prove the importance of the proposed scheme, we provide a theoretical study based on Time Petri Net to analyse some important properties related to the devastating effect of the wormhole attack and its countermeasure on the CL-MAC operations. Also, we perform an experimental evaluation through the simulation using realistic scenarios in order to show the performance of the proposal in terms of energy saving, packets loss ratio and latency. The obtained results indicate the usefulness of the formal study provided in this work when applied in security context and confirm clearly a good performance of the proposed scheme against wormhole attack.

Technological Advances in microelectronic and telecommunication fields enable the existence of tiny computing units, very small and more efficient. In the context of these new technologies, Wireless Sensor Networks (WSN) have emerged. The main research objective in WSN domain is the development of algorithms and protocols ensuring minimal energy consumption. Most proposed solutions are based on one-layer stack model approach. Recently, other works tend to exploit together many layers in order to optimize energy consumption. In this paper, we propose a Cross-Layer Medium Access Control (CL-MAC) protocol using two adjacent layers (MAC and Network) to economize energy for WSN. The basic idea behind our protocol is to wake-up only nodes belonging to a routing path from the source to the base station (Sink) by exploiting routing information while other nodes leave maintained as long time as possible in a sleep mode. The protocol is modeled using a time Petri net and validated by TiNA too...

Currently, for various reasons, authorities are facing the problem of locating a particular vehicle. Some cars are equipped by a geographical positioning system (GPS), but fake or those used in criminal acts have their GPS off. Therefore, locating and target tracking in Vehicular ad-hoc networks (VANETs) is gaining more attention in the research field due to all the envisioned applications that rely on it, such as endlessly tracking a particular vehicle knowing only its license plate number. This is a vital and challenging problem to merge with the dynamic nature of VANETs and the high speed of its nodes. In this paper we try to alleviate this problem by proposing a novel infrastructureless and lightweight tracking algorithm that allows authorities to constantly track a target node. Based on the clustering model, nodes surrounding the target have to collaborate to keep the target in sight and continuously inform the control center (the authorities' base station). A performance evaluation of our proposed solution is performed by using the NS2 simulator.

Wireless Sensor Networks (WSN) are expected to operate as long time as possible in all applications and environments. Facing energy challenge, software developers’ have to design save-energy programs. In this paper, an extended version of CL-MAC (CrossLayer-MAC) is slightly presented dealing with packet loss problem modeled using Time Petri net (TPN). TiNA (Time Net Analyzer) tool is used to validate the proposed model. The obtained properties such liveness, boundedness and reversibility prove the correct behavior of the new version of CLMAC where lost packets problem is solved. Basically, CL-MAC protocol was designed to reduce both energy and latency. Its main engine is to wake-up only nodes within the routing path.