Santander

A new methodology is proposed to increase the robustness of pipeline-based circuits. The goal is to improve signal integrity in the presence of powersupply voltage (V DD ) and/or temperature (T) variations, without degrading circuit performance. In the proposed methodology, we dynamically control the instant of data capture (the clock edge trigger) in key memory cells, according to local V DD and/or T variations. This way, data integrity lost is avoided, and circuit tolerance to power supply and/or temperature variations is enhanced. The methodology is based on a Dynamic Delay Buffer (DDB) block, used to sense V DD /T variations and to induce dynamic clock skews driving a limited subset of memory elements. Experimental results based on SPICE simulations for 2 sequential circuits are used to demonstrate that careful design may lead to improvements on circuit tolerance to V DD and/or T variations.

The purpose of this paper is to present and discuss a novel modeling and fault simulation technique for two types of dynamic faults in digital systems: transient power supply voltage drops and transient delays in logic elements or signals paths. Techniques and tools currently used for permanent faults are reused for dynamic (permanent) and intermittent faults. For transient power supply voltage drops (∆V DD ), two approaches are proposed: delay fault injection in all logic elements of the CUT (Circuit Under Test), or modulation of the clock and observation rate. For transient delays (e.g., SEU), single delay injection is performed at logic element level. Delay modulation is carried out by fault injection using the PLI interface of the commercial Verilog simulation tool. Preliminary results, demonstrated by the c7552 ISCAS'85 benchmark circuit, show that CUTs with long critical paths are very sensitive to power supply transients. Moreover, a pseudo-random test pattern can be used to identify the dependence of the CUT sensitivity to delay faults on defect size, for a given clock period, τ o .

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