IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012
We propose a self-contained, flat, forcedirected algorithm for global placement that is simpler t... more We propose a self-contained, flat, forcedirected algorithm for global placement that is simpler than existing placers and easier to integrate into timingclosure flows. It maintains lower-bound and upper-bound placements that converge to a final solution. The upperbound placement is produced by a novel rough legalization algorithm. Our placer SimPL outperforms mPL6, NTUPlace3, FastPlace3, APlace2 and Capo simultaneously in runtime and solution quality, running 6.4 times faster than mPL6 and reducing wirelength by 2% on the ISPD 2005 benchmark suite.
International Conference on Computer Aided Design, Nov 7, 2011
This mini-tutorial covers recent research on clocknetwork tuning. It starts with SPICE-accurate o... more This mini-tutorial covers recent research on clocknetwork tuning. It starts with SPICE-accurate optimizations used in winning entries at the ISPD 2009 and 2010 clock-network synthesis contests. After comparing clock trees to meshes, it outlines a recent redundant clock-network topology that retains most advantages of clock trees, but improves robustness to PVT variations. It also shows how to incorporate clock-network synthesis into global placement to reduce dynamic power and insertion delay.
This work focuses on congestion-driven placement of standard cells into rows in the fixed-die con... more This work focuses on congestion-driven placement of standard cells into rows in the fixed-die context. We summarize the stateof-the-art after two decades of research in recursive bisection placement and implement a new placer, called Capo, to empirically study the achievable limits of the approach. From among recently proposed improvements to recursive bisection, Capo incorporates a leading-edge multilevel min-cut partitioner [7], techniques for partitioning with small tolerance [8], optimal min-cut partitioners and end-case min-wirelength placers [5], previously unpublished partitioning tolerance computations, and block splitting heuristics. On the other hand, our "good enough" implementation does not use "overlapping" [17], multi-way partitioners [17, 20], analytical placement, or congestion estimation [24, 35]. In order to run on recent industrial placement instances, Capo must take into account fixed macros, power stripes and rows with different allowed cell orientations. Capo reads industry-standard LEF/DEF, as well as formats of the GSRC bookshelf for VLSI CAD algorithms [6], to enable comparisons on available placement instances in the fixed-die regime. Capo clearly demonstrates that despite a potential mismatch of objectives, improved mincut bisection can still lead to improved placement wirelength and congestion. Our experiments on recent industrial benchmarks fail to give a clear answer to the question in the title of this paper. However, they validate a series of improvements to recursive bisection and point out a need for transparent congestion management techniques that do not worsen the wirelength of already routable placements. Our experimental flow, which validates fixed-die placement results by violation-free detailed auto-routability, provides a new norm for comparison of VLSI placement implementations.
Many popular algorithms that work with Boolean functions are dramatically dependent on the order ... more Many popular algorithms that work with Boolean functions are dramatically dependent on the order of variables in input representations of Boolean functions. Such algorithms include satisfiability (SAT) solvers that are critical in formal verification and Binary Decision Diagrams (BDDs) manipulation algorithms that are increasingly popular in synthesis and verification. Finding better variable-orderings is a well-recognized problem in each of those contexts. Currently, all leading-edge variable-ordering algorithms are dynamic in the sense that they are invoked many times in the course of the "host" algorithm that solves SAT or manipulates BDDs. Examples include the DLIS ordering for SAT solvers and variable-sifting during BDD manipulations. In this work we propose a universal variable ordering MINCE (MIN Cut Etc.) that preprocesses a given Boolean formula in CNF. MINCE is completely independent from target algorithms and outperforms both DLIS for SAT and variable sifting for BDDs. We argue that MINCE tends to capture structural properties of Boolean functions arising from real-world applications.
International Conference on Computer Aided Design, Nov 4, 2001
The increasing popularity of SAT and BDD techniques in verification and synthesis encourages the ... more The increasing popularity of SAT and BDD techniques in verification and synthesis encourages the search for additional speed-ups. Since typical SAT and BDD algorithms are exponential in the worst-case, the structure of real-world instances is a natural source of improvements. While SAT and BDD techniques are often presented as mutually exclusive alternatives, our work points out that both can be improved via the use of the same structural properties of instances. Our proposed methods are based on efficient problem partitioning and can be easily applied as pre-processing with arbitrary SAT solvers and BDD packages without source code modifications. Finding a better variable-ordering is a well recognized problem for both SAT solvers and BDD packages. Currently, all leading edge variable-ordering algorithms are dynamic, in the sense that they are invoked many times in the course of the "host" algorithm that solves SAT or manipulates BDDs. Examples include the DLCS ordering for SAT solvers and variable-sifting during BDD manipulations. In this work we propose a universal variable-ordering MINCE (MIN Cut Etc.) that pre-processes a given Boolean formula in CNF. MINCE is completely independent from target algorithms and outperforms both DLCS for SAT and variable sifting for BDDs. We argue that MINCE tends to capture structural properties of Boolean functions arising from real-world applications. Our contribution is validated on the ISCAS circuits and the DIMACS benchmarks. Empirically, our technique often outperforms existing techniques by a factor of two or more. Our results motivate search for stronger dynamic ordering heuristics and combined static/dynamic techniques.
Zenodo (CERN European Organization for Nuclear Research), Dec 28, 2004
The increasing popularity of SAT and BDD techniques in formal hardware verification and automated... more The increasing popularity of SAT and BDD techniques in formal hardware verification and automated synthesis of logic circuits encourages the search for additional speedups. Since typical SAT and BDD algorithms are exponential in the worst-case, the structure of realworld instances is a natural source of improvements. While SAT and BDD techniques are often presented as mutually exclusive alternatives, our work points out that both can be improved via the use of the same structural properties of instances. Our proposed methods are based on efficient problem partitioning and can be easily applied as pre-processing with arbitrary SAT solvers and BDD packages without modifying the source code of SAT/BDD tools. Finding a better variable ordering is a well recognized problem for both SAT solvers and BDD packages. Currently, the best variable-ordering algorithms are dynamic, in the sense that they are invoked many times in the course of the host algorithm that solves SAT or manipulates BDDs. Examples include the DLCS ordering for SAT solvers and variable sifting during BDD manipulations. In this work we propose a universal variable-ordering algorithm MINCE (MIN Cut Etc.) that pre-processes a given Boolean formula in CNF. MINCE is completely independent from target SAT algorithms and in some cases outperforms both the variable state independent decaying sum (VSIDS) decision heuristic for SAT and variable sifting for BDDs. We argue that MINCE tends to capture structural properties of Boolean functions arising from real-world applications. Our contribution is validated on the ISCAS circuits and the DIMACS benchmarks. Empirically, our technique often outperforms existing SAT/BDD techniques by a factor of two or more. Our results motivate the search for better dynamic ordering heuristics and combined static/dynamic techniques.
2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)
Performance of modern multi-chip modules, increasingly implemented as interposer solutions, is li... more Performance of modern multi-chip modules, increasingly implemented as interposer solutions, is limited by system-level interconnects. We propose an effective method for optimal wirelength-driven die placement of interposer-based 3D ICs. Our key ideas are to leverage the constraint-satisfaction problem (CSP) formalism in combination with a branch-and-bound (B&B) algorithm, and to develop several novel techniques for early identification and pruning of unpromising configurations. Such techniques are crucial for addressing the combinatorial explosion when solving the NP-hard placement problem. Experiments on ISPD08 (modified) and MCNC benchmarks demonstrate that our method outperforms prior art: we can optimally place up to eleven rotatable dies, whereas state-of-the-art tools are limited to six dies.
The increasing popularity of SAT and BDD techniques in formal hardware verifica- tion and automat... more The increasing popularity of SAT and BDD techniques in formal hardware verifica- tion and automated synthesis of logic circuits encourages the search for additional speedups. Since typical SAT and BDD algorithms are exponential in the worst-case, the structure of real- world instances is a natural source of improvements. While SAT and BDD techniques are often presented as mutually exclusive alternatives, our work points out that both can be improved via the use of the same structural properties of instances. Our proposed methods are based on effi- cient problem partitioning and can be easily applied as pre-processing with arbitrary SAT solv- ers and BDD packages without modifying the source code of SAT/BDD tools. Finding a better variable ordering is a well recognized problem for both SAT solvers and BDD packages. Currently, the best variable-ordering algorithms are dynamic, in the sense that they are invoked many times in the course of the host algorithm that solves SAT or manipula...
Proceedings of the 50th Annual Design Automation Conference, 2013
IC performance, power dissipation, size, and signal integrity are now dominated by interconnects.... more IC performance, power dissipation, size, and signal integrity are now dominated by interconnects. However, with ever-shrinking standard cells, blind minimization of interconnect during placement causes routing failures. Hence, we develop Coordinated Placeand-Route (CoPR) with (i) a Lightweight Incremental Routing Estimation (LIRE) frequently invoked during placement, (ii) placement techniques that address three types of routing congestion, and (iii) an interface to congestion estimation that supports new types of incrementality. LIRE comprehends routing obstacles and nonuniform routing capacities, and relies on a cache-friendly, fullyincremental routing algorithm. Our implementation extends and improves our winning entry at the ICCAD 2012 Contest.
Proceedings of the 45th annual Design Automation Conference, 2008
Our work addresses protection of hardware IP at the mask level with the goal of preventing unauth... more Our work addresses protection of hardware IP at the mask level with the goal of preventing unauthorized manufacturing. The proposed protocol based on chip locking and activation is applicable to a broad category of electronic systems with a primary bus. Such designs include (1) numerous IP offerings for USB, PCI, PCI-E, AMBA and other bus standards typically used in system-on-a-chip designs and computer peripherals, (2) SRAM-based FPGAs that are programmed through an input bus, (3) general-purpose and embedded microprocessors, including soft cores, (4) DSPs, (5) network processors, and (6) game consoles. Our key insight is that such designs can be locked by scrambling the central bus by controlled reversible bit-permutations and substitutions. To securely establish a unique code per chip to control bus scrambling, we employ true random number generators and Diffie-Hellman cryptography during activation.
Proceedings. 1998 IEEE Symposium on IC/Package Design Integration (Cat. No.98CB36211)
We empirically study the implications of area-array I O for placement methodology. Our work devel... more We empirically study the implications of area-array I O for placement methodology. Our work develops a three-axis testbed that examines 1 I O regime area-array v s . peripheral pad locations, 2 I O and core placement methodology variants of alternating vs. simultaneous I O and core placement approaches, and 3 placement engine hierarchical quadratic for both core and I O cells vs. pure min-cut for core cells and assignment for I O. Experimental data show that the area-array I O regime is somewhat more forgiving" of bad placement methodologies than the peripheral I O regime. On the other hand, the wrong methodology can still entail substantial losses in solution quality and efciency. Last, we hypothesize that reductions of on-chip wirelength from adopting the area-array I O regime may be correlated with topological depth of circuits. Test Case I Os Topological pro le by levels Case 1
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000
We study alternatives to Fh4-based partitioning in the context of end-case processing for top-dow... more We study alternatives to Fh4-based partitioning in the context of end-case processing for top-down standard-cell placement. The primary motivation is that small partitioning instances frequently contain multiple cells larger than the prescribed partitioning tolerance (balance constraint) and cannot be moved while preserving the legality of a solution. We focus on optimal ptitioning and placement algorithms, based on either enumeration or branch-and-bound, that are invoked for instances below prescribed size thresholds, e.g., < 10 cells for placement and < 30 cells for partitioning. Such par&loners transparently handle tight balance constraints and uneven cell sizes while typically achieving 40% smaller cuts than the best of several FM starts for instances between 10 and 35 movable nodes. On such instances, branch-and-bound codes also achieve surprising speedups, on average, over single FM starts. Enumeration-based partitioners relying on Gray codes, while easier to implement and taking less time for elementary operations, can only compete with branch-and-bound on very small instances, to which optimal placers can be applied. In the context of a top-down global placement tool, the right combination of optimal partitioners and placers can achieve up to an average of 10% wirelength reduction and 50% CPU time savings for a set of industry testcases. The paper concludes with directions for future research.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2001
Digital system designs are the product of valuable effort and know-how. Their embodiments, from s... more Digital system designs are the product of valuable effort and know-how. Their embodiments, from software and hardware description language program down to device-level netlist and mask data, represent carefully guarded intellectual property (IP). Hence, design methodologies based on IP reuse require new mechanisms to protect the rights of IP producers and owners. This paper establishes principles of watermarking-based IP protection, where a watermark is a mechanism for identification that is: 1) nearly invisible to human and machine inspection; 2) difficult to remove; and 3) permanently embedded as an integral part of the design. Watermarking addresses IP protection by tracing unauthorized reuse and making untraceable unauthorized reuse as difficult as recreating given pieces of IP from scratch. We survey related work in cryptography and design methodology, then develop desiderata, metrics, and concrete protocols for constraint-based watermarking at various stages of the very large scale integration (VLSI) design process. In particular, we propose a new preprocessing approach that embeds watermarks as constraints into the input of a black-box design tool and a new postprocessing approach that embeds watermarks as constraints into the output of a black-box design tool. To demonstrate that our protocols can be transparently integrated into existing design flows, we use a testbed of commercial tools for VLSI physical design and embed watermarks into real-world industrial designs. We show that the implementation overhead is low-both in terms of central processing unit time and such standard physical design metrics as wirelength, layout area, number of vias, and routing congestion. We empirically show that in the placement and routing applications considered in our methods achieve strong proofs of authorship are resistant to tampering and do not adversely influence timing.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1998
A linear wirelength objective more e ectively captures timing, congestion, and other global place... more A linear wirelength objective more e ectively captures timing, congestion, and other global placement considerations than a squared wirelength objective. The GORDIAN-L cell placement tool 19 minimizes linear wirelength by rst approximating the linear wirelength objective b y a modi ed squared wirelength objective, then executing the following loop 1 minimize the current objective to yield some approximate solution, and 2 use the resulting solution to construct a more accurate objective until the solution converges. This paper shows how to apply a generalization 5, 6 of a 1937 algorithm due to Weiszfeld 22 to placement with a linear wirelength objective, and that the main GORDIAN-L loop is actually a special case of this algorithm. We then propose applying a regularization parameter to the generalized Weiszfeld algorithm to control the tradeo between convergence and solution accuracy; the GORDIAN-L iteration is equivalent to setting this regularization parameter to zero. We also apply novel numerical methods, such as the Primal Newton and Primal-Dual Newton iterations, to optimize the linear wirelength objective. Finally, w e show both theoretically and empirically that the Primal-Dual Newton iteration stably attains quadratic convergence, while the generalized Weiszfeld iteration is linear convergent. Hence, Primal-Dual Newton is a superior choice for implementing a placer such as GORDIAN-L, or for any linear wirelength optimization.
IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 2001
When minimizing a given objective function is challenging because of, for example, combinatorial ... more When minimizing a given objective function is challenging because of, for example, combinatorial complexity or points of nondifferentiability, one can apply more efficient and easier-to-implement algorithms to modified versions of the function. In the ideal case, one can employ known algorithms for the modified function that have a thorough theoretical and empirical record and for which public implementations are available. The main requirement here is that minimizers of the objective function not change much through the modification, i.e., the modification must have a bounded effect on the quality of the solution. Review of classic and recent placement algorithms suggests a dichotomy between approaches that either: (a) heuristically minimize a potentially irrelevant objective function (e.g., VLSI placement with quadratic wirelength) motivated by the simplicity and speed of a standard minimization algorithm; or (b) devise elaborate problem-specific minimization heuristics for more relevant objective functions (e.g., VLSI placement with linear wirelength). Smoothness and convexity of the objective functions typically enable efficient minimization. If either characteristic is not present in the objective function, one can modify and/or restrict the objective to special values of parameters to provide the missing properties. After the minimizers of the modified function are found, they can be further improved with respect to the original function by fast local search using only function evaluations. Thus, it is the modification step that deserves most attention. In this paper, we approximate convex nonsmooth continuous functions by convex differentiable functions which are parameterized by a scalar 0 and have convenient limit behavior as 0. This allows the use of Newton-type algorithms for minimization and, for standard numerical methods, translates into a tradeoff between solution quality and speed. We prove that our methods apply to arbitrary multivariate convex piecewise-linear functions that are widely used in synthesis and analysis of electrical networks [19], [27]. The utility of our approximations is particularly demonstrated for wirelength and nonlinear delay estimations used Manuscript
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012
We propose a self-contained, flat, forcedirected algorithm for global placement that is simpler t... more We propose a self-contained, flat, forcedirected algorithm for global placement that is simpler than existing placers and easier to integrate into timingclosure flows. It maintains lower-bound and upper-bound placements that converge to a final solution. The upperbound placement is produced by a novel rough legalization algorithm. Our placer SimPL outperforms mPL6, NTUPlace3, FastPlace3, APlace2 and Capo simultaneously in runtime and solution quality, running 6.4 times faster than mPL6 and reducing wirelength by 2% on the ISPD 2005 benchmark suite.
International Conference on Computer Aided Design, Nov 7, 2011
This mini-tutorial covers recent research on clocknetwork tuning. It starts with SPICE-accurate o... more This mini-tutorial covers recent research on clocknetwork tuning. It starts with SPICE-accurate optimizations used in winning entries at the ISPD 2009 and 2010 clock-network synthesis contests. After comparing clock trees to meshes, it outlines a recent redundant clock-network topology that retains most advantages of clock trees, but improves robustness to PVT variations. It also shows how to incorporate clock-network synthesis into global placement to reduce dynamic power and insertion delay.
This work focuses on congestion-driven placement of standard cells into rows in the fixed-die con... more This work focuses on congestion-driven placement of standard cells into rows in the fixed-die context. We summarize the stateof-the-art after two decades of research in recursive bisection placement and implement a new placer, called Capo, to empirically study the achievable limits of the approach. From among recently proposed improvements to recursive bisection, Capo incorporates a leading-edge multilevel min-cut partitioner [7], techniques for partitioning with small tolerance [8], optimal min-cut partitioners and end-case min-wirelength placers [5], previously unpublished partitioning tolerance computations, and block splitting heuristics. On the other hand, our "good enough" implementation does not use "overlapping" [17], multi-way partitioners [17, 20], analytical placement, or congestion estimation [24, 35]. In order to run on recent industrial placement instances, Capo must take into account fixed macros, power stripes and rows with different allowed cell orientations. Capo reads industry-standard LEF/DEF, as well as formats of the GSRC bookshelf for VLSI CAD algorithms [6], to enable comparisons on available placement instances in the fixed-die regime. Capo clearly demonstrates that despite a potential mismatch of objectives, improved mincut bisection can still lead to improved placement wirelength and congestion. Our experiments on recent industrial benchmarks fail to give a clear answer to the question in the title of this paper. However, they validate a series of improvements to recursive bisection and point out a need for transparent congestion management techniques that do not worsen the wirelength of already routable placements. Our experimental flow, which validates fixed-die placement results by violation-free detailed auto-routability, provides a new norm for comparison of VLSI placement implementations.
Many popular algorithms that work with Boolean functions are dramatically dependent on the order ... more Many popular algorithms that work with Boolean functions are dramatically dependent on the order of variables in input representations of Boolean functions. Such algorithms include satisfiability (SAT) solvers that are critical in formal verification and Binary Decision Diagrams (BDDs) manipulation algorithms that are increasingly popular in synthesis and verification. Finding better variable-orderings is a well-recognized problem in each of those contexts. Currently, all leading-edge variable-ordering algorithms are dynamic in the sense that they are invoked many times in the course of the "host" algorithm that solves SAT or manipulates BDDs. Examples include the DLIS ordering for SAT solvers and variable-sifting during BDD manipulations. In this work we propose a universal variable ordering MINCE (MIN Cut Etc.) that preprocesses a given Boolean formula in CNF. MINCE is completely independent from target algorithms and outperforms both DLIS for SAT and variable sifting for BDDs. We argue that MINCE tends to capture structural properties of Boolean functions arising from real-world applications.
International Conference on Computer Aided Design, Nov 4, 2001
The increasing popularity of SAT and BDD techniques in verification and synthesis encourages the ... more The increasing popularity of SAT and BDD techniques in verification and synthesis encourages the search for additional speed-ups. Since typical SAT and BDD algorithms are exponential in the worst-case, the structure of real-world instances is a natural source of improvements. While SAT and BDD techniques are often presented as mutually exclusive alternatives, our work points out that both can be improved via the use of the same structural properties of instances. Our proposed methods are based on efficient problem partitioning and can be easily applied as pre-processing with arbitrary SAT solvers and BDD packages without source code modifications. Finding a better variable-ordering is a well recognized problem for both SAT solvers and BDD packages. Currently, all leading edge variable-ordering algorithms are dynamic, in the sense that they are invoked many times in the course of the "host" algorithm that solves SAT or manipulates BDDs. Examples include the DLCS ordering for SAT solvers and variable-sifting during BDD manipulations. In this work we propose a universal variable-ordering MINCE (MIN Cut Etc.) that pre-processes a given Boolean formula in CNF. MINCE is completely independent from target algorithms and outperforms both DLCS for SAT and variable sifting for BDDs. We argue that MINCE tends to capture structural properties of Boolean functions arising from real-world applications. Our contribution is validated on the ISCAS circuits and the DIMACS benchmarks. Empirically, our technique often outperforms existing techniques by a factor of two or more. Our results motivate search for stronger dynamic ordering heuristics and combined static/dynamic techniques.
Zenodo (CERN European Organization for Nuclear Research), Dec 28, 2004
The increasing popularity of SAT and BDD techniques in formal hardware verification and automated... more The increasing popularity of SAT and BDD techniques in formal hardware verification and automated synthesis of logic circuits encourages the search for additional speedups. Since typical SAT and BDD algorithms are exponential in the worst-case, the structure of realworld instances is a natural source of improvements. While SAT and BDD techniques are often presented as mutually exclusive alternatives, our work points out that both can be improved via the use of the same structural properties of instances. Our proposed methods are based on efficient problem partitioning and can be easily applied as pre-processing with arbitrary SAT solvers and BDD packages without modifying the source code of SAT/BDD tools. Finding a better variable ordering is a well recognized problem for both SAT solvers and BDD packages. Currently, the best variable-ordering algorithms are dynamic, in the sense that they are invoked many times in the course of the host algorithm that solves SAT or manipulates BDDs. Examples include the DLCS ordering for SAT solvers and variable sifting during BDD manipulations. In this work we propose a universal variable-ordering algorithm MINCE (MIN Cut Etc.) that pre-processes a given Boolean formula in CNF. MINCE is completely independent from target SAT algorithms and in some cases outperforms both the variable state independent decaying sum (VSIDS) decision heuristic for SAT and variable sifting for BDDs. We argue that MINCE tends to capture structural properties of Boolean functions arising from real-world applications. Our contribution is validated on the ISCAS circuits and the DIMACS benchmarks. Empirically, our technique often outperforms existing SAT/BDD techniques by a factor of two or more. Our results motivate the search for better dynamic ordering heuristics and combined static/dynamic techniques.
2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)
Performance of modern multi-chip modules, increasingly implemented as interposer solutions, is li... more Performance of modern multi-chip modules, increasingly implemented as interposer solutions, is limited by system-level interconnects. We propose an effective method for optimal wirelength-driven die placement of interposer-based 3D ICs. Our key ideas are to leverage the constraint-satisfaction problem (CSP) formalism in combination with a branch-and-bound (B&B) algorithm, and to develop several novel techniques for early identification and pruning of unpromising configurations. Such techniques are crucial for addressing the combinatorial explosion when solving the NP-hard placement problem. Experiments on ISPD08 (modified) and MCNC benchmarks demonstrate that our method outperforms prior art: we can optimally place up to eleven rotatable dies, whereas state-of-the-art tools are limited to six dies.
The increasing popularity of SAT and BDD techniques in formal hardware verifica- tion and automat... more The increasing popularity of SAT and BDD techniques in formal hardware verifica- tion and automated synthesis of logic circuits encourages the search for additional speedups. Since typical SAT and BDD algorithms are exponential in the worst-case, the structure of real- world instances is a natural source of improvements. While SAT and BDD techniques are often presented as mutually exclusive alternatives, our work points out that both can be improved via the use of the same structural properties of instances. Our proposed methods are based on effi- cient problem partitioning and can be easily applied as pre-processing with arbitrary SAT solv- ers and BDD packages without modifying the source code of SAT/BDD tools. Finding a better variable ordering is a well recognized problem for both SAT solvers and BDD packages. Currently, the best variable-ordering algorithms are dynamic, in the sense that they are invoked many times in the course of the host algorithm that solves SAT or manipula...
Proceedings of the 50th Annual Design Automation Conference, 2013
IC performance, power dissipation, size, and signal integrity are now dominated by interconnects.... more IC performance, power dissipation, size, and signal integrity are now dominated by interconnects. However, with ever-shrinking standard cells, blind minimization of interconnect during placement causes routing failures. Hence, we develop Coordinated Placeand-Route (CoPR) with (i) a Lightweight Incremental Routing Estimation (LIRE) frequently invoked during placement, (ii) placement techniques that address three types of routing congestion, and (iii) an interface to congestion estimation that supports new types of incrementality. LIRE comprehends routing obstacles and nonuniform routing capacities, and relies on a cache-friendly, fullyincremental routing algorithm. Our implementation extends and improves our winning entry at the ICCAD 2012 Contest.
Proceedings of the 45th annual Design Automation Conference, 2008
Our work addresses protection of hardware IP at the mask level with the goal of preventing unauth... more Our work addresses protection of hardware IP at the mask level with the goal of preventing unauthorized manufacturing. The proposed protocol based on chip locking and activation is applicable to a broad category of electronic systems with a primary bus. Such designs include (1) numerous IP offerings for USB, PCI, PCI-E, AMBA and other bus standards typically used in system-on-a-chip designs and computer peripherals, (2) SRAM-based FPGAs that are programmed through an input bus, (3) general-purpose and embedded microprocessors, including soft cores, (4) DSPs, (5) network processors, and (6) game consoles. Our key insight is that such designs can be locked by scrambling the central bus by controlled reversible bit-permutations and substitutions. To securely establish a unique code per chip to control bus scrambling, we employ true random number generators and Diffie-Hellman cryptography during activation.
Proceedings. 1998 IEEE Symposium on IC/Package Design Integration (Cat. No.98CB36211)
We empirically study the implications of area-array I O for placement methodology. Our work devel... more We empirically study the implications of area-array I O for placement methodology. Our work develops a three-axis testbed that examines 1 I O regime area-array v s . peripheral pad locations, 2 I O and core placement methodology variants of alternating vs. simultaneous I O and core placement approaches, and 3 placement engine hierarchical quadratic for both core and I O cells vs. pure min-cut for core cells and assignment for I O. Experimental data show that the area-array I O regime is somewhat more forgiving" of bad placement methodologies than the peripheral I O regime. On the other hand, the wrong methodology can still entail substantial losses in solution quality and efciency. Last, we hypothesize that reductions of on-chip wirelength from adopting the area-array I O regime may be correlated with topological depth of circuits. Test Case I Os Topological pro le by levels Case 1
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000
We study alternatives to Fh4-based partitioning in the context of end-case processing for top-dow... more We study alternatives to Fh4-based partitioning in the context of end-case processing for top-down standard-cell placement. The primary motivation is that small partitioning instances frequently contain multiple cells larger than the prescribed partitioning tolerance (balance constraint) and cannot be moved while preserving the legality of a solution. We focus on optimal ptitioning and placement algorithms, based on either enumeration or branch-and-bound, that are invoked for instances below prescribed size thresholds, e.g., < 10 cells for placement and < 30 cells for partitioning. Such par&loners transparently handle tight balance constraints and uneven cell sizes while typically achieving 40% smaller cuts than the best of several FM starts for instances between 10 and 35 movable nodes. On such instances, branch-and-bound codes also achieve surprising speedups, on average, over single FM starts. Enumeration-based partitioners relying on Gray codes, while easier to implement and taking less time for elementary operations, can only compete with branch-and-bound on very small instances, to which optimal placers can be applied. In the context of a top-down global placement tool, the right combination of optimal partitioners and placers can achieve up to an average of 10% wirelength reduction and 50% CPU time savings for a set of industry testcases. The paper concludes with directions for future research.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2001
Digital system designs are the product of valuable effort and know-how. Their embodiments, from s... more Digital system designs are the product of valuable effort and know-how. Their embodiments, from software and hardware description language program down to device-level netlist and mask data, represent carefully guarded intellectual property (IP). Hence, design methodologies based on IP reuse require new mechanisms to protect the rights of IP producers and owners. This paper establishes principles of watermarking-based IP protection, where a watermark is a mechanism for identification that is: 1) nearly invisible to human and machine inspection; 2) difficult to remove; and 3) permanently embedded as an integral part of the design. Watermarking addresses IP protection by tracing unauthorized reuse and making untraceable unauthorized reuse as difficult as recreating given pieces of IP from scratch. We survey related work in cryptography and design methodology, then develop desiderata, metrics, and concrete protocols for constraint-based watermarking at various stages of the very large scale integration (VLSI) design process. In particular, we propose a new preprocessing approach that embeds watermarks as constraints into the input of a black-box design tool and a new postprocessing approach that embeds watermarks as constraints into the output of a black-box design tool. To demonstrate that our protocols can be transparently integrated into existing design flows, we use a testbed of commercial tools for VLSI physical design and embed watermarks into real-world industrial designs. We show that the implementation overhead is low-both in terms of central processing unit time and such standard physical design metrics as wirelength, layout area, number of vias, and routing congestion. We empirically show that in the placement and routing applications considered in our methods achieve strong proofs of authorship are resistant to tampering and do not adversely influence timing.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1998
A linear wirelength objective more e ectively captures timing, congestion, and other global place... more A linear wirelength objective more e ectively captures timing, congestion, and other global placement considerations than a squared wirelength objective. The GORDIAN-L cell placement tool 19 minimizes linear wirelength by rst approximating the linear wirelength objective b y a modi ed squared wirelength objective, then executing the following loop 1 minimize the current objective to yield some approximate solution, and 2 use the resulting solution to construct a more accurate objective until the solution converges. This paper shows how to apply a generalization 5, 6 of a 1937 algorithm due to Weiszfeld 22 to placement with a linear wirelength objective, and that the main GORDIAN-L loop is actually a special case of this algorithm. We then propose applying a regularization parameter to the generalized Weiszfeld algorithm to control the tradeo between convergence and solution accuracy; the GORDIAN-L iteration is equivalent to setting this regularization parameter to zero. We also apply novel numerical methods, such as the Primal Newton and Primal-Dual Newton iterations, to optimize the linear wirelength objective. Finally, w e show both theoretically and empirically that the Primal-Dual Newton iteration stably attains quadratic convergence, while the generalized Weiszfeld iteration is linear convergent. Hence, Primal-Dual Newton is a superior choice for implementing a placer such as GORDIAN-L, or for any linear wirelength optimization.
IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 2001
When minimizing a given objective function is challenging because of, for example, combinatorial ... more When minimizing a given objective function is challenging because of, for example, combinatorial complexity or points of nondifferentiability, one can apply more efficient and easier-to-implement algorithms to modified versions of the function. In the ideal case, one can employ known algorithms for the modified function that have a thorough theoretical and empirical record and for which public implementations are available. The main requirement here is that minimizers of the objective function not change much through the modification, i.e., the modification must have a bounded effect on the quality of the solution. Review of classic and recent placement algorithms suggests a dichotomy between approaches that either: (a) heuristically minimize a potentially irrelevant objective function (e.g., VLSI placement with quadratic wirelength) motivated by the simplicity and speed of a standard minimization algorithm; or (b) devise elaborate problem-specific minimization heuristics for more relevant objective functions (e.g., VLSI placement with linear wirelength). Smoothness and convexity of the objective functions typically enable efficient minimization. If either characteristic is not present in the objective function, one can modify and/or restrict the objective to special values of parameters to provide the missing properties. After the minimizers of the modified function are found, they can be further improved with respect to the original function by fast local search using only function evaluations. Thus, it is the modification step that deserves most attention. In this paper, we approximate convex nonsmooth continuous functions by convex differentiable functions which are parameterized by a scalar 0 and have convenient limit behavior as 0. This allows the use of Newton-type algorithms for minimization and, for standard numerical methods, translates into a tradeoff between solution quality and speed. We prove that our methods apply to arbitrary multivariate convex piecewise-linear functions that are widely used in synthesis and analysis of electrical networks [19], [27]. The utility of our approximations is particularly demonstrated for wirelength and nonlinear delay estimations used Manuscript
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Papers by Igor Markov