Abstract. Branch prediction reversal has been proved to be an effective alternative approach ,to ... more Abstract. Branch prediction reversal has been proved to be an effective alternative approach ,to dropping ,misprediction rates by means ,of adding ,a Confidence Estimator to a correlating branch predictor. This paper presents a Branch Prediction Reversal Unit ( BPRU) especially oriented to enhance ,correlating branch predictors, such as the gshare and the Alpha 21264 metapredictor. The novelty of this proposal
2011 IEEE International Parallel & Distributed Processing Symposium, 2011
In the recent years virtually all processor architectures employ multiple cores per chip (CMPs). ... more In the recent years virtually all processor architectures employ multiple cores per chip (CMPs). It is possible to use legacy (i.e., single-core) power saving techniques in CMPs which run either sequential applications or independent multithreaded workloads. However, new challenges arise when running parallel shared-memory applications. In the later case, sacrificing some performance in a single core (thread) in order to be more energy-efficient might unintentionally delay the rest of cores (threads) due to synchronization points (locks/barriers), therefore, harming the performance of the whole application.
ABSTRACT To obtain benefit of the increasing transistor count in current processors, designs are ... more ABSTRACT To obtain benefit of the increasing transistor count in current processors, designs are leading to CMPs that will integrate tens or hundreds of processor cores on-chip. However, scaling and voltage factors are increasing susceptibility of architectures to transient, intermittent and permanent faults, as well as process variations. A very recent solution found in literature consists of Dynamic Core Coupling (DCC) [6]. DCC provides a fault tolerant framework based on dynamic binding of cores for re-execution. This technique relies on the use of a shared-bus. However, for current and future CMP architectures, more efficient designs are tiled-CMPs, which are organized around a direct network, since area, scalability and power constraints make impractical the use of a bus as the interconnection network. In this work, we present the changes needed in the original DCC proposal to be used for a direct network environment. These changes are mostly due to the replacement of a bus for a mesh as interconnection network, the coherence protocol and the consistency window. Our evaluations show that, for several par-allel scientific applications, the performance overhead with this new environment rises to 10%, 19%, 42.5% and 47% for 4, 8, 16 and 32 core pairs, respectively, compared to the 5% performance degradation as pre-viously reported for 8 core pairs in the original DCC proposal.
Resumen—Energy-efficient microprocessor designs are currently one of main goals pursued by design... more Resumen—Energy-efficient microprocessor designs are currently one of main goals pursued by designers in both high performance and embedded processor domains. Recent processor implementations and research efforts have been focused on dynamic power consumption. However, as process technology advances toward deep submicron -below 90 nm.-, static power becomes a new challenge to address, especially for large on-chip array structures such as
Nowadays, chip multiprocessors (CMPs) are the new standard design for a wide range of microproces... more Nowadays, chip multiprocessors (CMPs) are the new standard design for a wide range of microprocessors: mobile devices (in the near future almost every smartphone will be governed by a CMP), desktop computers, laptop, servers, GPUs, APUs, etc. This new way of increasing performance by exploiting parallelism has two major drawbacks: off-chip bandwidth and communication latency between cores. 3D die-stacked processors are a recent design trend aimed at overcoming these drawbacks by stacking multiple device layers. However, the increase in packing density also leads to an increase in power density, which translates into thermal problems. Different proposals can be found in the literature to face these thermal problems such as dynamic thermal management (DTM), dynamic voltage and frequency scaling (DVFS), thread migration, etc. In this paper we propose the use of microarchitectural power budget techniques to reduce peak temperature. In particular, we first introduce Token3D, a new power balancing policy that takes into account temperature and layout information to balance the available per core power along other power optimizations for 3D designs. And second, we analyze a wide range of floorplans looking for the optimal temperature configuration. Experimental results show a reduction of the peak temperature of 2-26ºC depending on the selected floorplan.
Energy-efficient microprocessor designs are one of the major concerns in both high performance an... more Energy-efficient microprocessor designs are one of the major concerns in both high performance and embedded processor domains. Furthermore, as process technology advances toward deep submicron, static power dissipation becomes a new challenge to address. Value prediction emerged as a effective way of increasing proc essor performance by overcoming data dependences. The more accurate the predictor is the more perform ance
The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings., 2003
With the constant advances in technology that lead to the increasing of the transistor count and ... more With the constant advances in technology that lead to the increasing of the transistor count and processor frequency, power dissipation is becoming one of the major issues in high-performance processors. These processors increase their clock frequency by lengthening the pipeline, which puts more pressure on the branch prediction engine since branches take longer to be resolved. Branch mispredictions are responsible for around 28% of the power dissipated by a typical processor due to the useless activities performed by instructions that are squashed.
2011 IEEE 17th International On-Line Testing Symposium, 2011
Technology scaling improvement is affecting the reliability of ICs due to increases in static and... more Technology scaling improvement is affecting the reliability of ICs due to increases in static and dynamic variations as well as wear-out failures. This is particularly true for caches that dominate the area of modern processors and are built with minimum-sized, but prone to failure, SRAM cells.
Proceedings of the 4th international conference on Computing frontiers - CF '07, 2007
Energy-efficient microprocessor designs are one of the major concerns in both high performance an... more Energy-efficient microprocessor designs are one of the major concerns in both high performance and embedded processor domains. Furthermore, as process technology advances toward deep submicron, static power dissipation becomes a new challenge to address, especially for large on-chip array structures such as caches or prediction tables. Value prediction emerged in the recent past as a very effective way of increasing processor performance by overcoming data dependences. The more accurate the value predictor is the more performance is obtained, at the expense of becoming a source of power consumption and a thermal hot spot, and therefore increasing its leakage. Recent techniques, aimed at reducing the leakage power of array structures such as caches, either switch off (non-state preserving) or reduce the voltage level (statepreserving) of unused array portions.
Continuing advances in semiconductor technology and demand for higher performance will lead to mo... more Continuing advances in semiconductor technology and demand for higher performance will lead to more powerful, superpipelined and wider issue processors. Instruction caches in such processors will consume a significant fraction of the on-chip energy due to very wide fetch on each cycle. This paper proposes a new energy-effective design of the fetch unit that exploits the fact that not all instructions in a given I-cache fetch line are used due to taken branches. A Fetch Mask Determination unit is proposed to detect which instructions in an I-cache access will actually be used to avoid fetching any of the other instructions. The solution is evaluated for a 4-, 8-and 16-wide issue processor in 100nm technology. Results show an average improvement in the Icache Energy-Delay product of 20% for the 8-wide issue processor and 33% for the 16-wide issue processor for the SPEC2000, with no negative impact on performance.
2010 International Conference on High Performance Computing, 2010
CMOS scaling exacerbates hardware errors making reliability a big concern for recent and future m... more CMOS scaling exacerbates hardware errors making reliability a big concern for recent and future microarchitecture designs. Mechanisms to provide fault tolerance in architectures must accomplish several objectives such as low performance degradation, power consumption and area overhead. Several studies have been already proposed to provide fault tolerance for parallel codes. However, these proposals are usually implemented over non-realistic environments including the use of shared-buses among processors or modifying highly optimized hardware designs such as caches. Our main design goal is to provide transient fault detection and recovery while modifying hardware as less as possible.
2007 IEEE International Parallel and Distributed Processing Symposium, 2007
As process technology advances toward deep submicron (below 90nm), static power becomes a new cha... more As process technology advances toward deep submicron (below 90nm), static power becomes a new challenge to address for energy-efficient high performance processors, especially for large on-chip array structures such as caches and prediction tables. Value Prediction appeared as an effective way of increasing processor performance by overcoming data dependences, but at the risk of becoming a thermal hot spot due to the additional power dissipation.
Previous studies have shown that the interconnection network of a Chip-Multiprocessor (CMP) has s... more Previous studies have shown that the interconnection network of a Chip-Multiprocessor (CMP) has significant impact on both overall performance and energy consumption. Moreover, wires used in such interconnect can be designed with varying latency, bandwidth and power characteristics. In this work, we present a proposal for performance-and energy-efficient message management in tiled CMPs by using a heterogeneous interconnect. Our proposal consists of Reply Partitioning, a technique that classifies all coherence messages into critical and short, and non-critical and long messages; and the use of a heterogeneous interconnection network comprised of low-latency wires for critical messages and low-energy wires for non-critical ones. Through detailed simulations of 8and 16-core CMPs, we show that our proposal obtains average improvements of 8% in execution time and 65% in the Energy-Delay 2 Product metric of the interconnect over previous works.
21st International Conference on Advanced Information Networking and Applications Workshops (AINAW'07), 2007
Continuous improvements in integration scale have made major microprocessor vendors to move to de... more Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessors (CMPs) constitute the architecture of choice in the high performance embedded domain for several reasons such as better levels of scalability and performance/energy ratio. On the other hand, higher clock frequencies and increasing transistor density have revealed power dissipation as a critical design issue, especially in embedded systems where reduced energy consumption directly translates into extended battery life. In this work we present Sim-PowerCMP, a detailed architecture-level power-performance simulation tool for CMP architectures that integrates several well-known contemporary simulators (RSIM, HotLeakage and Orion) into a single framework. As a case of use of Sim-PowerCMP, we present a characterization of the energy-efficiency of a CMP for parallel scientific applications, paying special attention to the energy consumed on the interconnect. Results for an 8-and 16-core CMP show that the contribution of the interconnection network to the total power is close to 20%, on average, and that the most consuming messages are replies that carry data (almost 70% of total energy consumed in the interconnect).
2008 37th International Conference on Parallel Processing, 2008
Previous studies have shown that the interconnection network of a Chip-Multiprocessor (CMP) has s... more Previous studies have shown that the interconnection network of a Chip-Multiprocessor (CMP) has significant impact on both overall performance and energy consumption. Moreover, wires used in such interconnect can be designed with varying latency, bandwidth and power characteristics. In this work, we present a proposal for performance-and energy-efficient message management in tiled CMPs that combines both address compression with a heterogeneous interconnect. Our proposal consists of applying an address compression scheme that dynamically compresses the addresses within coherence messages allowing for a significant area slack. The arising area can be exploited for wire latency improvement by using a heterogeneous interconnection network comprised of a small set of very-low-latency wires for critical short-messages in addition to baseline wires. Detailed simulations of a 16-core CMP show that our proposal obtains average improvements of 10% in execution time and 38% in the Energy-Delay 2
Proceedings of the 16th international conference on Supercomputing - ICS '02, 2002
The reasons for performance losses due to conditional branch mispredictions are first studied. Br... more The reasons for performance losses due to conditional branch mispredictions are first studied. Branch misprediction penalties are broken into three categories: pipeline-fill penalty, window-fill penalty, and serialization penalty. The first and third of these produce most of the performance loss, but the second is also significant. Previously proposed dual (or multi) path execution methods attempt to reduce all three penalties, but these methods are also quite complex. Most of the complexity is caused by simultaneously executing instructions from multiple paths.
To obtain benefit of the increasing tran- sistor count in current processors, designs are lead- i... more To obtain benefit of the increasing tran- sistor count in current processors, designs are lead- ing to CMPs that will integrate tens or hundreds of processor cores on-chip. However, scaling and voltage factors are increasing susceptibility of architectures to transient, intermittent and permanent faults, as well as process variations. A very recent solution found in literature consists of Dynamic Core Coupling (DCC) (1). DCC provides a fault tolerant framework based on dynamic binding of cores for re-execution. This technique relies on the use of a shared-bus. However, for current and future CMP architectures, more ecient designs are tiled- CMPs, which are organized around a direct network, since area, scalability and power constraints make im- practical the use of a bus as the interconnection net- work. In this work, we present the changes needed in the original DCC proposal to be used for a direct net- work environment. These changes are mostly due to the replacement of a bus for ...
High performance processor designs have evolved toward architectures that integrate multiple proc... more High performance processor designs have evolved toward architectures that integrate multiple processing cores on the same chip. As the number of cores inside a Chip MultiProcessor (CMP) increases, the interconnection network will have significant impact on both overall performance and energy consumption as previous studies have shown. Moreover, wires used in such interconnect can be designed with varying latency, bandwidth and power characteristics. In this work, we show how messages can be efficiently managed in tiled CMP, from the point of view of both performance and energy, by combining both address compression with a heterogeneous interconnect. In particular, our proposal is based on applying an address compression scheme that dynamically compresses the addresses within coherence messages allowing for a significant area slack. The arising area is exploited for wire latency improvement by using a heterogeneous interconnection network comprised of a small set of very-low-latency wires for critical short-messages in addition to baseline wires. Detailed simulations of a 16-core CMP show that our proposal obtains average improvements of 10% in execution time and 38% in the energy-delay 2 product of the interconnect. Additionally, the sensitivity analysis shows that our proposal performs well when either OoO cores or caches with higher latencies are considered.
Energy consumption and power dissipation are important concerns in the design of embedded systems... more Energy consumption and power dissipation are important concerns in the design of embedded systems and they will become even more crucial with finer process geometry, higher frequencies, deeper pipelines and wider issue designs. In particular, the instruction cache consumes more energy than any other processor module, especially with commonly used highly associative CAM-based implementations.
Abstract. Branch prediction reversal has been proved to be an effective alternative approach ,to ... more Abstract. Branch prediction reversal has been proved to be an effective alternative approach ,to dropping ,misprediction rates by means ,of adding ,a Confidence Estimator to a correlating branch predictor. This paper presents a Branch Prediction Reversal Unit ( BPRU) especially oriented to enhance ,correlating branch predictors, such as the gshare and the Alpha 21264 metapredictor. The novelty of this proposal
2011 IEEE International Parallel & Distributed Processing Symposium, 2011
In the recent years virtually all processor architectures employ multiple cores per chip (CMPs). ... more In the recent years virtually all processor architectures employ multiple cores per chip (CMPs). It is possible to use legacy (i.e., single-core) power saving techniques in CMPs which run either sequential applications or independent multithreaded workloads. However, new challenges arise when running parallel shared-memory applications. In the later case, sacrificing some performance in a single core (thread) in order to be more energy-efficient might unintentionally delay the rest of cores (threads) due to synchronization points (locks/barriers), therefore, harming the performance of the whole application.
ABSTRACT To obtain benefit of the increasing transistor count in current processors, designs are ... more ABSTRACT To obtain benefit of the increasing transistor count in current processors, designs are leading to CMPs that will integrate tens or hundreds of processor cores on-chip. However, scaling and voltage factors are increasing susceptibility of architectures to transient, intermittent and permanent faults, as well as process variations. A very recent solution found in literature consists of Dynamic Core Coupling (DCC) [6]. DCC provides a fault tolerant framework based on dynamic binding of cores for re-execution. This technique relies on the use of a shared-bus. However, for current and future CMP architectures, more efficient designs are tiled-CMPs, which are organized around a direct network, since area, scalability and power constraints make impractical the use of a bus as the interconnection network. In this work, we present the changes needed in the original DCC proposal to be used for a direct network environment. These changes are mostly due to the replacement of a bus for a mesh as interconnection network, the coherence protocol and the consistency window. Our evaluations show that, for several par-allel scientific applications, the performance overhead with this new environment rises to 10%, 19%, 42.5% and 47% for 4, 8, 16 and 32 core pairs, respectively, compared to the 5% performance degradation as pre-viously reported for 8 core pairs in the original DCC proposal.
Resumen—Energy-efficient microprocessor designs are currently one of main goals pursued by design... more Resumen—Energy-efficient microprocessor designs are currently one of main goals pursued by designers in both high performance and embedded processor domains. Recent processor implementations and research efforts have been focused on dynamic power consumption. However, as process technology advances toward deep submicron -below 90 nm.-, static power becomes a new challenge to address, especially for large on-chip array structures such as
Nowadays, chip multiprocessors (CMPs) are the new standard design for a wide range of microproces... more Nowadays, chip multiprocessors (CMPs) are the new standard design for a wide range of microprocessors: mobile devices (in the near future almost every smartphone will be governed by a CMP), desktop computers, laptop, servers, GPUs, APUs, etc. This new way of increasing performance by exploiting parallelism has two major drawbacks: off-chip bandwidth and communication latency between cores. 3D die-stacked processors are a recent design trend aimed at overcoming these drawbacks by stacking multiple device layers. However, the increase in packing density also leads to an increase in power density, which translates into thermal problems. Different proposals can be found in the literature to face these thermal problems such as dynamic thermal management (DTM), dynamic voltage and frequency scaling (DVFS), thread migration, etc. In this paper we propose the use of microarchitectural power budget techniques to reduce peak temperature. In particular, we first introduce Token3D, a new power balancing policy that takes into account temperature and layout information to balance the available per core power along other power optimizations for 3D designs. And second, we analyze a wide range of floorplans looking for the optimal temperature configuration. Experimental results show a reduction of the peak temperature of 2-26ºC depending on the selected floorplan.
Energy-efficient microprocessor designs are one of the major concerns in both high performance an... more Energy-efficient microprocessor designs are one of the major concerns in both high performance and embedded processor domains. Furthermore, as process technology advances toward deep submicron, static power dissipation becomes a new challenge to address. Value prediction emerged as a effective way of increasing proc essor performance by overcoming data dependences. The more accurate the predictor is the more perform ance
The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings., 2003
With the constant advances in technology that lead to the increasing of the transistor count and ... more With the constant advances in technology that lead to the increasing of the transistor count and processor frequency, power dissipation is becoming one of the major issues in high-performance processors. These processors increase their clock frequency by lengthening the pipeline, which puts more pressure on the branch prediction engine since branches take longer to be resolved. Branch mispredictions are responsible for around 28% of the power dissipated by a typical processor due to the useless activities performed by instructions that are squashed.
2011 IEEE 17th International On-Line Testing Symposium, 2011
Technology scaling improvement is affecting the reliability of ICs due to increases in static and... more Technology scaling improvement is affecting the reliability of ICs due to increases in static and dynamic variations as well as wear-out failures. This is particularly true for caches that dominate the area of modern processors and are built with minimum-sized, but prone to failure, SRAM cells.
Proceedings of the 4th international conference on Computing frontiers - CF '07, 2007
Energy-efficient microprocessor designs are one of the major concerns in both high performance an... more Energy-efficient microprocessor designs are one of the major concerns in both high performance and embedded processor domains. Furthermore, as process technology advances toward deep submicron, static power dissipation becomes a new challenge to address, especially for large on-chip array structures such as caches or prediction tables. Value prediction emerged in the recent past as a very effective way of increasing processor performance by overcoming data dependences. The more accurate the value predictor is the more performance is obtained, at the expense of becoming a source of power consumption and a thermal hot spot, and therefore increasing its leakage. Recent techniques, aimed at reducing the leakage power of array structures such as caches, either switch off (non-state preserving) or reduce the voltage level (statepreserving) of unused array portions.
Continuing advances in semiconductor technology and demand for higher performance will lead to mo... more Continuing advances in semiconductor technology and demand for higher performance will lead to more powerful, superpipelined and wider issue processors. Instruction caches in such processors will consume a significant fraction of the on-chip energy due to very wide fetch on each cycle. This paper proposes a new energy-effective design of the fetch unit that exploits the fact that not all instructions in a given I-cache fetch line are used due to taken branches. A Fetch Mask Determination unit is proposed to detect which instructions in an I-cache access will actually be used to avoid fetching any of the other instructions. The solution is evaluated for a 4-, 8-and 16-wide issue processor in 100nm technology. Results show an average improvement in the Icache Energy-Delay product of 20% for the 8-wide issue processor and 33% for the 16-wide issue processor for the SPEC2000, with no negative impact on performance.
2010 International Conference on High Performance Computing, 2010
CMOS scaling exacerbates hardware errors making reliability a big concern for recent and future m... more CMOS scaling exacerbates hardware errors making reliability a big concern for recent and future microarchitecture designs. Mechanisms to provide fault tolerance in architectures must accomplish several objectives such as low performance degradation, power consumption and area overhead. Several studies have been already proposed to provide fault tolerance for parallel codes. However, these proposals are usually implemented over non-realistic environments including the use of shared-buses among processors or modifying highly optimized hardware designs such as caches. Our main design goal is to provide transient fault detection and recovery while modifying hardware as less as possible.
2007 IEEE International Parallel and Distributed Processing Symposium, 2007
As process technology advances toward deep submicron (below 90nm), static power becomes a new cha... more As process technology advances toward deep submicron (below 90nm), static power becomes a new challenge to address for energy-efficient high performance processors, especially for large on-chip array structures such as caches and prediction tables. Value Prediction appeared as an effective way of increasing processor performance by overcoming data dependences, but at the risk of becoming a thermal hot spot due to the additional power dissipation.
Previous studies have shown that the interconnection network of a Chip-Multiprocessor (CMP) has s... more Previous studies have shown that the interconnection network of a Chip-Multiprocessor (CMP) has significant impact on both overall performance and energy consumption. Moreover, wires used in such interconnect can be designed with varying latency, bandwidth and power characteristics. In this work, we present a proposal for performance-and energy-efficient message management in tiled CMPs by using a heterogeneous interconnect. Our proposal consists of Reply Partitioning, a technique that classifies all coherence messages into critical and short, and non-critical and long messages; and the use of a heterogeneous interconnection network comprised of low-latency wires for critical messages and low-energy wires for non-critical ones. Through detailed simulations of 8and 16-core CMPs, we show that our proposal obtains average improvements of 8% in execution time and 65% in the Energy-Delay 2 Product metric of the interconnect over previous works.
21st International Conference on Advanced Information Networking and Applications Workshops (AINAW'07), 2007
Continuous improvements in integration scale have made major microprocessor vendors to move to de... more Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessors (CMPs) constitute the architecture of choice in the high performance embedded domain for several reasons such as better levels of scalability and performance/energy ratio. On the other hand, higher clock frequencies and increasing transistor density have revealed power dissipation as a critical design issue, especially in embedded systems where reduced energy consumption directly translates into extended battery life. In this work we present Sim-PowerCMP, a detailed architecture-level power-performance simulation tool for CMP architectures that integrates several well-known contemporary simulators (RSIM, HotLeakage and Orion) into a single framework. As a case of use of Sim-PowerCMP, we present a characterization of the energy-efficiency of a CMP for parallel scientific applications, paying special attention to the energy consumed on the interconnect. Results for an 8-and 16-core CMP show that the contribution of the interconnection network to the total power is close to 20%, on average, and that the most consuming messages are replies that carry data (almost 70% of total energy consumed in the interconnect).
2008 37th International Conference on Parallel Processing, 2008
Previous studies have shown that the interconnection network of a Chip-Multiprocessor (CMP) has s... more Previous studies have shown that the interconnection network of a Chip-Multiprocessor (CMP) has significant impact on both overall performance and energy consumption. Moreover, wires used in such interconnect can be designed with varying latency, bandwidth and power characteristics. In this work, we present a proposal for performance-and energy-efficient message management in tiled CMPs that combines both address compression with a heterogeneous interconnect. Our proposal consists of applying an address compression scheme that dynamically compresses the addresses within coherence messages allowing for a significant area slack. The arising area can be exploited for wire latency improvement by using a heterogeneous interconnection network comprised of a small set of very-low-latency wires for critical short-messages in addition to baseline wires. Detailed simulations of a 16-core CMP show that our proposal obtains average improvements of 10% in execution time and 38% in the Energy-Delay 2
Proceedings of the 16th international conference on Supercomputing - ICS '02, 2002
The reasons for performance losses due to conditional branch mispredictions are first studied. Br... more The reasons for performance losses due to conditional branch mispredictions are first studied. Branch misprediction penalties are broken into three categories: pipeline-fill penalty, window-fill penalty, and serialization penalty. The first and third of these produce most of the performance loss, but the second is also significant. Previously proposed dual (or multi) path execution methods attempt to reduce all three penalties, but these methods are also quite complex. Most of the complexity is caused by simultaneously executing instructions from multiple paths.
To obtain benefit of the increasing tran- sistor count in current processors, designs are lead- i... more To obtain benefit of the increasing tran- sistor count in current processors, designs are lead- ing to CMPs that will integrate tens or hundreds of processor cores on-chip. However, scaling and voltage factors are increasing susceptibility of architectures to transient, intermittent and permanent faults, as well as process variations. A very recent solution found in literature consists of Dynamic Core Coupling (DCC) (1). DCC provides a fault tolerant framework based on dynamic binding of cores for re-execution. This technique relies on the use of a shared-bus. However, for current and future CMP architectures, more ecient designs are tiled- CMPs, which are organized around a direct network, since area, scalability and power constraints make im- practical the use of a bus as the interconnection net- work. In this work, we present the changes needed in the original DCC proposal to be used for a direct net- work environment. These changes are mostly due to the replacement of a bus for ...
High performance processor designs have evolved toward architectures that integrate multiple proc... more High performance processor designs have evolved toward architectures that integrate multiple processing cores on the same chip. As the number of cores inside a Chip MultiProcessor (CMP) increases, the interconnection network will have significant impact on both overall performance and energy consumption as previous studies have shown. Moreover, wires used in such interconnect can be designed with varying latency, bandwidth and power characteristics. In this work, we show how messages can be efficiently managed in tiled CMP, from the point of view of both performance and energy, by combining both address compression with a heterogeneous interconnect. In particular, our proposal is based on applying an address compression scheme that dynamically compresses the addresses within coherence messages allowing for a significant area slack. The arising area is exploited for wire latency improvement by using a heterogeneous interconnection network comprised of a small set of very-low-latency wires for critical short-messages in addition to baseline wires. Detailed simulations of a 16-core CMP show that our proposal obtains average improvements of 10% in execution time and 38% in the energy-delay 2 product of the interconnect. Additionally, the sensitivity analysis shows that our proposal performs well when either OoO cores or caches with higher latencies are considered.
Energy consumption and power dissipation are important concerns in the design of embedded systems... more Energy consumption and power dissipation are important concerns in the design of embedded systems and they will become even more crucial with finer process geometry, higher frequencies, deeper pipelines and wider issue designs. In particular, the instruction cache consumes more energy than any other processor module, especially with commonly used highly associative CAM-based implementations.
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Papers by Juan L. Aragón