Papers by Luciano Agostini
2006 International Conference on Field Programmable Logic and Applications, 2006
Page 1. FPGA DESIGN OF A H.264/AVC MAIN PROFILE DECODER FOR HDTV Luciano V. Agostini, Arnaldo P. ... more Page 1. FPGA DESIGN OF A H.264/AVC MAIN PROFILE DECODER FOR HDTV Luciano V. Agostini, Arnaldo P. Azevedo Filho, Vagner S. Rosa, Eduardo A. Berriel, Tatiana G. S Santos, Sergio Bampi, Altamiro A. Susin Informatics ...
Complexity-Aware High Efficiency Video Coding, 2015
Complexity-Aware High Efficiency Video Coding, 2015
Complexity-Aware High Efficiency Video Coding, 2015
Este artigo apresenta o projeto de uma arquitetura para o cálculo da Transformada Discreta do Cos... more Este artigo apresenta o projeto de uma arquitetura para o cálculo da Transformada Discreta do Cosseno (DCT) em uma dimensão (1D). A aplicação alvo é a compressão de imagens digitais, mais especificamente, a compressão JPEG. A DCT é a essência da compressão JPEG, por isso o seu estudo e desenvolvimento é um dos fatores mais críticos em projetos de arquiteturas para compressores JPEG. O artigo apresenta o algoritmo escolhido para o cálculo da DCT 1D, a arquitetura desenvolvida e os resultados do mapeamento desta arquitetura para FPGAs da Altera. Como resultado final, a arquitetura desenvolvida gera uma matriz 8 x 8 de coeficientes da DCT 1D, a cada 7,27ms.
IEEE Transactions on Circuits and Systems for Video Technology, 2015
Este artigo apresenta o projeto de uma arquitetura para o cálculo da Transformada Discreta do Cos... more Este artigo apresenta o projeto de uma arquitetura para o cálculo da Transformada Discreta do Cosseno (DCT) em uma dimensão (1D). A aplicação alvo é a compressão de imagens digitais, mais especificamente, a compressão JPEG. A DCT é a essência da compressão JPEG, por isso o seu estudo e desenvolvimento é um dos fatores mais críticos em projetos de arquiteturas para compressores JPEG. O artigo apresenta o algoritmo escolhido para o cálculo da DCT 1D, a arquitetura desenvolvida e os resultados do mapeamento desta arquitetura para FPGAs da Altera. Como resultado final, a arquitetura desenvolvida gera uma matriz 8 x 8 de coeficientes da DCT 1D, a cada 7,27ms.
This work presents an algorithmic investigation of motion estimation (ME) in digital video compre... more This work presents an algorithmic investigation of motion estimation (ME) in digital video compression. This analysis is a solid evaluation of ME algorithms based on different criteria, targeting the best choice to be designed in software or hardware. This choice has a direct impact in the motion vector quality and in the motion estimator performance. Six algorithms and two subsamples techniques were investigated. All algorithms were developed in C and they use SAD as distortion criterion. For each algorithm, three block sizes and four different search area sizes were evaluated. The algorithms were applied to ten video sequences and their average results were considered in the presented evaluations.
2012 25th Symposium on Integrated Circuits and Systems Design, Aug 1, 2012
ABSTRACT This work presents a high throughput hardware design for the Adaptive Loop Filter (ALF) ... more ABSTRACT This work presents a high throughput hardware design for the Adaptive Loop Filter (ALF) cores, a new technique proposed by the High Efficiency Video Coding (HEVC), the emerging video coding standard, in order to improve the subjective video quality. The ALF is a part of the In-Loop Filter which also includes the Deblocking Filter (DF) and the Sample Adaptive Offset (SAO). These three filters are responsible to improve the final video quality, reducing the errors that are generated in all encoder steps. The ALF is a diamond-shaped filter and it has three sizes: 5×5, 7×7 and 9×9. This work proposes efficient hardware architectures for the filter cores of these three ALF sizes, with focus on real time processing of high definition videos. The architectures were described in VHDL and synthesized to an Altera FPGA, achieving 204MHz in the worst case, and consequently, reaching a minimum frame rate of 98 HD 1080p (1920×1080) frames per second for and 49 WQXGA (2560×1600) frames per second.
2014 Ieee Visual Communications and Image Processing Conference, Dec 1, 2014
This paper presents hardware solutions for the SATD (Sum of Absolute Transformed Differences) sim... more This paper presents hardware solutions for the SATD (Sum of Absolute Transformed Differences) similarity criterion calculation using the 2-D Hadamard transform. Two SATD versions were designed: one for 4x4 blocks and other for 8x8 blocks. This design focuses in the H.264/AVC video coding standard. The SATD criterion was compared with two other criteria commonly used in video coding: Sum of Squares of Differences (SSD) and Sum of Absolute Differences (SAD). The results obtained through this evaluation showed that SATD is a good solution, especially when high motion videos are being encoded. The designed architectures targets real time when processing high resolution videos, then a high level of parallelism was considered. The reached results encourage the use of SATD in video coding systems.
Este trabalho analisa o impacto do uso do Filtro Adaptativo de Laço (ALF -Adaptative Loop Filter)... more Este trabalho analisa o impacto do uso do Filtro Adaptativo de Laço (ALF -Adaptative Loop Filter) e do filtro de Deslocamento Adaptativo de Amostras (SAO -Samples Adaptative Offset), sendo ambos, filtros propostos pelo padrão de codificação emergente HEVC (High Efficiency Video Coding) [JCT-VC, 2011].
Journal of Internet Technology, Apr 15, 2013
2012 Proceedings of the 20th European Signal Processing Conference, Aug 1, 2012
ABSTRACT The High Efficiency Video Coding (HEVC) is an emerging standard that achieves higher enc... more ABSTRACT The High Efficiency Video Coding (HEVC) is an emerging standard that achieves higher encoding efficiency when compared to previous standards such as H.264/AVC. One key contributor to this improvement is the new intra prediction method that supports a large number of prediction directions at a cost of very high computational complexity. This paper presents a fast intra prediction mode decision algorithm, which instead of taking into account only the modes of the neighbor PUs (prediction units) uses edge information of the current PU to choose a reduced set of directions from which the best prediction mode (direction) is finally selected. The proposed method provides a decrease of up to 32.08% in the HEVC intra prediction processing time, with a little increase in the bit-rate (0.9% on average) and a negligible reduction in PSNR values.
Revista De Iniciacao Cientifica, Apr 2, 2013
Hifen, 2007
This work presents an evaluation of many motion estimation algorithms used in digital video compr... more This work presents an evaluation of many motion estimation algorithms used in digital video compression. All the studied algorithms were developed in software and use SAD as distortion criterion. For each algorithm, three versions were implemented, one for each block size, 4x4, 8x8 and 16x16 samples. The algorithms were evaluated with four different search area sizes, 46x46, 80x80, 144x144 and 208x208 samples. The algorithms were applied to ten video sequences and the average results were used to evaluate the algorithm performance. The quality and computational cost results are presented and evaluated.
Com o crescimento na demanda por vídeos com melhor qualidade e com maiores resoluções, a codifica... more Com o crescimento na demanda por vídeos com melhor qualidade e com maiores resoluções, a codificação de vídeo vem sendo cada vez mais um processo fundamental para tornar vídeos digitais viáveis. Sem esse processo, os vídeos requereriam um volume de dados muito grande, e essa informação precisa ser armazenada e eventualmente transmitida, o que faria com que não fosse possível, por exemplo, transmitir vídeos pela internet de forma eficiente. Além disso, dispositivos móveis capazes de gravar e transmitir vídeos são cada vez mais comuns na vida das pessoas, como smartphones, câmeras digitas, tablets e outros.
Hifen, Jul 15, 2008
This paper presents the design of four solutions for the Motion Compensation of H.264/AVC standar... more This paper presents the design of four solutions for the Motion Compensation of H.264/AVC standard. Three alternatives were designed for fixed size blocks with 16x16, 8x8 and 4x4 pixels, and one for multiple block sizes. Firstly, the solutions were implemented in software using C language. Then, the architectures were designed, described in VHDL and mapped to an Altera FPGA . Obtained results indicate that the software designs are more than 100 times slower than the hardware designs. The hardware designs, in worst case, are able to process more than 100 HDTV (1920x1080 pixels) frames per second. Resumo. Este artigo apresenta o desenvolvimento de quatro soluções para a Compensação de Movimento do padrão H.264/AVC. Foram desenvolvidas três alternativas utilizando blocos de tamanho fixo 16x16, 8x8 e 4x4 pixels e uma alternativa considerando blocos de tamanho variável. Primeiramente foram desenvolvidas soluções em software, utilizando C. Então as arquiteturas foram desenvolvidas, descritas em VHDL e mapeadas em um FPGA da Altera. Os resultados obtidos indicam que as implementações em software são mais de 100 vezes mais lentas do que as implementações em hardware. No pior caso, as implementações em hardware são capazes de processar mais 100 quadros HDTV (1920x1080 pixels) por segundo.
2014 Ieee Visual Communications and Image Processing Conference, Dec 1, 2014
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Papers by Luciano Agostini