Abstract Rapid, real-time detection of pathogenic microorganisms is an emerging evolving field of... more Abstract Rapid, real-time detection of pathogenic microorganisms is an emerging evolving field of research, especially for microorganisms that pose a major threat to public health. Alumina covered interdigitated capacitive microsensors were previously designed in our laboratory for DNA hybridization electrical detection (LOD of 30 nM target DNA). The device is constructed with standard CMOS materials.
ABSTRACT Low-power and high-temperature sensors and MEMS designs based on bulk, SOI and IC compat... more ABSTRACT Low-power and high-temperature sensors and MEMS designs based on bulk, SOI and IC compatible materials and processes are presented here. Target markets are in general public sensors for UV, ozone, CO, liquids presence, eg in mobile devices. Or in health, sensors for the medical diagnosis (DNA, RNA, bacteria, viruses). Simple, low cost and low consumption devices are required in medical applications.
We present a new fully self-aligned single-electron memory with a single pair of nano floating ga... more We present a new fully self-aligned single-electron memory with a single pair of nano floating gates, made of different materials (Si and Ge). The energy barrier that prevents stored charge leakage is induced not only by quantum effects but also by the conduction-band offset that arises between Ge and Si. The dimensions and position of each floating gate are well-defined and controlled. The devices exhibit a long retention time and single-electron injection at room temperature.
ABSTRACT Actual challenges in analog HF applications require both design and technique approaches... more ABSTRACT Actual challenges in analog HF applications require both design and technique approaches to achieve an optimal solution. In this paper, a low-voltage SOI transconductor topology for HF operation is presented. The structure has DC-gain tuning capability by using a controllable Negative Load Resistance (NLR) and high bandwidth due to the low values of parasitic capacitors–even for a 2 µm technology–.
Résumé La mémoire est un élément incontournable de tout circuit électronique; le développement de... more Résumé La mémoire est un élément incontournable de tout circuit électronique; le développement des applications analogiques basse puissance et basse tension sera conditionné par la disponibilité de points mémoire présentant ces mêmes caractéristiques. Dans cet article, nous examinons les possibilités de réaliser un point mémoire analogique permanent en technologie SOI qui soit adapté aux circuits basse puissance, alimentés sous faible tension.
Abstract A new method for extracting the carrier recombination lifetime in dual-gate silicon-on-i... more Abstract A new method for extracting the carrier recombination lifetime in dual-gate silicon-on-insulator (SOI) structures is proposed. The experiment, model, and numerical simulations indicate that an excess forward current is obtained when carrier recombination occurs in the whole film volume.
Based on an extensive review of research results on the material, process, device and circuit pro... more Based on an extensive review of research results on the material, process, device and circuit properties of thin-film fully depleted SOI CMOS, our work demonstrates that such a process with channel lengths of about 1 μm may emerge as a most promising and mature contender for integrated microsystems which must operate under low-voltage low-power conditions, at microwave frequencies and/or in the temperature range 200–350° C.
ABSTRACT In this paper an overall analysis on the matching properties of Graded-Channel (GC) SOI ... more ABSTRACT In this paper an overall analysis on the matching properties of Graded-Channel (GC) SOI MOSFETs in comparison to conventional SOI transistors is performed. Experimental results show that GC devices present poorer matching behavior in comparison to conventional SOI counterpart for equal mask channel length, whereas for same effective channel length, almost the same matching behavior. The analytical model for the drain current of GC devices is used to investigate the reasons for this matching worsening.
SOI stands for Silicon-on-Insulator. The basic difference with conventional bulk silicon indeed l... more SOI stands for Silicon-on-Insulator. The basic difference with conventional bulk silicon indeed lies in the starting material (Fig. 1):-in bulk Si, the active devices are built atop the surface of a wafer of monocristalline silicon.-in SOI, the top Si active layer is separated from the underlying mechanical substrate by a thick insulating layer, which leads to a number of advantageous device and circuit properties when compared to bulk Si.
An extended study of analog circuit design using graded-channel (GC) silicon-on-insulator (SOI) M... more An extended study of analog circuit design using graded-channel (GC) silicon-on-insulator (SOI) MOSFETs in comparison to conventional fully depleted (FD) transistors is performed. Performances of single-transistor operational transconductance amplifier (OTA) implemented using GC and conventional FD SOI nMOSFETs are compared.
Abstract The low temperature electrical behavior of adjacent silicide/Si Schottky contacts with o... more Abstract The low temperature electrical behavior of adjacent silicide/Si Schottky contacts with or without dopant segregation is investigated. The electrical characteristics are very well modeled by thermionic-field emission for nonsegregated contacts separated by micrometer-sized gaps. Still, an excess of current occurs at low temperature for short contact separations or dopant-segregated contacts when the voltage applied to the device is sufficiently high.
The electron mobility and concentration in double-gate silicon-on-insulator (SOI) gate-all-around... more The electron mobility and concentration in double-gate silicon-on-insulator (SOI) gate-all-around transistors is extracted by Hall effect measurements at room and liquid nitrogen temperature. The Hall mobility is compared with the drift mobility determined from the transconductance measurement of the devices in strong inversion. The results of this study indicate that the method based on ID/(gm) 0.5 provides acceptable values for the drift mobility.
An extended study of the occurrence of inherent parasitic bipolar effects in conventional and gra... more An extended study of the occurrence of inherent parasitic bipolar effects in conventional and graded-channel fully depleted silicon-on-insulator nMOSFETs is carried out. The graded-channel device is a new asymmetric channel MOSFET, fabricated through a simple process variation.
The purpose of this paper is to completely describe the low and high frequency performance includ... more The purpose of this paper is to completely describe the low and high frequency performance including microwave noise parameters of 0.25 μm fully depleted (FD) silicon-on-insulator (SOI) devices and to compare the noise performance with 0.25 μm partially depleted (PD) devices. These FD devices present a state of the art NFmin of 0.8 dB and high Gass of 13 dB at 6 GHz, at V ds= 0.75 V, P dc< 3 mW at 80 μm total gate width.
In this paper, we investigate and optimize the static characteristics of NPN lateral bipolar tran... more In this paper, we investigate and optimize the static characteristics of NPN lateral bipolar transistors implemented in a thin-film fully-depleted SOI CMOS process for high-temperature analog applications. The basic lateral SOI bipolar device, which shows good behaviour in high-temperature circuits in spite of its relatively poor performances, is firstly described regarding its process and layout parameters. Then the concept of the graded-base bipolar transistor is introduced.
The main interface and interconnection materials normally used in complementary metal-oxide semic... more The main interface and interconnection materials normally used in complementary metal-oxide semiconductor (CMOS) integrated circuit processing, ie silicon oxides and aluminum, were evaluated with regards to deoxyribonucleic acid (DNA) attachment. We investigated and quantified the influence of various techniques of fabrication of the silicon oxide on DNA binding obtained by four different biochemical processes.
Abstract The present paper describes a systematic straightforward design of a Σ-Δ fractional-N Ph... more Abstract The present paper describes a systematic straightforward design of a Σ-Δ fractional-N Phase-Locked Loop based on HDL behavioral modeling. The proposed design consists in describing the mixed mode behavior of this Σ-Δ fractional-N PLL architecture starting from the specifications of each building block. The HDL models of critical PLL blocks have been described in VHDL-AMS to predict the different over-all specifications. The effect of different noise sources has been accurately introduced to study the PLL system performances.
Abstract—Ultra-low-power and static CMOS full adders are implemented in a 0.15 µm FD SOI CMOS tec... more Abstract—Ultra-low-power and static CMOS full adders are implemented in a 0.15 µm FD SOI CMOS technology with 1.5 V supply. The power consumption of ultra-low-power full adder is shown to be half that of static CMOS. These results are confirmed by both measurements and SPICE simulations in different corners of operation.
Abstract Progress of integrated circuit technology allows integration of analog and digital circu... more Abstract Progress of integrated circuit technology allows integration of analog and digital circuits on the same chip. This co-integration yields higher performances and reliability, while reducing power consumption, but also raises new challenges for circuit designers. The substrate noise generated by the switching digital part has detrimental effects on the analog part. In this contribution, a wide-band characterization of the so-called “digital substrate noise” is realized, in bulk and in SOI technology.
The development of new integrated high-speed Si receivers is requested for short distance optical... more The development of new integrated high-speed Si receivers is requested for short distance optical data link and emerging optical storage (OS) systems, notably for the Gb/s Ethernet standard [1]-[8] and Blue DVD (Blu-Ray, HDDVD)[3],[4],[9]. As requirements on band‐width, gain, power consumption as well as low read-out noise and cost are quite severe, an optimal design strategy of a monolithically integrated solution, ie with on-chip photodetec‐tor and transimpedance amplifier (TIA), is required.
Abstract Rapid, real-time detection of pathogenic microorganisms is an emerging evolving field of... more Abstract Rapid, real-time detection of pathogenic microorganisms is an emerging evolving field of research, especially for microorganisms that pose a major threat to public health. Alumina covered interdigitated capacitive microsensors were previously designed in our laboratory for DNA hybridization electrical detection (LOD of 30 nM target DNA). The device is constructed with standard CMOS materials.
ABSTRACT Low-power and high-temperature sensors and MEMS designs based on bulk, SOI and IC compat... more ABSTRACT Low-power and high-temperature sensors and MEMS designs based on bulk, SOI and IC compatible materials and processes are presented here. Target markets are in general public sensors for UV, ozone, CO, liquids presence, eg in mobile devices. Or in health, sensors for the medical diagnosis (DNA, RNA, bacteria, viruses). Simple, low cost and low consumption devices are required in medical applications.
We present a new fully self-aligned single-electron memory with a single pair of nano floating ga... more We present a new fully self-aligned single-electron memory with a single pair of nano floating gates, made of different materials (Si and Ge). The energy barrier that prevents stored charge leakage is induced not only by quantum effects but also by the conduction-band offset that arises between Ge and Si. The dimensions and position of each floating gate are well-defined and controlled. The devices exhibit a long retention time and single-electron injection at room temperature.
ABSTRACT Actual challenges in analog HF applications require both design and technique approaches... more ABSTRACT Actual challenges in analog HF applications require both design and technique approaches to achieve an optimal solution. In this paper, a low-voltage SOI transconductor topology for HF operation is presented. The structure has DC-gain tuning capability by using a controllable Negative Load Resistance (NLR) and high bandwidth due to the low values of parasitic capacitors–even for a 2 µm technology–.
Résumé La mémoire est un élément incontournable de tout circuit électronique; le développement de... more Résumé La mémoire est un élément incontournable de tout circuit électronique; le développement des applications analogiques basse puissance et basse tension sera conditionné par la disponibilité de points mémoire présentant ces mêmes caractéristiques. Dans cet article, nous examinons les possibilités de réaliser un point mémoire analogique permanent en technologie SOI qui soit adapté aux circuits basse puissance, alimentés sous faible tension.
Abstract A new method for extracting the carrier recombination lifetime in dual-gate silicon-on-i... more Abstract A new method for extracting the carrier recombination lifetime in dual-gate silicon-on-insulator (SOI) structures is proposed. The experiment, model, and numerical simulations indicate that an excess forward current is obtained when carrier recombination occurs in the whole film volume.
Based on an extensive review of research results on the material, process, device and circuit pro... more Based on an extensive review of research results on the material, process, device and circuit properties of thin-film fully depleted SOI CMOS, our work demonstrates that such a process with channel lengths of about 1 μm may emerge as a most promising and mature contender for integrated microsystems which must operate under low-voltage low-power conditions, at microwave frequencies and/or in the temperature range 200–350° C.
ABSTRACT In this paper an overall analysis on the matching properties of Graded-Channel (GC) SOI ... more ABSTRACT In this paper an overall analysis on the matching properties of Graded-Channel (GC) SOI MOSFETs in comparison to conventional SOI transistors is performed. Experimental results show that GC devices present poorer matching behavior in comparison to conventional SOI counterpart for equal mask channel length, whereas for same effective channel length, almost the same matching behavior. The analytical model for the drain current of GC devices is used to investigate the reasons for this matching worsening.
SOI stands for Silicon-on-Insulator. The basic difference with conventional bulk silicon indeed l... more SOI stands for Silicon-on-Insulator. The basic difference with conventional bulk silicon indeed lies in the starting material (Fig. 1):-in bulk Si, the active devices are built atop the surface of a wafer of monocristalline silicon.-in SOI, the top Si active layer is separated from the underlying mechanical substrate by a thick insulating layer, which leads to a number of advantageous device and circuit properties when compared to bulk Si.
An extended study of analog circuit design using graded-channel (GC) silicon-on-insulator (SOI) M... more An extended study of analog circuit design using graded-channel (GC) silicon-on-insulator (SOI) MOSFETs in comparison to conventional fully depleted (FD) transistors is performed. Performances of single-transistor operational transconductance amplifier (OTA) implemented using GC and conventional FD SOI nMOSFETs are compared.
Abstract The low temperature electrical behavior of adjacent silicide/Si Schottky contacts with o... more Abstract The low temperature electrical behavior of adjacent silicide/Si Schottky contacts with or without dopant segregation is investigated. The electrical characteristics are very well modeled by thermionic-field emission for nonsegregated contacts separated by micrometer-sized gaps. Still, an excess of current occurs at low temperature for short contact separations or dopant-segregated contacts when the voltage applied to the device is sufficiently high.
The electron mobility and concentration in double-gate silicon-on-insulator (SOI) gate-all-around... more The electron mobility and concentration in double-gate silicon-on-insulator (SOI) gate-all-around transistors is extracted by Hall effect measurements at room and liquid nitrogen temperature. The Hall mobility is compared with the drift mobility determined from the transconductance measurement of the devices in strong inversion. The results of this study indicate that the method based on ID/(gm) 0.5 provides acceptable values for the drift mobility.
An extended study of the occurrence of inherent parasitic bipolar effects in conventional and gra... more An extended study of the occurrence of inherent parasitic bipolar effects in conventional and graded-channel fully depleted silicon-on-insulator nMOSFETs is carried out. The graded-channel device is a new asymmetric channel MOSFET, fabricated through a simple process variation.
The purpose of this paper is to completely describe the low and high frequency performance includ... more The purpose of this paper is to completely describe the low and high frequency performance including microwave noise parameters of 0.25 μm fully depleted (FD) silicon-on-insulator (SOI) devices and to compare the noise performance with 0.25 μm partially depleted (PD) devices. These FD devices present a state of the art NFmin of 0.8 dB and high Gass of 13 dB at 6 GHz, at V ds= 0.75 V, P dc< 3 mW at 80 μm total gate width.
In this paper, we investigate and optimize the static characteristics of NPN lateral bipolar tran... more In this paper, we investigate and optimize the static characteristics of NPN lateral bipolar transistors implemented in a thin-film fully-depleted SOI CMOS process for high-temperature analog applications. The basic lateral SOI bipolar device, which shows good behaviour in high-temperature circuits in spite of its relatively poor performances, is firstly described regarding its process and layout parameters. Then the concept of the graded-base bipolar transistor is introduced.
The main interface and interconnection materials normally used in complementary metal-oxide semic... more The main interface and interconnection materials normally used in complementary metal-oxide semiconductor (CMOS) integrated circuit processing, ie silicon oxides and aluminum, were evaluated with regards to deoxyribonucleic acid (DNA) attachment. We investigated and quantified the influence of various techniques of fabrication of the silicon oxide on DNA binding obtained by four different biochemical processes.
Abstract The present paper describes a systematic straightforward design of a Σ-Δ fractional-N Ph... more Abstract The present paper describes a systematic straightforward design of a Σ-Δ fractional-N Phase-Locked Loop based on HDL behavioral modeling. The proposed design consists in describing the mixed mode behavior of this Σ-Δ fractional-N PLL architecture starting from the specifications of each building block. The HDL models of critical PLL blocks have been described in VHDL-AMS to predict the different over-all specifications. The effect of different noise sources has been accurately introduced to study the PLL system performances.
Abstract—Ultra-low-power and static CMOS full adders are implemented in a 0.15 µm FD SOI CMOS tec... more Abstract—Ultra-low-power and static CMOS full adders are implemented in a 0.15 µm FD SOI CMOS technology with 1.5 V supply. The power consumption of ultra-low-power full adder is shown to be half that of static CMOS. These results are confirmed by both measurements and SPICE simulations in different corners of operation.
Abstract Progress of integrated circuit technology allows integration of analog and digital circu... more Abstract Progress of integrated circuit technology allows integration of analog and digital circuits on the same chip. This co-integration yields higher performances and reliability, while reducing power consumption, but also raises new challenges for circuit designers. The substrate noise generated by the switching digital part has detrimental effects on the analog part. In this contribution, a wide-band characterization of the so-called “digital substrate noise” is realized, in bulk and in SOI technology.
The development of new integrated high-speed Si receivers is requested for short distance optical... more The development of new integrated high-speed Si receivers is requested for short distance optical data link and emerging optical storage (OS) systems, notably for the Gb/s Ethernet standard [1]-[8] and Blue DVD (Blu-Ray, HDDVD)[3],[4],[9]. As requirements on band‐width, gain, power consumption as well as low read-out noise and cost are quite severe, an optimal design strategy of a monolithically integrated solution, ie with on-chip photodetec‐tor and transimpedance amplifier (TIA), is required.
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Papers by Denis Flandre