This study presents a detection system with a prototype acquisition module and display interface ... more This study presents a detection system with a prototype acquisition module and display interface for capacitive plantar pressure monitoring. The detection system mainly focuses on a systemlevel design (not a system on chip). The prototype acquisition module consists of commercial ICs and self-designed chips: A capacitance-to-voltage converter (CVC) and a 10-bit fully differential successive approximation register analog-to-digital converter are fabricated by the TSMC 0.18 µm 1P6M 3.3 V process. The feature of the CVC is selectable for the detection points from 1 to 64, which is controlled by the digital codes of a field-programmable gate array (FPGA). It also has the embedded functions of crosstalk attenuation (CA) for cross-type capacitive sensors and a self-separated input signal for capacitive plantar pressure monitoring. The CA can effectively reduce parasitic capacitances and influences of the temperature and relative humidity of the environment: An M×N array only requires M + N tracks of I/O ports to reduce detected complexity. The measured results shown on the display interfaces reveal the positions and amplitudes (voltage swings) of the corresponding capacitances. The conversion time for one capacitance is 0.4 ms, and the maximum conversion time for 64 capacitances is 25.6 ms. A handmade cross-type capacitive array and a cross-type capacitive plantar pressure sensor are used to demonstrate the detection system.
2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2016
This paper presents a highly efficient magnetically coupled rectifier IC for the 13.56 MHz ISM fr... more This paper presents a highly efficient magnetically coupled rectifier IC for the 13.56 MHz ISM frequency band. By converting conventional analog building blocks into the proposed clocked circuits, this rectifier IC achieves peak power conversion efficiency (PCE) and peak voltage conversion ratio (VCR) of 96% and 94%, respectively. The maximum output power using a 50Ω load is 162.45mW. The ASIC implemented in UMC 0.18um CMOS has an area with pads of 0.574 mm × 0.356 mm and the active area is 0.0274 mm2 only. The achieved power density of 5928.83 mW/mm2 is the highest reported up-to-date.
IEEE Transactions on Biomedical Circuits and Systems, 2018
This paper presents a systematic method for decreasing the amount of transconductors used by an o... more This paper presents a systematic method for decreasing the amount of transconductors used by an operational transconductance amplifier-capacitor (OTA-C) filter to decrease the power consumption and the active area. An OTA with a localfeedback linearized technique and a transconductance booster is proposed based on the presented method. The proposed OTA combines current division with source degeneration to enhance linearity and implement low transconductance. This topology enables the proposed OTA to drive multiple integration capacitors without an additional output stage. The OTA-based circuit realizes low power consumption by operating under a weak inversion at a supply voltage of 1 V. Thus, a fifth-order laddertype low-pass Butterworth OTA-C filter is implemented for the acquisition of electrocardiograph (ECG) signals. The proposed method is validated using a prototype fabricated through a 1P6M 0.18-μm CMOS process. Results show that in ECG signal acquisition, the proposed filter has a signal bandwidth located within 250 Hz, a dynamic range of 61.2 dB, and a power consumption of 41 nW to achieve a figure-of-merit of 5.4 × 10 −13. The active area of the filter is 0.24 mm 2 .
2015 International Symposium on Bioelectronics and Bioinformatics (ISBB), 2015
An analog front-end circuit system, which includes an adaptive sigma-delta modulator (SDM) with a... more An analog front-end circuit system, which includes an adaptive sigma-delta modulator (SDM) with a wide dynamic range and a low power consumption, is proposed for an electroencephalogram acquisition system. The required loop filter for the SDM is implemented using Gm-C integrators, which can significantly reduce power consumption and facilitate flexible coefficient adjustment. The performance of the detection system is also improved by employing an adaptive structure and a dynamic range extension algorithm. The system includes a chopper, an SDM, a digital filter with a chopper, and a calibration unit. Circuit simulation reveals that the dynamic range can be extended by more than 40 dB, and accurate results are achieved by the proposed brain signal acquisition system.
International Symposium on Bioelectronics and Bioinformations 2011, 2011
ABSTRACT This paper presents a low-power RF-transmitter for intelligent healthcare systems. With ... more ABSTRACT This paper presents a low-power RF-transmitter for intelligent healthcare systems. With attention to power-efficient communication in the local sensor network, the required low-power integrated circuits (ICs) are developed for a healthcare system with miniaturization and system integration. A quadrature CMOS voltage-controlled oscillator and a direct-conversion transmitter with PA and up-conversion mixer have been implemented to fit the specification of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the transmitter have been applied in the TSMC 0.18-μm CMOS standard process. The measurement results reveal that the transmitter IC can fit in with the link budget of the UHF ZigBee system for healthcare applications.
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.
ABSTRACT The modified switched-capacitor biquad circuits for low-Q and high-Q structures are pres... more ABSTRACT The modified switched-capacitor biquad circuits for low-Q and high-Q structures are presented in This work. By using the switched-opamp technique, the structures make only one active opamp in each phase without destroying their biquad functions. This idea can be applied on the implementation of high-order SC filters to save more power consumption. Meanwhile, the z-domain transfer functions for SC biquad circuits are analyzed to verify the modified structures. Finally, three types of low-Q SC biquad filters are presented as design examples. The simulation results show that the frequency responses of the general active-RC biquad circuits and the modified SC ones are much similar.
2010 IEEE Asia Pacific Conference on Circuits and Systems, 2010
ABSTRACT Inductive coupling is commonly used for wireless power and data transfer in biomedical t... more ABSTRACT Inductive coupling is commonly used for wireless power and data transfer in biomedical telemetry systems. The capability of telemetry module to communicate with the inside of the body makes it possible to transmit the control signal into the implant electronic devices and process the detected inner biophysical signal externally by back-telemetry. On the other hand, the telemetry module inside is capable of converting the radio-frequency (RF) energy delivered through the body tissue into DC as the supply for the implanted device. In this paper, a novel wireless power and data receiver is presented to receive RF signal and generates 1-V DC supply voltage for the sequent device. The overall circuits with core area of 0.07 mm2 have been implemented in a TSMC 0.35μm 2P4M standard CMOS process technology. Measured result shows that the low-power on-chip LDO regulator provides a stable 1-V DC supply voltage and the digital data as well as the 256-kHz clock are obtained precisely.
This paper presents a 10-channel time-of-flight application-specific integrated circuit (ASIC) fo... more This paper presents a 10-channel time-of-flight application-specific integrated circuit (ASIC) for positron emission tomography in a 90 nm standard CMOS process. To overcome variations in channel-to-channel timing resolution caused by mismatch and process variations, adaptive biases and a digital-toanalog converter (DAC) are utilized. The main contributions of this work are as follows. First, multistage architectures reduce the total power consumption, and detection bandwidths of analog preamplifiers and comparators are increased to 1 and 1.5 GHz, respectively, relative to those in previous studies. Second, a total intrinsic electronic timing resolution of 9.71 ps root-mean-square (RMS) is achieved (13.88 ps peak and 11.8 ps average of the 10 channels in 5 ASICs). Third, the proposed architecture reduces variations in channel-to-channel timing resolution to 2.6 bits (equivalent to 4.17 ps RMS) by calibrating analog comparator threshold levels. A 181.5 ps full-width-at-half-maximum timing resolution is measured with an avalanche photo diode and a laser setup. The power consumption is 2.5 mW using 0.5 and 1.2 V power supplies. The proposed ASIC is implemented in a 90 nm TSMC CMOS process with a total area of 3.3 mm × 2.7 mm. Index Terms-Adaptive bias, analog comparator, digital-toanalog converter (DAC), front-end, positron emission tomography (PET), time-of-flight (TOF).
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.
ABSTRACT A speech codec including four main blocks, a class AB switched-current sigma-delta modul... more ABSTRACT A speech codec including four main blocks, a class AB switched-current sigma-delta modulator (SDM), a decimator, an interpolator, and a sigma-delta demodulator (SDDM) is presented. In order to achieve low-power consumption and wide dynamic range, a novel class AB switched-current (SI) integrator is adopted to implement the SDM with over-sampling ratio (OSR) of 64. In addition, design of a reduced-multiplier structure is proposed and applied to the finite impulse response (FIR) filters of the decimator and the interpolator which both of them share the most of hardware in the implementation. Therefore, the number of multipliers and the chip area are reduced. The speech codec was implemented using the TSMC 0.35μm 2P4M standard CMOS process technology. Simulation results with an input of 1kHz sinusoidal wave in the 4 kHz bandwidth show that the speech codec has a maximum signal-to-noise and distortion ratio (SNDR) of 46dB and dynamic range over 65dB with a single 2.5V supply voltage.
2009 IEEE International Symposium on Circuits and Systems, 2009
In this paper, a 1-V 8-bit 10 kS/s successive approximation (SA) analog-to-digital converter (ADC... more In this paper, a 1-V 8-bit 10 kS/s successive approximation (SA) analog-to-digital converter (ADC) with ultra-low power characteristic is implemented for biosignal acquisition systems. To decrease power consumption, a passive sample-and-hold (SH) circuit and an opamp-free, capacitor-based digital-to-analog converter (DAC) are utilized. The only active circuit, a comparator, is implemented in the sub-threshold region to preserve the required bias current. According to the measured results, the ADC has a signal-to-noise distortion ratio (SNDR) of 45.2 dB, and peak spurious free dynamic range (SFDR) of 54 dB for a 1 kHz 500 mV pp input sine wave. The effective number of bits (ENOB) is 7.2. Its differential nonlinearity (DNL) and integral nonlinearity (INL) are-0.41/+0.38 and-0.89/+0.6 LSB, respectively. The total power consumption is 950 nW, and the figure of merit (FOM) is 3230 fJ/conversion-step. The active area, which is 0.93 x 0.93 mm 2 , is determined by using TSMC 0.18μm 1P6M CMOS process.
IEEE Transactions on Circuits and Systems II: Express Briefs, 2008
Abstract A quadrature voltage-controlled oscillator (QVCO) with a wide tuning range is proposed a... more Abstract A quadrature voltage-controlled oscillator (QVCO) with a wide tuning range is proposed and implemented in the TSMC 0.18-mum CMOS process. The said QVCO uses a cross-coupled structure and a current-reuse technology to produce the quadrature signal ...
IEEE Transactions on Circuits and Systems I: Regular Papers, 2006
Abstract An ultralow-voltage and low-power adaptive sigma-delta analog-to-digital converter (SDAD... more Abstract An ultralow-voltage and low-power adaptive sigma-delta analog-to-digital converter (SDADC) with a 10-bit dynamic range for bio-microsystem applications is presented. The proposed SDADC includes a switched-current sigma-delta modulator (SISDM) and a ...
A system design with new empirical stability criteria for sigma-delta modulators is proposed. The... more A system design with new empirical stability criteria for sigma-delta modulators is proposed. The stability criteria is a cubic function obtained by the least square method, and simulations including coefficients variation due to component mismatches of circuit ...
IEEE Transactions on Biomedical Circuits and Systems, 2021
Epilepsy is a common clinical disease. Severe epilepsy can be life-threatening in certain unexpec... more Epilepsy is a common clinical disease. Severe epilepsy can be life-threatening in certain unexpected conditions, so it is important to detect seizures instantly with a wearable device and to provide treatment within the golden window. The observation of the electroencephalography (EEG) signal is an imperative method to assist correct epilepsy diagnosis. To detect and classify EEG signals, a convolutional neural network (CNN) is an intuitive and appropriate method that borrows expertise from neurologists. However, the computational cost of training and inference on artificial intelligence (AI)-based solutions make software-only and hardware-only solutions incompetent for real-time monitoring on embedded devices. Hence, this study proposes three key contributions for the challenge, namely, an algorithm framework to provide real-time epilepsy detection, a dedicated coprocessor chip implementing this framework to enable real time epilepsy detection to offload and accelerate detection algorithm, and a custom interface with the coprocessor and reduced instruction set computer-V (RISC-V) instructions to reconfigure the coprocessor and transfer data. The epilepsy detection framework is implemented in 11-layer CNN. The proposed epilepsy detection algorithm performs 97.8% accuracy for floating-point and 93.5% for fixed-point operations through animal experiments with lab rats. The RISC-V CNN coprocessor is fabricated in the TSMC 0.18-μm CMOS process. For each classification, the coprocessor consumes 51 nJ/class. and 0.9 µJ/class. energy on data transfer and inference, respectively. The detection latency on the chip is 0.012 s. With the integration of the hardware coprocessor, AI algorithms can be applied to epilepsy detection for real-time monitoring.
IEEE Transactions on Biomedical Circuits and Systems, 2021
This work presents a portable wireless urine detection system which consists of an electrochemica... more This work presents a portable wireless urine detection system which consists of an electrochemical readout application specific integrated circuit (ASIC) and a biosensor composed of 2, 2'-azino-bis(3-ethylbenzothiazoline-6-sulphonic acid) and carbon nanotube (ABTS-CNT) for the detection of urine albumin-to-creatinine ratio (UACR). The ASIC includes a potentiostat, a digital circuitry and a power management circuit which can perform electrochemistry techniques with a dual-channel screen-printing carbon electrode (SPCE). Electrochemical experiments on the proposed biosensor (SPCE|ABTS-CNT|Nafion) have revealed promising sensing characteristics for creatinine and human serum albumin detection. Practical urine tests has demonstrated the capability of the proposed urine detection system for UACR detection with both the power-efficient readout ASIC and the ABTS-CNT biosensor. A user-friendly prototype has also been designed which can be useful for either personal health administrationor homecare.
IEEE Transactions on Biomedical Circuits and Systems, 2020
This paper presents a high energy efficiency, highintegrated, and low-power on-off keying transce... more This paper presents a high energy efficiency, highintegrated, and low-power on-off keying transceiver for a 2.4 GHz industrial scientific medical band. The proposed receiver includes an input matching network, a low-noise amplifier, a novel single-to-differential envelope detector, a level shifter, cascaded baseband amplifiers, and a hysteresis comparator. The proposed transmitter includes a bias-stimulating circuit, a current-reused self-mixing voltage controlled oscillator, and a quadruple-transconductance power amplifier. Numerous proposed techniques implemented in the mentioned circuits improve the energy per bit and power efficiency. Therefore, the proposed receiver for short-distanced propagation can achieve a sensitivity of −46 dBm with a carrier frequency of 2.45 GHz and a high data rate of 2 Mbps. The proposed transmitter achieves an output power of −17 dBm with a high data rate of 20 Mbps. This work is fabricated in a TSMC 0.18 μm CMOS process and consumes 160 W and 0.6 mW in the receiver and transmitter, respectively, from a 1.2 V supply voltage. The energy per bit of 80 pJ/bit in the receiver part and the figure of merit of 9 in the transmitter part are better than those of existing state-of-the-art transceivers.
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019
A 1024-point single-bin discrete Fourier transform (SBDFT)-based digital calibration technique is... more A 1024-point single-bin discrete Fourier transform (SBDFT)-based digital calibration technique is presented for high-performance, full-code successive approximation (SAR) analog-to-digital converters (ADCs). This proposed method can evaluate the radix error in capacitor-DAC (CDAC), which deviates from the designed value. Thus, the corrected digital output codes are generated to compensate the error, thereby reducing the harmonic distortion caused by capacitor mismatch. Moreover, the proposed algorithm adopts a recursive SBDFT computation rather than a conventional fast Fourier transform (FFT) computation methods because the simple hardware, which reduces hardware complexity and power consumption, can be achieved to calculate a certain bin in this work. The effective number of bits (ENOB) and signal-to-noise ratio (SNDR) can be enhanced by approximately 2 bits and 14.52 dB, respectively, on the basis of the simulation result of a 12-bit SAR ADC behavior model with 0.3% capacitor mismatch. The proposed SAR ADC is fabricated in TSMC 0.18 µ m 1P6M technology. Measurement results explain that the SNDR, spurious free dynamic range, and ENOB are 46.49/67.28 dB, 49.66/80.73 dB, and 7.43/10.88 bits before/after calibration, respectively, wherein the power supply is 3.3 V and the input signal frequency is 2 kHz with a sampling rate of 100 kS/s.
2015 International Symposium on Bioelectronics and Bioinformatics (ISBB), 2015
This study proposes an electrocardiographic (ECG) monitoring and emotion stabilization system tha... more This study proposes an electrocardiographic (ECG) monitoring and emotion stabilization system that is composed of an acquisition system on chip and an Android system. This system has three main parts. The first part is a low-power analog front-end circuit for biosignal sensing. The second part comprises a digital signal processor for down sampling, filtering, and QRS detection. The last part is an emotion stabilization feedback control based on an Android-operated physiological information platform. This platform allows physiological information display, data recording, signal processing, and analysis. All circuits are fabricated in a TSMC 0.18 μm standard CMOS process.
This study presents a detection system with a prototype acquisition module and display interface ... more This study presents a detection system with a prototype acquisition module and display interface for capacitive plantar pressure monitoring. The detection system mainly focuses on a systemlevel design (not a system on chip). The prototype acquisition module consists of commercial ICs and self-designed chips: A capacitance-to-voltage converter (CVC) and a 10-bit fully differential successive approximation register analog-to-digital converter are fabricated by the TSMC 0.18 µm 1P6M 3.3 V process. The feature of the CVC is selectable for the detection points from 1 to 64, which is controlled by the digital codes of a field-programmable gate array (FPGA). It also has the embedded functions of crosstalk attenuation (CA) for cross-type capacitive sensors and a self-separated input signal for capacitive plantar pressure monitoring. The CA can effectively reduce parasitic capacitances and influences of the temperature and relative humidity of the environment: An M×N array only requires M + N tracks of I/O ports to reduce detected complexity. The measured results shown on the display interfaces reveal the positions and amplitudes (voltage swings) of the corresponding capacitances. The conversion time for one capacitance is 0.4 ms, and the maximum conversion time for 64 capacitances is 25.6 ms. A handmade cross-type capacitive array and a cross-type capacitive plantar pressure sensor are used to demonstrate the detection system.
2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2016
This paper presents a highly efficient magnetically coupled rectifier IC for the 13.56 MHz ISM fr... more This paper presents a highly efficient magnetically coupled rectifier IC for the 13.56 MHz ISM frequency band. By converting conventional analog building blocks into the proposed clocked circuits, this rectifier IC achieves peak power conversion efficiency (PCE) and peak voltage conversion ratio (VCR) of 96% and 94%, respectively. The maximum output power using a 50Ω load is 162.45mW. The ASIC implemented in UMC 0.18um CMOS has an area with pads of 0.574 mm × 0.356 mm and the active area is 0.0274 mm2 only. The achieved power density of 5928.83 mW/mm2 is the highest reported up-to-date.
IEEE Transactions on Biomedical Circuits and Systems, 2018
This paper presents a systematic method for decreasing the amount of transconductors used by an o... more This paper presents a systematic method for decreasing the amount of transconductors used by an operational transconductance amplifier-capacitor (OTA-C) filter to decrease the power consumption and the active area. An OTA with a localfeedback linearized technique and a transconductance booster is proposed based on the presented method. The proposed OTA combines current division with source degeneration to enhance linearity and implement low transconductance. This topology enables the proposed OTA to drive multiple integration capacitors without an additional output stage. The OTA-based circuit realizes low power consumption by operating under a weak inversion at a supply voltage of 1 V. Thus, a fifth-order laddertype low-pass Butterworth OTA-C filter is implemented for the acquisition of electrocardiograph (ECG) signals. The proposed method is validated using a prototype fabricated through a 1P6M 0.18-μm CMOS process. Results show that in ECG signal acquisition, the proposed filter has a signal bandwidth located within 250 Hz, a dynamic range of 61.2 dB, and a power consumption of 41 nW to achieve a figure-of-merit of 5.4 × 10 −13. The active area of the filter is 0.24 mm 2 .
2015 International Symposium on Bioelectronics and Bioinformatics (ISBB), 2015
An analog front-end circuit system, which includes an adaptive sigma-delta modulator (SDM) with a... more An analog front-end circuit system, which includes an adaptive sigma-delta modulator (SDM) with a wide dynamic range and a low power consumption, is proposed for an electroencephalogram acquisition system. The required loop filter for the SDM is implemented using Gm-C integrators, which can significantly reduce power consumption and facilitate flexible coefficient adjustment. The performance of the detection system is also improved by employing an adaptive structure and a dynamic range extension algorithm. The system includes a chopper, an SDM, a digital filter with a chopper, and a calibration unit. Circuit simulation reveals that the dynamic range can be extended by more than 40 dB, and accurate results are achieved by the proposed brain signal acquisition system.
International Symposium on Bioelectronics and Bioinformations 2011, 2011
ABSTRACT This paper presents a low-power RF-transmitter for intelligent healthcare systems. With ... more ABSTRACT This paper presents a low-power RF-transmitter for intelligent healthcare systems. With attention to power-efficient communication in the local sensor network, the required low-power integrated circuits (ICs) are developed for a healthcare system with miniaturization and system integration. A quadrature CMOS voltage-controlled oscillator and a direct-conversion transmitter with PA and up-conversion mixer have been implemented to fit the specification of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the transmitter have been applied in the TSMC 0.18-μm CMOS standard process. The measurement results reveal that the transmitter IC can fit in with the link budget of the UHF ZigBee system for healthcare applications.
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.
ABSTRACT The modified switched-capacitor biquad circuits for low-Q and high-Q structures are pres... more ABSTRACT The modified switched-capacitor biquad circuits for low-Q and high-Q structures are presented in This work. By using the switched-opamp technique, the structures make only one active opamp in each phase without destroying their biquad functions. This idea can be applied on the implementation of high-order SC filters to save more power consumption. Meanwhile, the z-domain transfer functions for SC biquad circuits are analyzed to verify the modified structures. Finally, three types of low-Q SC biquad filters are presented as design examples. The simulation results show that the frequency responses of the general active-RC biquad circuits and the modified SC ones are much similar.
2010 IEEE Asia Pacific Conference on Circuits and Systems, 2010
ABSTRACT Inductive coupling is commonly used for wireless power and data transfer in biomedical t... more ABSTRACT Inductive coupling is commonly used for wireless power and data transfer in biomedical telemetry systems. The capability of telemetry module to communicate with the inside of the body makes it possible to transmit the control signal into the implant electronic devices and process the detected inner biophysical signal externally by back-telemetry. On the other hand, the telemetry module inside is capable of converting the radio-frequency (RF) energy delivered through the body tissue into DC as the supply for the implanted device. In this paper, a novel wireless power and data receiver is presented to receive RF signal and generates 1-V DC supply voltage for the sequent device. The overall circuits with core area of 0.07 mm2 have been implemented in a TSMC 0.35μm 2P4M standard CMOS process technology. Measured result shows that the low-power on-chip LDO regulator provides a stable 1-V DC supply voltage and the digital data as well as the 256-kHz clock are obtained precisely.
This paper presents a 10-channel time-of-flight application-specific integrated circuit (ASIC) fo... more This paper presents a 10-channel time-of-flight application-specific integrated circuit (ASIC) for positron emission tomography in a 90 nm standard CMOS process. To overcome variations in channel-to-channel timing resolution caused by mismatch and process variations, adaptive biases and a digital-toanalog converter (DAC) are utilized. The main contributions of this work are as follows. First, multistage architectures reduce the total power consumption, and detection bandwidths of analog preamplifiers and comparators are increased to 1 and 1.5 GHz, respectively, relative to those in previous studies. Second, a total intrinsic electronic timing resolution of 9.71 ps root-mean-square (RMS) is achieved (13.88 ps peak and 11.8 ps average of the 10 channels in 5 ASICs). Third, the proposed architecture reduces variations in channel-to-channel timing resolution to 2.6 bits (equivalent to 4.17 ps RMS) by calibrating analog comparator threshold levels. A 181.5 ps full-width-at-half-maximum timing resolution is measured with an avalanche photo diode and a laser setup. The power consumption is 2.5 mW using 0.5 and 1.2 V power supplies. The proposed ASIC is implemented in a 90 nm TSMC CMOS process with a total area of 3.3 mm × 2.7 mm. Index Terms-Adaptive bias, analog comparator, digital-toanalog converter (DAC), front-end, positron emission tomography (PET), time-of-flight (TOF).
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.
ABSTRACT A speech codec including four main blocks, a class AB switched-current sigma-delta modul... more ABSTRACT A speech codec including four main blocks, a class AB switched-current sigma-delta modulator (SDM), a decimator, an interpolator, and a sigma-delta demodulator (SDDM) is presented. In order to achieve low-power consumption and wide dynamic range, a novel class AB switched-current (SI) integrator is adopted to implement the SDM with over-sampling ratio (OSR) of 64. In addition, design of a reduced-multiplier structure is proposed and applied to the finite impulse response (FIR) filters of the decimator and the interpolator which both of them share the most of hardware in the implementation. Therefore, the number of multipliers and the chip area are reduced. The speech codec was implemented using the TSMC 0.35μm 2P4M standard CMOS process technology. Simulation results with an input of 1kHz sinusoidal wave in the 4 kHz bandwidth show that the speech codec has a maximum signal-to-noise and distortion ratio (SNDR) of 46dB and dynamic range over 65dB with a single 2.5V supply voltage.
2009 IEEE International Symposium on Circuits and Systems, 2009
In this paper, a 1-V 8-bit 10 kS/s successive approximation (SA) analog-to-digital converter (ADC... more In this paper, a 1-V 8-bit 10 kS/s successive approximation (SA) analog-to-digital converter (ADC) with ultra-low power characteristic is implemented for biosignal acquisition systems. To decrease power consumption, a passive sample-and-hold (SH) circuit and an opamp-free, capacitor-based digital-to-analog converter (DAC) are utilized. The only active circuit, a comparator, is implemented in the sub-threshold region to preserve the required bias current. According to the measured results, the ADC has a signal-to-noise distortion ratio (SNDR) of 45.2 dB, and peak spurious free dynamic range (SFDR) of 54 dB for a 1 kHz 500 mV pp input sine wave. The effective number of bits (ENOB) is 7.2. Its differential nonlinearity (DNL) and integral nonlinearity (INL) are-0.41/+0.38 and-0.89/+0.6 LSB, respectively. The total power consumption is 950 nW, and the figure of merit (FOM) is 3230 fJ/conversion-step. The active area, which is 0.93 x 0.93 mm 2 , is determined by using TSMC 0.18μm 1P6M CMOS process.
IEEE Transactions on Circuits and Systems II: Express Briefs, 2008
Abstract A quadrature voltage-controlled oscillator (QVCO) with a wide tuning range is proposed a... more Abstract A quadrature voltage-controlled oscillator (QVCO) with a wide tuning range is proposed and implemented in the TSMC 0.18-mum CMOS process. The said QVCO uses a cross-coupled structure and a current-reuse technology to produce the quadrature signal ...
IEEE Transactions on Circuits and Systems I: Regular Papers, 2006
Abstract An ultralow-voltage and low-power adaptive sigma-delta analog-to-digital converter (SDAD... more Abstract An ultralow-voltage and low-power adaptive sigma-delta analog-to-digital converter (SDADC) with a 10-bit dynamic range for bio-microsystem applications is presented. The proposed SDADC includes a switched-current sigma-delta modulator (SISDM) and a ...
A system design with new empirical stability criteria for sigma-delta modulators is proposed. The... more A system design with new empirical stability criteria for sigma-delta modulators is proposed. The stability criteria is a cubic function obtained by the least square method, and simulations including coefficients variation due to component mismatches of circuit ...
IEEE Transactions on Biomedical Circuits and Systems, 2021
Epilepsy is a common clinical disease. Severe epilepsy can be life-threatening in certain unexpec... more Epilepsy is a common clinical disease. Severe epilepsy can be life-threatening in certain unexpected conditions, so it is important to detect seizures instantly with a wearable device and to provide treatment within the golden window. The observation of the electroencephalography (EEG) signal is an imperative method to assist correct epilepsy diagnosis. To detect and classify EEG signals, a convolutional neural network (CNN) is an intuitive and appropriate method that borrows expertise from neurologists. However, the computational cost of training and inference on artificial intelligence (AI)-based solutions make software-only and hardware-only solutions incompetent for real-time monitoring on embedded devices. Hence, this study proposes three key contributions for the challenge, namely, an algorithm framework to provide real-time epilepsy detection, a dedicated coprocessor chip implementing this framework to enable real time epilepsy detection to offload and accelerate detection algorithm, and a custom interface with the coprocessor and reduced instruction set computer-V (RISC-V) instructions to reconfigure the coprocessor and transfer data. The epilepsy detection framework is implemented in 11-layer CNN. The proposed epilepsy detection algorithm performs 97.8% accuracy for floating-point and 93.5% for fixed-point operations through animal experiments with lab rats. The RISC-V CNN coprocessor is fabricated in the TSMC 0.18-μm CMOS process. For each classification, the coprocessor consumes 51 nJ/class. and 0.9 µJ/class. energy on data transfer and inference, respectively. The detection latency on the chip is 0.012 s. With the integration of the hardware coprocessor, AI algorithms can be applied to epilepsy detection for real-time monitoring.
IEEE Transactions on Biomedical Circuits and Systems, 2021
This work presents a portable wireless urine detection system which consists of an electrochemica... more This work presents a portable wireless urine detection system which consists of an electrochemical readout application specific integrated circuit (ASIC) and a biosensor composed of 2, 2'-azino-bis(3-ethylbenzothiazoline-6-sulphonic acid) and carbon nanotube (ABTS-CNT) for the detection of urine albumin-to-creatinine ratio (UACR). The ASIC includes a potentiostat, a digital circuitry and a power management circuit which can perform electrochemistry techniques with a dual-channel screen-printing carbon electrode (SPCE). Electrochemical experiments on the proposed biosensor (SPCE|ABTS-CNT|Nafion) have revealed promising sensing characteristics for creatinine and human serum albumin detection. Practical urine tests has demonstrated the capability of the proposed urine detection system for UACR detection with both the power-efficient readout ASIC and the ABTS-CNT biosensor. A user-friendly prototype has also been designed which can be useful for either personal health administrationor homecare.
IEEE Transactions on Biomedical Circuits and Systems, 2020
This paper presents a high energy efficiency, highintegrated, and low-power on-off keying transce... more This paper presents a high energy efficiency, highintegrated, and low-power on-off keying transceiver for a 2.4 GHz industrial scientific medical band. The proposed receiver includes an input matching network, a low-noise amplifier, a novel single-to-differential envelope detector, a level shifter, cascaded baseband amplifiers, and a hysteresis comparator. The proposed transmitter includes a bias-stimulating circuit, a current-reused self-mixing voltage controlled oscillator, and a quadruple-transconductance power amplifier. Numerous proposed techniques implemented in the mentioned circuits improve the energy per bit and power efficiency. Therefore, the proposed receiver for short-distanced propagation can achieve a sensitivity of −46 dBm with a carrier frequency of 2.45 GHz and a high data rate of 2 Mbps. The proposed transmitter achieves an output power of −17 dBm with a high data rate of 20 Mbps. This work is fabricated in a TSMC 0.18 μm CMOS process and consumes 160 W and 0.6 mW in the receiver and transmitter, respectively, from a 1.2 V supply voltage. The energy per bit of 80 pJ/bit in the receiver part and the figure of merit of 9 in the transmitter part are better than those of existing state-of-the-art transceivers.
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019
A 1024-point single-bin discrete Fourier transform (SBDFT)-based digital calibration technique is... more A 1024-point single-bin discrete Fourier transform (SBDFT)-based digital calibration technique is presented for high-performance, full-code successive approximation (SAR) analog-to-digital converters (ADCs). This proposed method can evaluate the radix error in capacitor-DAC (CDAC), which deviates from the designed value. Thus, the corrected digital output codes are generated to compensate the error, thereby reducing the harmonic distortion caused by capacitor mismatch. Moreover, the proposed algorithm adopts a recursive SBDFT computation rather than a conventional fast Fourier transform (FFT) computation methods because the simple hardware, which reduces hardware complexity and power consumption, can be achieved to calculate a certain bin in this work. The effective number of bits (ENOB) and signal-to-noise ratio (SNDR) can be enhanced by approximately 2 bits and 14.52 dB, respectively, on the basis of the simulation result of a 12-bit SAR ADC behavior model with 0.3% capacitor mismatch. The proposed SAR ADC is fabricated in TSMC 0.18 µ m 1P6M technology. Measurement results explain that the SNDR, spurious free dynamic range, and ENOB are 46.49/67.28 dB, 49.66/80.73 dB, and 7.43/10.88 bits before/after calibration, respectively, wherein the power supply is 3.3 V and the input signal frequency is 2 kHz with a sampling rate of 100 kS/s.
2015 International Symposium on Bioelectronics and Bioinformatics (ISBB), 2015
This study proposes an electrocardiographic (ECG) monitoring and emotion stabilization system tha... more This study proposes an electrocardiographic (ECG) monitoring and emotion stabilization system that is composed of an acquisition system on chip and an Android system. This system has three main parts. The first part is a low-power analog front-end circuit for biosignal sensing. The second part comprises a digital signal processor for down sampling, filtering, and QRS detection. The last part is an emotion stabilization feedback control based on an Android-operated physiological information platform. This platform allows physiological information display, data recording, signal processing, and analysis. All circuits are fabricated in a TSMC 0.18 μm standard CMOS process.
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Papers by Shuenn Yuh Lee