Department of Electrical Enginering

A novel adaptive approach for sigma-delta modulators (SDMs) to improve dynamic range significantly is proposed. Based on adapting the signal power gain of SDMs, several dynamic-range curves can be obtained. The cascade of integrators with distributed feedback (CIFB) structure is used to demonstrate the basic idea. A systematic approach with the proposed optimising algorithm is used to acquire the boundary constraints. Therefore, a wider dynamic range can be achieved without changing the original architecture. The simulation results reveal that the proposed method under coefficient spread of 60 000 can improve dynamic ranges by 39 and 20 dB for a fourth-order CIFB structure with an oversampling ratio (OSR) of 32 and 64, respectively. Moreover, a fourth-order SDM with CIFB structure and OSR of 32 under the coefficient spread of 3 455 with less hardware is implemented by switched-capacitor circuits, and a 16 dB dynamic range improvement is revealed to agree with the proposed method.

A low-power, wireless, and implantable microstimulator system on chip with smart powering management, immediate neural signal acquisition, and wireless rechargeable system is proposed. A system controller with parity checking handles the adjustable stimulus parameters for the stimulated objective. In the current paper, the rat's intra-cardiac electrogram is employed as the stimulated model in the animal study, and it is sensed

In this paper, wireless telemetry using the near-field coupling technique with round-wire coils for an implanted car- diac microstimulator is presented. The proposed system possesses an external powering amplifier and an internal bidirectional mi- crostimulator. The energy of the microstimulator is provided by a rectifier that can efficiently charge a rechargeable device. A fully integrated regulator and a charge pump

In this paper, a cross-domain integration system composed of a gene transfer technique with a pre-clinical trial, an on-chip circuit design, an off-chip hardware with peripheral unit integration, and a custom software is presented. Opsin protein-gene transfer is successfully conducted to demonstrate that gene transfer treatment with optical stimulation has several benefits compared with electrical treatment. The proposed wireless programmable stimulating system on chip (WPSSoC) is composed of two sensing channels combined with a decimation filter to acquire intracranial electroencephalography (iEEG), an epilepsy detection unit (EDU), a stimulator with a waveform controller, and an ultra-low-power embedded transceiver. The equivalent sample rate of sensed data is 375 samples/s with 16-bit output data. The performance of intermodulation distortion with a third order (IMD3) is approximately 68 dB. The EDU extracts approximate entropy (ApEn) and spectrum bins for the classifier. The stimulator with controller features on the waveformadjustable function to provide 0-510 μA of electrical stimulation and 0-50 mW of optical stimulation. The proposed transceiver is implemented with a 2.45 GHz on-off keying (OOK) carrier frequency. Transmitter and receiver front-ends perform at 50.6 and 12.7 pJ/bit of energy per bit, respectively. Power consumption and area of WPSSoC are about 1 mW and 13.67 mm 2 in a 0.18 μm process, respectively. Circuits of each part are integrated in a 4.3 cm × 2 cm printed circuit board. The shrunk device is verified with Thy1-ChR2-YFP gene transfer in C57BL/6 mice by using a custom software which is used to provide commands and monitor iEEG. INDEX TERMS ChR2 gene transferring, electrical stimulation, epilepsy, implantable device, in vivo testing, open-/closed-loop control, optical stimulation, system-on-chip, wireless monitoring and control

Inductive coupling is presented with the help of a high-efficiency Class-E power amplifier for an implantable cardiac microstimulator. The external coil inductively transmits power and data with a carrier frequency of 256 kHz into the internal coil of electronic devices inside the body. The detected cardiac signal is fed back to the external device with the same pair of coils to save on space in the telemetry device. To maintain the power reliability of the microstimulator for long-term use, two small rechargeable batteries are employed to supply voltage to the internal circuits. The power management unit, which includes radio frequency front-end circuits with battery charging and detection functions, is used for the supply control. For cardiac stimulation, a high-efficiency charge pump is also proposed in the present paper to generate a stimulated voltage of 3.2 V under a 1 V supply voltage. A phase-locked-loop (PLL)-based phase shift keying demodulator is implemented to efficiently extract the data and clock from an inductive AC signal. The circuits, with an area of 0.45 mm 2 , are implemented in a TSMC 0.35 m 2P4M standard CMOS process. Measurement results reveal that power can be extracted from the inductive coupling and stored in rechargeable batteries, which are controlled by the power management unit, when one of the batteries is drained. Moreover, the data and clock can be precisely recovered from the coil coupling, and a stimulated voltage of 3.2 V can be readily generated by the proposed charge-pump circuits to stimulate cardiac tissues.

This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a lowpower analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successiveapproximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs. Index Terms-Analog filter, analog front-end ICs, analog-todigital converter (ADC), ECG signal acquisition, low noise amplifier (LNA), low-power circuits, power amplifier (PA), power splitter, quadrature mixer, quadrature voltage-controlled oscillator (QVCO).

This paper presents an ultra-low-power fourth-order bandpass operational transconductance amplifier-C (OTA-C) filter for an implantable cardiac microstimulator used to detect the R-wave of intracardiac electrograms. The OTA-C filter fabricated by TSMC 0.35-mm complementary metal-oxide-semiconductor (CMOS) technology is operated in the subthreshold region to save power under a supply voltage of 1 V. The current cancellation technique is adopted to reduce the transconductance of the amplifier. Through this, the low-frequency OTA-C filter can be realized by ultra-low transconductance with on-chip capacitors. Direct comparison to conventional RLC ladders replaced by OTA-C circuits shows that the method of reducing the number of OTAs further diminishes power consumption. Design issues, including ultra-low transconductance, linearity, and noise, are also discussed. Measurement results show that the low-voltage, low-power filter has a bandwidth between 10 and 50 Hz, third inter-modulation distortion of À40 dB, dynamic range of 43 dB, and power consumption of only 12 nW. The real electrocardiography signal is fed into the bandpass filter to verify the function of signal processing with the distribution of the R-wave.

This paper presents a novel topology for the even harmonic mixer (EHM). The proposed mixer employs current reuse and double frequency circuits in the RF input stage and LO stage, respectively, to improve its linearity and isolation. In addition, the proposed topology has the advantage of the low power consumption. In order to demonstrate the benefits of the proposed mixer, theoretical analyses of conversion gain and linearity have been described in details. The measured results reveal that the proposed mixer possesses single-end conversion gain of 8 dB and third-order input intercept point (IIP 3) of-3.8 dBm, respectively, under the supply voltage of 1.8 V and LO power of 4 dBm. The power consumption of the proposed mixer is about 1.4 mW at 900 MHz.

This paper presents a wireless biosignal acquisition system-on-a-chip (WBSA-SoC) specialized for electrocardiogram (ECG) monitoring. The proposed system consists of three subsystems, namely, 1) the ECG acquisition node, 2) the protocol for standard IEEE 802.15.4 ZigBee system, and 3) the RF transmitter circuits. The ZigBee protocol is adopted for wireless communication to achieve high integration, applicability, and portability. A fully integrated CMOS RF front end containing a quadrature voltage-controlled oscillator and a 2.4-GHz low-IF (i.e., zero-IF) transmitter is employed to transmit ECG signals through wireless communication. The low-power WBSA-SoC is implemented by the TSMC 0.18-μm standard CMOS process. An ARM-based displayer with FPGA demodulation and an RF receiver with analog-to-digital mixed-mode circuits are constructed as verification platform to demonstrate the wireless ECG acquisition system. Measurement results on the human body show that the proposed SoC can effec...

A low-power, low-intermediate frequency (IF) radio frequency (RF) front-end, including low-noise amplifier (LNA) and mixer for the medical implant communications service (MICS) RF band, is presented. The frequencies of LNA and mixer range from 402 MHz to 405 MHz, while the IF of the mixer is 450 KHz. Current-reuse, back-gate coupling, current-bleeding, and feedback circuit design techniques are utilized in the LNA design to achieve 10 dB of gain and the required noise figure (NF) under the low power consumption of 0.94 mW. By contrast, the Gilbert-type mixer generates 20 dB of conversion gain by using current-reuse, back-gate coupling, and current-bleeding techniques. The front-end is operated using a 1.8 V power supply and is capable of achieving a 97 dBm sensitivity using quadrature phase shift keying modulation while consuming 1.3 mW. The proposed front-end is implemented in TSMC 0.18 CMOS process with a total area of 1.4 mm 1.2 mm. The gain enhancement technique has been substantially optimized compared with previous works and measurement results indicate that the front-end obtains the highest figure of merit compared with previous works.

An equation-based behavioral model has been developed to predict the real performance of a single–loop single-bit Sigma Delta Modulator (SDM). By using this prediction flow, not only can the circuit specifications be acquired, including the gain, bandwidth, slew rate of the OPAMPs, and the capacitor value in the switched-capacitor circuits, but the real performance of the SDM can also be predicted. The switched-capacitor circuits according to the required circuit specifications are employed to design a fourth-order feed-forward (FF) SDM with an over-sampling ratio (OSR) of 64 and a bandwidth of 10kHz using a TSMC 0.35µm CMOS process. The measurement results reveal that the SDM with an input frequency of 2.5kHz and a supply voltage of 3.3V can achieve a dynamic range of 90dB and a spurious-free dynamic range (SFDR) of 85dB under the signal bandwidth of 10kHz and a sampling frequency of 1.28MHz, respectively. The precision of the equation-based behavioral model has been validated by e...

This study presents a self-testing platform with a foreground digital calibration technique for successive approximation register (SAR) analog-to-digital converters (ADCs). A high-accuracy digital-to-analog converter (DAC) with digital control is used for the proposed self-testing platform to generate the sinusoidal test signal. This signal is then implemented using an Arduino board, and the clock signal is generated to test the ADCs. In addition, fast Fourier transform and recursive discrete Fourier transform (RDFT) processors are adopted for dynamic performance evaluation and calibration of the ADCs. The third harmonic distortion caused by the non-linearity of the track-and-hold circuit, the mismatch of the DAC capacitor array, and the direct current (DC) offset of the comparator can be calculated using the processors to improve the ADC performance. The advantages of the proposed platform include its low cost, high integration, and no need for an extra analogy compensation circuit to deal with calibration. In this work a 12 bit SAR ADC and an RDFT processor are used in the Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) 0.18 µm standard complementary metal-oxide-semiconductor (CMOS) process with a sampling rate of 18.75 kS/s to validate the proposed method. The measurement results show that the signal-to-noise and distortion ratio is 55.07 dB before calibration and 61.35 dB after calibration.

The current paper presents an outdoor monitoring system for elderly people, which can transmit information on physiological signals and falling events to a healthcare center at any time and from any place. To detect simultaneously the occurrence of any falling event, as well as the relative electrocardiogram (ECG) signal of the user, a multi-thread method is proposed with the objective of enhancing the response time and the accuracy of detection. A healthcare box is used to determine the relative position of the patient through a global positioning system for fall detection; moreover, an ECG signal acquisition thread is adopted to increase the precision of the fall detection system. Integrating a precise map into the monitoring system facilitates understanding of a client user of the correct location and surrounding environment using the portable display. According to experimental results based on 4,000 samples, successful detection time with the multi-thread method was reduced by 38%, thereby increasing rescue opportunities for elderly patients who are at risk 1 .

This special issue of the Journal of Medical and Biological Engineering highlights the field of advanced bioelectronics and bioinformatics. Several papers were considered for this special issue, including those on bioelectronics in wearable and implantable medical devices, such as sensors, and bioinformatics in healthcare, brain cognition, and various neural pathologies. Many investigators contributed original research articles to this issue, demonstrating emerging research fields. More than 20 papers were accepted for publication after a high-quality critical review was conducted, and 14 papers were selected for this special issue. This special issue on bioelectronics and bioinformatics attracted a substantial number of fullpaper submissions from many countries. We appreciate the numerous volunteers who helped review the manuscripts. This paper provides a brief review of issues regarding bioelectronics and bioinformatics devices.

This paper is devoted to developing a biomedical engineering application, an IOT-based system which can instantly detect drivers' fatigue level and their physiological condition. Drivers' fatigue level can be estimated by monitoring their real-time biodata, such as Electrocardiography (ECG), Photoplethysmogram (PPG), blood pressure and blood oxygen saturation. Furthermore, with cloud database, this monitoring system will be fully constructed, Internet of Things (IOT) connects drivers with monitoring platform, and finally it achieves the purpose of improving public transport safety.

A voltage-controlled oscillator (VCO) with low phase noise and low power dissipation for IEEE 802.11b is proposed. A negative resistance multiple-gated circuit with a bypass capacitor is adopted to improve phase noise. The chip is implemented in 0.18-m CMOS process under a supply voltage of 0.9 V and power consumption of 2.7 mW. Its measured results show that the VCO has a phase noise of 122.3 dBc/Hz at 1-MHz offset frequency from the carrier frequency, and the tuning frequency from 2.17 to 2.73 GHz can be obtained under the tuning voltage of 0.9 to 0.9 V. The theoretical analysis and design consideration are also conducted in detail to show the benefits of the proposed VCO.

This paper presents a 5.25-GHz folded-cascode evenharmonic mixer (FEHM) for low-voltage applications. This FEHM employs the folded technique to reduce the headroom voltage, a current reuse circuit in the RF stage to improve its linearity, and the frequency-doubling technique in the local oscillator (LO) stage to produce an LO double-frequency signal. In addition, the proposed technique exhibits the advantage of high conversion gain. In order to demonstrate the benefits and optimize the circuit design, the theoretical studies of conversion gain, linearity, and noise performance are described. For measurement, the proposed FEHM possesses conversion gain of 8.3 dB, third-order input intercept point (IIP 3) of 0.03 dBm, and second-order input intercept point (IIP 2) of 31.2 dBm under the supply voltage of 0.9 V and LO power of 5.5 dBm. The power consumption of the proposed mixer is about 4.95 mW at an IF frequency of 500 kHz.

A novel adaptive approach for sigma-delta modulators (SDMs) to improve dynamic range significantly is proposed. Based on adapting the signal power gain of SDMs, several dynamic-range curves can be obtained. The cascade of integrators with distributed feedback (CIFB) structure is used to demonstrate the basic idea. A systematic approach with the proposed optimising algorithm is used to acquire the boundary constraints. Therefore, a wider dynamic range can be achieved without changing the original architecture. The simulation results reveal that the proposed method under coefficient spread of 60 000 can improve dynamic ranges by 39 and 20 dB for a fourth-order CIFB structure with an oversampling ratio (OSR) of 32 and 64, respectively. Moreover, a fourth-order SDM with CIFB structure and OSR of 32 under the coefficient spread of 3 455 with less hardware is implemented by switched-capacitor circuits, and a 16 dB dynamic range improvement is revealed to agree with the proposed method.

A fast Fourier transform (FFT)-based digital calibration method for 1.5 bit/stage pipeline analog-to-digital converter (ADC) is proposed in this paper. Capacitor mismatch and finite gain of the operational amplifier (OPAMP) can be overcome by the proposed calibration method. Given that the capacitor mismatch and the finite OPAMP gain cause the radix of all the stages of 1.5 bit/stage pipeline ADC to become unequal to 2, the FFT processor can be adopted to evaluate the actual radixes of all the stages and then generate new digital output to compensate for error caused by these non-ideal effects. Moreover, as capacitor mismatch and the finite gain of OPAMP can be compensated, low-gain OPAMP can be used in high-performance ADC to reduce power dissipation; a small capacitor can then be adopted to save on space. An example of a 10 bit 1.5 bit/stage pipelined ADC with only an 8 bit circuit performance is implemented in 0.18 μm TSMC CMOS process. Circuit measurement result reveals that the signal-to-noise-and-distortion ratio of 51.03 dB with 11 dB improvement after calibration can be achieved at the sample rate of 1 MHz. Copyright