NOTICE WARNING CONCERNING COPYRIGHT RESTRICTIONS: The copyright law of the United States (title 1... more NOTICE WARNING CONCERNING COPYRIGHT RESTRICTIONS: The copyright law of the United States (title 17, U.S. Code) governs the making of photocopies or other reproductions of copyrighted material. Any copying of this document without permission of its author may be prohibited by law.
The design of a 64-word by 64-bit dynamic RAM is described. The RAM cell is implemented as a four... more The design of a 64-word by 64-bit dynamic RAM is described. The RAM cell is implemented as a four-transistor dynamic cell. Sense amplifiers are used to reduce access time. Bootstrapped logic reduces power dissipation. Experimental results indicate a typical cycle time of 160ns and power dissipation of 160mW. /
The quiescent current testing (IDDQ testing) for CMOS ICs provides several advantages over other ... more The quiescent current testing (IDDQ testing) for CMOS ICs provides several advantages over other testing methods. However, the future of IDDQ testing is threatened by increased sub-threshold leakage current for new technologies. The conventional pass/fail limit setting methodology cannot survive in its present form. In this paper we evaluate two statistical outlier rejection methods – the Chauvenet’s criterion and the Tukey test – for their applicability to IDDQ testing. They are compared with the static-threshold method. The results of the analysis of application of these methods to the SEMATECH data are presented.
This work presents a methodology to identify integrated circuit yield detractors using SRAM funct... more This work presents a methodology to identify integrated circuit yield detractors using SRAM functional test results in combination with a defect-bitmap dictionary. We investigate the accuracy of the defect classification under different forms of voltage testing and current testing. In particular we investigate the benefit of using multiple Iddq current levels calibrated to remove normal parametric variations. We also investigate the effects of unmodeled defects and the ability to identify cases off certain and uncertain diagnosis. We have experimentally validated our approach using a production microprocessor cache
Increasing values and spread in leakage current makes it impossible to distinguish between faulty... more Increasing values and spread in leakage current makes it impossible to distinguish between faulty and fault-free chips using single threshold method. Neighboring chips on a wafer have similar fault-free properties. By obtaining differences in I DDQ values it is possible to discriminate faulty dice. In this paper, a technique in which comparison of I DDQ of a die with that of its neighboring dice on the wafer is evaluated. The analysis based on the SEMATECH test data § is presented.
... by Sagar Suresh Sabade , Duncan Walker , Vivek Sarin , Donald ... MISC{Sabade04bymultiple, au... more ... by Sagar Suresh Sabade , Duncan Walker , Vivek Sarin , Donald ... MISC{Sabade04bymultiple, author = {Sagar Suresh Sabade and Duncan Walker and Vivek Sarin and Donald Friesen and Henry Taylor}, title = {BY MULTIPLE PARAMETER CORRELATION}, year = {2004} }. ...
The design of a 64-word by 64-bit dynamic RAM is described. The RAM cell is implemented as a four... more The design of a 64-word by 64-bit dynamic RAM is described. The RAM cell is implemented as a four-transistor dynamic cell. Sense amplifiers are used to reduce access time. Bootstrapped logic reduces power dissipation. Experimental results indicate a typical cycle time of ...
ABSTRACT This paper describes the DEfect to FAult Mapper (DEFAM), and its use in integrated circu... more ABSTRACT This paper describes the DEfect to FAult Mapper (DEFAM), and its use in integrated circuit test quality analysis and yield prediction. DEFAM analyzes the effects of spot defects on a design during the manufacturing process, and computes the probability of circuit faults that may occur. Unlike traditional tools, DEFAM exploits the design hierarchy to reduce the required analysis effort. It also reports faults in terms of the design hierarchy, which is essential for many applications. Yield analysis results are given for CMOS designs of up to 164K transistors. Test quality analysis results are given for an adder module.
This paper describes the PREDITOR process editor and slatisiical simulator. PREDITOR provides int... more This paper describes the PREDITOR process editor and slatisiical simulator. PREDITOR provides interactive process editing and statistical process/device simulation. PREDITOR is implemented using the Chip Database (CDB), a 3-D geometry and field database for representing the results of IC process and device simulation. A process step abstraction pwnnits the details of database access and the simulation model to be hidden from the process flow m;mipulation tools. This makes it possible to add external simulators such as SAMPLE and SUPREM-IV to the list of possible process and device simulation models, with only local changes to the PREDITOR code. Using fast analytical models, process simulation and device parameter extraction for a CMOS inverter takes 1.3sec on a DECstation 3100.
Proceedings of the 1998 Acm Sigda Sixth International Symposium on Field Programmable Gate Arrays, 1998
ABSTRACT This paper presents a vector generation approach for testing interconnects in configurab... more ABSTRACT This paper presents a vector generation approach for testing interconnects in configurable (SRAM-based) Field Programmable Gate Arrays (FPGAs). The proposed approach detects bridging faults and is based on quiescent current (IDDQ monitoring. Compared with previous voltage-based methods, IDDQ testing has the advantage of utilizing a small number of programming phases for configuring the FPGA during the test process with negligible observability requirements, even under multiple faults. Algorithms for test generation which exploit the homogeneous nature of the FPGA array, are described. An example using the XC4000 is described in detail. For testing the XC4000 series interconnect, a total of 20 phases and 11 vectors are required: 11 phases for S (switch) block testing, and 9 phases for C (connection) block testing.
Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159), 2000
Defect diagnosis in random logic is currently done using the stuck-at fault model, while most def... more Defect diagnosis in random logic is currently done using the stuck-at fault model, while most defects seen in manufacturing result in bridging faults. In this work we use physical design and test failure information combined with bridging and stuck-at fault models to localize defects in random logic. We term this approach computer-aided fault to defect mapping (CAFDM). We build on top of the existing mature stuck-at diagnosis infrastructure. The performance of the CAFDM software was tested by injecting bridging faults into samples of a streaming audio controller chip and comparing the predicted defect locations and layers with the actual values. The correct defect location and layer was predicted in all 9 samples for which scan-based diagnosis could be performed. The experiment was repeated on production samples that failed scan test, with promising results.
IEEE International Conference on Test, 2005., 2005
A practical built-in current sensor (BICS) is described that senses the voltage drop on supply li... more A practical built-in current sensor (BICS) is described that senses the voltage drop on supply lines caused by quiescent current leakage. This non-invasive procedure avoids any performance degradation. The sensor performs analog-to-digital conversion of the input signal using a stochastic process, with scan chain readout. Self-calibration and digital chopping are used to minimize offset and low frequency noise and drift. The measurement results of a 350 nm test chip are described. The sensor achieves a resolution of 182 µA, with the promise of much higher resolution.
Proceedings of 1993 International Conference on Computer Aided Design (ICCAD), 1993
This paper describes the DEFAM defect to fault mapper, and its use in test quality analysis and y... more This paper describes the DEFAM defect to fault mapper, and its use in test quality analysis and yield prediction. DEFAM analyzes the effects of spot defects in the manufacturing process on a design, and computes the probability of circuit faults that may occur. Unlike traditional tools, DEFAM exploits the design hierarchy to reduce the simulation effort needed. It also reports
22nd IEEE VLSI Test Symposium, 2004. Proceedings., 2004
The path delay fault model is the most realistic model for delay faults. Testing all the paths in... more The path delay fault model is the most realistic model for delay faults. Testing all the paths in a circuit achieves 100% delay fault coverage according to traditional path delay fault coverage metrics. These metrics result in unrealistically low fault coverage if only a subset of paths is tested, and the real test quality is not reflected. For example, the traditional path delay fault coverage of any practical test for circuit c6288 is close to 0 because this circuit has an exponential number of paths. In this paper, a statistical and realistic path delay fault coverage metric is presented. Then the quality of several existing test sets (path selection methods) is evaluated in terms of local and global delay faults using this metric, in comparison with the transition fault and traditional path delay fault coverage metrics.
IEEE International Conference on Test, 2005., 2005
Excessive power supply noise can lead to overkill during delay test. A static compaction solution... more Excessive power supply noise can lead to overkill during delay test. A static compaction solution is described to prevent such overkill. Low-cost power supply noise models are developed and used in compaction. An error analysis of these models is given. This paper improves on prior work in terms of models and algorithm to increase accuracy and performance. Experimental results are given on ISCAS89 circuits.
Excessive power supply noise can lead to overkill during delay test. A static compaction algorith... more Excessive power supply noise can lead to overkill during delay test. A static compaction algorithm is described in this paper that prevents such overkill. A power supply noise estimation tool has been built and integrated into the compaction process. Compaction results for KLPG delay tests for ISCAS89 circuits under different power grid environments are presented.
Proceedings. 16th IEEE Symposium on Computer Arithmetic, 2003
Delay faults are an increasingly important test challenge. Traditional delay fault models are inc... more Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they only model a subset of delay defect behaviors. To solve this problem a combined delay fault (CDF) model has been developed, which models delay faults caused by the combination of spot defects, parametric process variation, and capacitive coupling. The spot defects are modeled as both resistive opens and shorts. The CDF model has been implemented in the CodSim delay fault simulator which gives more realistic delay fault coverage. The fault coverage of traditional test sets has been evaluated on the ISCAS85 circuits.
ABSTRACT Dynamic compaction is an effective way to reduce the number of test patterns while maint... more ABSTRACT Dynamic compaction is an effective way to reduce the number of test patterns while maintaining high fault coverage. This paper proposes a new dynamic compaction algorithm for generating compacted test sets for K longest paths per gate (KLPG) in combinational circuits or scan-based sequential circuits. This algorithm uses a greedy approach to compact paths with non-conflicting assignments together during test generation. Experimental results for ISCAS89 benchmark circuits and two industry circuits show that the pattern count of KLPG can be significantly reduced (up to 3x compared to static compaction) using the proposed method. The pattern count after dynamic compaction is comparable to the number of transition fault tests, while achieving higher test quality.
NOTICE WARNING CONCERNING COPYRIGHT RESTRICTIONS: The copyright law of the United States (title 1... more NOTICE WARNING CONCERNING COPYRIGHT RESTRICTIONS: The copyright law of the United States (title 17, U.S. Code) governs the making of photocopies or other reproductions of copyrighted material. Any copying of this document without permission of its author may be prohibited by law.
The design of a 64-word by 64-bit dynamic RAM is described. The RAM cell is implemented as a four... more The design of a 64-word by 64-bit dynamic RAM is described. The RAM cell is implemented as a four-transistor dynamic cell. Sense amplifiers are used to reduce access time. Bootstrapped logic reduces power dissipation. Experimental results indicate a typical cycle time of 160ns and power dissipation of 160mW. /
The quiescent current testing (IDDQ testing) for CMOS ICs provides several advantages over other ... more The quiescent current testing (IDDQ testing) for CMOS ICs provides several advantages over other testing methods. However, the future of IDDQ testing is threatened by increased sub-threshold leakage current for new technologies. The conventional pass/fail limit setting methodology cannot survive in its present form. In this paper we evaluate two statistical outlier rejection methods – the Chauvenet’s criterion and the Tukey test – for their applicability to IDDQ testing. They are compared with the static-threshold method. The results of the analysis of application of these methods to the SEMATECH data are presented.
This work presents a methodology to identify integrated circuit yield detractors using SRAM funct... more This work presents a methodology to identify integrated circuit yield detractors using SRAM functional test results in combination with a defect-bitmap dictionary. We investigate the accuracy of the defect classification under different forms of voltage testing and current testing. In particular we investigate the benefit of using multiple Iddq current levels calibrated to remove normal parametric variations. We also investigate the effects of unmodeled defects and the ability to identify cases off certain and uncertain diagnosis. We have experimentally validated our approach using a production microprocessor cache
Increasing values and spread in leakage current makes it impossible to distinguish between faulty... more Increasing values and spread in leakage current makes it impossible to distinguish between faulty and fault-free chips using single threshold method. Neighboring chips on a wafer have similar fault-free properties. By obtaining differences in I DDQ values it is possible to discriminate faulty dice. In this paper, a technique in which comparison of I DDQ of a die with that of its neighboring dice on the wafer is evaluated. The analysis based on the SEMATECH test data § is presented.
... by Sagar Suresh Sabade , Duncan Walker , Vivek Sarin , Donald ... MISC{Sabade04bymultiple, au... more ... by Sagar Suresh Sabade , Duncan Walker , Vivek Sarin , Donald ... MISC{Sabade04bymultiple, author = {Sagar Suresh Sabade and Duncan Walker and Vivek Sarin and Donald Friesen and Henry Taylor}, title = {BY MULTIPLE PARAMETER CORRELATION}, year = {2004} }. ...
The design of a 64-word by 64-bit dynamic RAM is described. The RAM cell is implemented as a four... more The design of a 64-word by 64-bit dynamic RAM is described. The RAM cell is implemented as a four-transistor dynamic cell. Sense amplifiers are used to reduce access time. Bootstrapped logic reduces power dissipation. Experimental results indicate a typical cycle time of ...
ABSTRACT This paper describes the DEfect to FAult Mapper (DEFAM), and its use in integrated circu... more ABSTRACT This paper describes the DEfect to FAult Mapper (DEFAM), and its use in integrated circuit test quality analysis and yield prediction. DEFAM analyzes the effects of spot defects on a design during the manufacturing process, and computes the probability of circuit faults that may occur. Unlike traditional tools, DEFAM exploits the design hierarchy to reduce the required analysis effort. It also reports faults in terms of the design hierarchy, which is essential for many applications. Yield analysis results are given for CMOS designs of up to 164K transistors. Test quality analysis results are given for an adder module.
This paper describes the PREDITOR process editor and slatisiical simulator. PREDITOR provides int... more This paper describes the PREDITOR process editor and slatisiical simulator. PREDITOR provides interactive process editing and statistical process/device simulation. PREDITOR is implemented using the Chip Database (CDB), a 3-D geometry and field database for representing the results of IC process and device simulation. A process step abstraction pwnnits the details of database access and the simulation model to be hidden from the process flow m;mipulation tools. This makes it possible to add external simulators such as SAMPLE and SUPREM-IV to the list of possible process and device simulation models, with only local changes to the PREDITOR code. Using fast analytical models, process simulation and device parameter extraction for a CMOS inverter takes 1.3sec on a DECstation 3100.
Proceedings of the 1998 Acm Sigda Sixth International Symposium on Field Programmable Gate Arrays, 1998
ABSTRACT This paper presents a vector generation approach for testing interconnects in configurab... more ABSTRACT This paper presents a vector generation approach for testing interconnects in configurable (SRAM-based) Field Programmable Gate Arrays (FPGAs). The proposed approach detects bridging faults and is based on quiescent current (IDDQ monitoring. Compared with previous voltage-based methods, IDDQ testing has the advantage of utilizing a small number of programming phases for configuring the FPGA during the test process with negligible observability requirements, even under multiple faults. Algorithms for test generation which exploit the homogeneous nature of the FPGA array, are described. An example using the XC4000 is described in detail. For testing the XC4000 series interconnect, a total of 20 phases and 11 vectors are required: 11 phases for S (switch) block testing, and 9 phases for C (connection) block testing.
Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159), 2000
Defect diagnosis in random logic is currently done using the stuck-at fault model, while most def... more Defect diagnosis in random logic is currently done using the stuck-at fault model, while most defects seen in manufacturing result in bridging faults. In this work we use physical design and test failure information combined with bridging and stuck-at fault models to localize defects in random logic. We term this approach computer-aided fault to defect mapping (CAFDM). We build on top of the existing mature stuck-at diagnosis infrastructure. The performance of the CAFDM software was tested by injecting bridging faults into samples of a streaming audio controller chip and comparing the predicted defect locations and layers with the actual values. The correct defect location and layer was predicted in all 9 samples for which scan-based diagnosis could be performed. The experiment was repeated on production samples that failed scan test, with promising results.
IEEE International Conference on Test, 2005., 2005
A practical built-in current sensor (BICS) is described that senses the voltage drop on supply li... more A practical built-in current sensor (BICS) is described that senses the voltage drop on supply lines caused by quiescent current leakage. This non-invasive procedure avoids any performance degradation. The sensor performs analog-to-digital conversion of the input signal using a stochastic process, with scan chain readout. Self-calibration and digital chopping are used to minimize offset and low frequency noise and drift. The measurement results of a 350 nm test chip are described. The sensor achieves a resolution of 182 µA, with the promise of much higher resolution.
Proceedings of 1993 International Conference on Computer Aided Design (ICCAD), 1993
This paper describes the DEFAM defect to fault mapper, and its use in test quality analysis and y... more This paper describes the DEFAM defect to fault mapper, and its use in test quality analysis and yield prediction. DEFAM analyzes the effects of spot defects in the manufacturing process on a design, and computes the probability of circuit faults that may occur. Unlike traditional tools, DEFAM exploits the design hierarchy to reduce the simulation effort needed. It also reports
22nd IEEE VLSI Test Symposium, 2004. Proceedings., 2004
The path delay fault model is the most realistic model for delay faults. Testing all the paths in... more The path delay fault model is the most realistic model for delay faults. Testing all the paths in a circuit achieves 100% delay fault coverage according to traditional path delay fault coverage metrics. These metrics result in unrealistically low fault coverage if only a subset of paths is tested, and the real test quality is not reflected. For example, the traditional path delay fault coverage of any practical test for circuit c6288 is close to 0 because this circuit has an exponential number of paths. In this paper, a statistical and realistic path delay fault coverage metric is presented. Then the quality of several existing test sets (path selection methods) is evaluated in terms of local and global delay faults using this metric, in comparison with the transition fault and traditional path delay fault coverage metrics.
IEEE International Conference on Test, 2005., 2005
Excessive power supply noise can lead to overkill during delay test. A static compaction solution... more Excessive power supply noise can lead to overkill during delay test. A static compaction solution is described to prevent such overkill. Low-cost power supply noise models are developed and used in compaction. An error analysis of these models is given. This paper improves on prior work in terms of models and algorithm to increase accuracy and performance. Experimental results are given on ISCAS89 circuits.
Excessive power supply noise can lead to overkill during delay test. A static compaction algorith... more Excessive power supply noise can lead to overkill during delay test. A static compaction algorithm is described in this paper that prevents such overkill. A power supply noise estimation tool has been built and integrated into the compaction process. Compaction results for KLPG delay tests for ISCAS89 circuits under different power grid environments are presented.
Proceedings. 16th IEEE Symposium on Computer Arithmetic, 2003
Delay faults are an increasingly important test challenge. Traditional delay fault models are inc... more Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they only model a subset of delay defect behaviors. To solve this problem a combined delay fault (CDF) model has been developed, which models delay faults caused by the combination of spot defects, parametric process variation, and capacitive coupling. The spot defects are modeled as both resistive opens and shorts. The CDF model has been implemented in the CodSim delay fault simulator which gives more realistic delay fault coverage. The fault coverage of traditional test sets has been evaluated on the ISCAS85 circuits.
ABSTRACT Dynamic compaction is an effective way to reduce the number of test patterns while maint... more ABSTRACT Dynamic compaction is an effective way to reduce the number of test patterns while maintaining high fault coverage. This paper proposes a new dynamic compaction algorithm for generating compacted test sets for K longest paths per gate (KLPG) in combinational circuits or scan-based sequential circuits. This algorithm uses a greedy approach to compact paths with non-conflicting assignments together during test generation. Experimental results for ISCAS89 benchmark circuits and two industry circuits show that the pattern count of KLPG can be significantly reduced (up to 3x compared to static compaction) using the proposed method. The pattern count after dynamic compaction is comparable to the number of transition fault tests, while achieving higher test quality.
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Papers by Hank Walker