About Me

Hi there! My name is Yiqiu (Susan) Sun. I'm a Computer Science PhD student at University of Illinois, Urbana-Champaign. My research focus is Processing-In-Memory(PIM) Architectures, Programming Models for Novel Architectures and Hardware-Software Co-design. I am fortunate to be advised by Prof. Saugata Ghose.

Previously, I received B.S.E degree in Computer Engineering from University of Michigan, where I worked with Prof. John P. Hayes and Prof. Trevor Mudge. I also received Bachelor of Engineering degree in Electrical and Computer Engineering from Shanghai Jiao Tong University (UM-SJTU Joint Institute).

Office: Room 224, CSL Building, 1308 W Main Street MC 228, Urbana, IL, 61801
Email: [email protected]

Publications

“The Memory Processing Unit: A Generalized Interface for End-to-End In-Memory Execution,” 2026 IEEE International Symposium on High-Performance Computer Architecture (HPCA),
M. S. Q. Truong, Y. Sun, D. Xiong, A. Shah, A. Glass, A. Farrell, J. A. Bain, L. R. Carley and S. Ghose
[link]

“Benefits of Stochastic Computing in Hearing Aid Filterbank Design,” 2021 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2021, pp. 1-5, doi: 10.1109/BioCAS49922.2021.9645021.
T. J. Baker, Y. Sun and J. P. Hayes
[link]

Research Projects

Programming Models for Processing-In-Memory

Explore the implementation of data-parallel programming models on RACER, a cost-effective Processing-Using-Memory architecture.
Under submission for CAL'26 and MICRO'26.

Support End-to-End Execution for Processing-Using-Memory

Proposed the memory processing unit (MPU), a microarchitecture-agnostic interface layer for general-purpose PUM with three components: ISA, ensemble execution model and control path.

Scheduling Algorithms and Optimizations for Lowering Python Package APIs to AI Engine Array

Schedule high-level NumPy logic onto AI engines, establish specialized performance modeling for AI engines and design a more exhaustive FFT design space than polyhedral model.
Picture credit to Xilinx.

Analyzing the Impact of Processing-in-Memory Devices on Scene Reconstruction

Evaluate two different depth fusion algorithms executing on a conventional CPU + memory system and a Hybrid Memory Cube with standard CPU cores. Design a custom hardware accelerator for depth fusion that can be built into the logic layer of a 3D-stacked memory.

Misc

1. I love climbing, running and cooking!
2. My favourite color is green.