36 t2 100 5392 ENTRY t2 100 5392 ACQUIRE t2 100 5393 RELEASE t1 100 5393 ACQUIRE t2 100 5393 ENTRY t2 27 5393 BUSY t1 100 5394 RELEASE t1 100 5394 ENTRY t1 100 5394 ACQUIRE t2 74 5394 RETRY t1 100 5395 RELEASE t1 100 5395 ENTRY t1 100 5395 ACQUIRE t2 83 5395 RETRY t1 100 5396 RELEASE t1 100 5396 ENTRY t1 100 5396 ACQUIRE t2 80 5396 RETRY t1 100 5397 RELEASE t1 100 5397 ENTRY t1 100 5397 ACQUIRE t2 79 5397 RETRY ... A thread switch t2 tries to keep running, but immediately has to block because t1 acquired the GIL signal signal signal signal Here, the GIL battle begins. Every RELEASE of the GIL signals t2. Since there are two cores, the OS schedules t2, but leaves t1 running on the other core. Since t1 is left running, it immediately reacquires the GIL before t2 can get to it (so, t2 wakes up, finds the GIL is in use, and blocks again)