Proceedings of the Sixth International Conference on Computer and Communication Technology 2015
This paper reports a new three levels interconnect signaling system for the On-Chip High Speed Se... more This paper reports a new three levels interconnect signaling system for the On-Chip High Speed SerDes Transceiver used in multi-module System-on-Chip (SoC) communication. This signaling system consists of a three-level encoder, a line driver, interconnect, a line receiver and a three-level detector. It also presents the influences of Process, Voltage and Temperature (PVT) variations on the three levels interconnect signaling system. The proposed signaling system is designed in UMC 180nm CMOS Process Technology and all simulations are done using Cadence Spectre Simulator. Under different process corners, it is observed that the percentage variations on interconnect delay and total average power for three levels interconnect signaling system varies with interconnect line length. Also, with supply voltage variations, the interconnect delay and total average power decreases and increases respectively with increasing supply voltage. Finally, in the case of Temperature variations, it is observed that the interconnect delay and total average power increases and decreases with increase in temperature respectively. This design and results will provide some ideas to the designer about the worst case values and the level of margins to provide at the system design level.
Generalized frequency division multiplexing (GFDM) is non orthogonal multicarrier modulation sche... more Generalized frequency division multiplexing (GFDM) is non orthogonal multicarrier modulation scheme which is suitable for the fifth generation (5G) of wireless network. Pulse shaping filter design in GFDM system have effects on symbol error rate performance due to inter symbol interference (ISI). In this paper Contribute to symbol error rate (SER) performance in GFDM system with additive white Gaussian noise channel (AWGN), zero forcing channel (ZF) rayleigh fading has been analyzed for pulse shaping filter namely raised cosine (RC) and root raised cosine filter (RRC) and also Simulation is done and results are reported in terms of symbol error rate (SER), signal to noise ratio (SNR), different value of roll off factor and different modulation technique. Comparison of simulation results of this method with existing methods is done and improvements in result are obtained as compared to existing.
this paper presents implementation of switch capacitor filter with sample and hold circuit, nonov... more this paper presents implementation of switch capacitor filter with sample and hold circuit, nonoverlapping clock and a gain stage using 180 nm CMOS technology. After implementation, an integration of a Sampler circuit is done with help of Implemented basic blocks with sampling frequency of 2.0 GHz. Finally complete design of band pass filter having a band width of ≤13 Hz is designed which is used for EEG signals application. This band pass filter is a combination of lower cut off frequency 0.7123 Hz and higher cut off frequency of 12.895 Hz which is ideal in detecting EEG Signals (Theta, Alpha, Beta and Delta EEG wave forms). Op-amp used in these circuits having a gain of 47.779 db.
This paper reports design of a ring oscillator using CS-COMS low noise logic family for mixed sig... more This paper reports design of a ring oscillator using CS-COMS low noise logic family for mixed signal SOCs. Design has been implemented using 180nm technology with 1.8V supply voltage using CSCMOS logic. CS-CMOS logic efficiently reduce switching noise while maintaining the speed as compare to the other logics like CSL, CBL etc. After completion of the design authors have simulated the design in Spectre simulator and obtained the best simulation results. Authors have determined the parameters like phase noise, delay.
This paper reports an area-efficient LNA design using an active inductor which can be realised in... more This paper reports an area-efficient LNA design using an active inductor which can be realised in various UHF band receivers. The overall low noise performance of LNA is achieved by cancelling the inductor noise through additional feed forward path. This circuit is implemented using 0.18μm CMOS technology with cadence environment and its operating range is 0.4 to 1GHz. Design is simulated in virtuoso simulator and simulation results are measured. Noise figure is 1.6 to 3.0 dB for the UHF band and power dissipation of overall circuit is 14.03mw at 1.8V supply. KEYWORD: Cadence, MOS based Active Inductor, Feed forward path logic (FFP), Low Noise Amplifier (LNA), Spectre Simulator.
IOP Conference Series: Materials Science and Engineering
Electronics engineers are currently faced with the task of designing linear and broad scale volta... more Electronics engineers are currently faced with the task of designing linear and broad scale voltage regulated oscillator for analogue and a varied signal applications for a shorter design period of time. The Band gap reference source is used here to compensate the noise which affects the Phase lock loop operation from power supplied noise. A cascode current mirror based band gap reference current starved voltage controlled Oscillator (BG-CSVCO) is discussed in detailed as a new design strategy for reducing power supplied noise in Phase lock loop (PLL) applications. A cascode current mirror based band gap reference CS-VCO design is simulated and direct employing in 180nm Cadence CMOS technology. A frequency range of band gap reference CS-VCO is 0.009 GHz up to the 2.07 GHz for adjusting range of 0.5V to 1.8V with the power dissipation is 0.564mW. The VDD as supplied voltage was 1.8volt.
2021 12th International Conference on Computing Communication and Networking Technologies (ICCCNT), 2021
This study describes the design of a novel 13-transistor (13T) Static Random Access Memory (SRAM)... more This study describes the design of a novel 13-transistor (13T) Static Random Access Memory (SRAM) bitcell that employs a single bitline design with isolated transistors used for write and read operation. The bitcell incorporates Schmitt- Trigger based inverters, resulting in a considerable rise in cell's static noise margin. A power gating approach is also used to increase the bitcell's write capabilities, resulting in reduced power consumption during write operations. The proposed bitcell was designed using a 0.18μm technology in Cadence Virtuoso Software. The various performance parameters like stability, Power Consumption, Delay and Leakage power are compared against the conventional 6T SRAM bitcell. Overall, the proposed 13T SRAM bitcell outperforms the conventional 6T SRAM cell in every aspect.
Journal of Telecommunication, Electronic and Computer Engineering, 2019
This paper presents the design of a QVCO (Quadrature voltage controlled oscillator) with high tun... more This paper presents the design of a QVCO (Quadrature voltage controlled oscillator) with high tuning range and low phase noise for Radio Frequency applications. The proposed VCO has been designed to produce quadrature signal by using cross coupled topology. Extra pair of MOSFETS are added to improve the quality factor of the LC tank, which helps to improve the phase noise. The tuning range of VCO ranges from 3.8 GHz to 4.52 GHz, which is nearly 20%. Additionally, the obtained phase noise is -120.31 dBc/Hz at 1MHz offset frequency. The observed power dissipation is 13.21 mW.
In this work, a single-ended 10T static random access memory (SRAM) cell is presented. Proposed c... more In this work, a single-ended 10T static random access memory (SRAM) cell is presented. Proposed cell employs Schmitt-trigger (ST) based inverter to enhance read stability. Single ended feature of the cell saves switching power. Simulation is carried out on 180nm technology using Cadence. Results revealed that our cell provides 1.40x larger read static noise margin (RSNM) compared to conventional 6T cell at 0.7V. During write '0' proposed cell offers 312mV of write static noise margin (WSNM) at 0.7V. During read operation, our cell offers 3.29x lower switching power compared to 6T cell. Standby power dissipation in proposed cellis1.16x of convention 6T cell at 0.7V.
Various improved method for Analog to digital converter (ADC) testing are evaluated. The ADC stat... more Various improved method for Analog to digital converter (ADC) testing are evaluated. The ADC static and dynamic parameters i.e. offset error, gain error, NOB and nonlinearity errors like INL, DNL are obtained from sinewave histogram test. Therefore, the relationships among these parameters are analyzed. With the appropriate approximation in the reference sine wave histogram and the estimation of the ADC parameters, the realization of an ADC output analyzer.
2017 8th International Conference on Computing, Communication and Networking Technologies (ICCCNT), 2017
Biological information processing system, a neuron, is an astonishing piece of design with an ene... more Biological information processing system, a neuron, is an astonishing piece of design with an energy efficiency unmatched to any human-engineered counterpart. This proposed design is an inspired effort to implement a neuron with adaptability. The designed neuron has improved spike-control and thus can be used in advanced neural networks. The proposed controllable-spike Integrate and fire neurons are highly energy efficient. Comparison of different ameliorated silicon neuron designs are described with experimental results. Electronic synthesis of neurons can be utilized for neuromorphic modeling of large-scale neural systems like brain-scanning and sensing technology. The proposed work has been designed using Cadence tool on 180 nm technology node with 1.8 V source.
A single stage source coupled Complementary Metal Oxide Semiconductor Voltage Controlled Oscillat... more A single stage source coupled Complementary Metal Oxide Semiconductor Voltage Controlled Oscillator (CMOS VCO) is designed in this paper. The design is implemented in Cadence environment with high oscillation frequency and low power consumption. This design is a single stage and it has low phase noise because author has reduced noise sources. Oscillation frequency of the designed VCO is ranges from 1.052 GHz to 2.136 GHz. The circuit is simulated using 180nm UMC Technology. Simulation results are reported that the phase noise is -64.96dBc/Hz@1MHz and power consumption is 6.951 mW with 2.136 GHz oscillation frequency and 1.8 V supply voltage. Present results are compared with earlier published work and improvements are observed.
This paper reveals the present status of wireless telemedicine system for m-health application. W... more This paper reveals the present status of wireless telemedicine system for m-health application. Wireless telemedicine network equipped with mobile, computer and telecommunication technologies which provide medical data, information and services from distant locations. Telemedicine opens a world of healthcare delivery by building clinical bridges between patients and available healthcare by integrating Information and Communication Technology, Biomedical Engineering, Medical Science, etc. using minimum costs, effective develop- ment and utilization of ancillary infrastructure and services. We have studied 130 research papers on telemedicine and its aspects, this paper is an extrac- tion which emphasized on wireless technologies like GSM, General Packet Radio Services, EDGE, 3G, 4G, 5G, Cognitive Radio Network, World Wide interoperability of Microwave Access, Wireless Local Area Network, Wireless Body Area Network, Very Small Aperture Terminal, Satellite communication and WPAN (Blueto...
This paper presents a design of low power data channel for application in High Definition Multime... more This paper presents a design of low power data channel for application in High Definition Multimedia Interface (HDMI) Transmitter circuit. The input is 10 bit parallel data and output is serial data at 1.65 Gbps. This circuit uses only a single frequency of serial clock input. All other timing signals are derived within the circuit from the serial clock. This design has dedicated lines to disable and enable all its channels within two pixel-clock periods only. A pair of disable and enable functions performed immediately after power-on of the circuit serves as the reset function. The presented design is immune to data-dependent switching spikes in supply current and pushes them in the range of serial frequency and its multiples. Thus filtering requirements are relaxed. The output stage uses a bias voltage of 2.8 volts for a receiver pull-up voltage of 3.3 volts. The reported data channel is designed using UMC 180 nm CMOS Technology. The design is modifiable for other inter-board seri...
In this work, we present a single-ended Schmitt-trigger (ST) based 12T static random access memor... more In this work, we present a single-ended Schmitt-trigger (ST) based 12T static random access memory (SRAM) cell. The proposed cell employs cross-point data aware write structure, and thus supports bit interleaving architecture to mitigate soft errors. The proposed cell does not suffer from read disturbance as bit line is completely isolated from bit storage node. Simulation is done on 180 nm CMOS technology on Cadence. Read static noise margin (RSNM) of the proposed cell is improved by1.42X as compared to conventional 6T bit cell at Vdd=0.7 V. The proposed cell offers 0.0065X lesser write ‘1’ delay as compared to previously proposed ST based 11T SRAM. Keywords: HSNM, read delay, RSNM, SRAM, write delay, WSNM Cite this Article Mansore SR, Gamad RS, Mishra DK. Schmitt-Trigger Based 12T SRAM Cell with Enhanced Stability . Journal of Semiconductor Devices and Circuits . 2018; 5(1): 5–10p.
International Journal of Advance Research, Ideas and Innovations in Technology, 2018
This paper presents a design of Low power 4 bits Counter at circuit and system level of abstracti... more This paper presents a design of Low power 4 bits Counter at circuit and system level of abstraction using Cadence Virtuoso and Xilinx ISE 14.7 respectively. The laboratory work described includes the CMOS based transistor level design and VHDL based synthesis and implementation of the counter using back end and front end tools respectively. The functionality of the design has been simulated and tested using 0.18µm gdpk CMOS technology with 1.8V supply voltage using cadence virtuoso for back-end designing whereas, Xilinx ISE 14.7 is used for front-end simulation, synthesized using plan¬-ahead and is implemented on ArtixTM-7(family), with device xC7A100TTM. Power calculation has been done at 100 MHz clock frequency for the 1.8V supply voltage.
This paper presents the analysis and design of high speed, high gain fully differential operation... more This paper presents the analysis and design of high speed, high gain fully differential operational amplifier (opamp). Both the main op-amp and the boosting op-amp are fully differential folded-cascode. The main op-amp has a switched capacitor common mode feedback circuit. Two fully differential folded-cascode op amps with continuoustime CMFBs are used as auxiliary op amps to increase the open-loop gain of the main op amp. Common mode feedback (CMFB) is used to stable the designed op-amp against temperature. This design has been implemented in 0.18μm UMC mixed signal CMOS Technology using Cadence. Spectre simulation shows that the op-amp has the DC gain of 112dB and the unity gain bandwidth of 1.15GHz.
Proceedings of the Sixth International Conference on Computer and Communication Technology 2015
This paper reports a new three levels interconnect signaling system for the On-Chip High Speed Se... more This paper reports a new three levels interconnect signaling system for the On-Chip High Speed SerDes Transceiver used in multi-module System-on-Chip (SoC) communication. This signaling system consists of a three-level encoder, a line driver, interconnect, a line receiver and a three-level detector. It also presents the influences of Process, Voltage and Temperature (PVT) variations on the three levels interconnect signaling system. The proposed signaling system is designed in UMC 180nm CMOS Process Technology and all simulations are done using Cadence Spectre Simulator. Under different process corners, it is observed that the percentage variations on interconnect delay and total average power for three levels interconnect signaling system varies with interconnect line length. Also, with supply voltage variations, the interconnect delay and total average power decreases and increases respectively with increasing supply voltage. Finally, in the case of Temperature variations, it is observed that the interconnect delay and total average power increases and decreases with increase in temperature respectively. This design and results will provide some ideas to the designer about the worst case values and the level of margins to provide at the system design level.
Generalized frequency division multiplexing (GFDM) is non orthogonal multicarrier modulation sche... more Generalized frequency division multiplexing (GFDM) is non orthogonal multicarrier modulation scheme which is suitable for the fifth generation (5G) of wireless network. Pulse shaping filter design in GFDM system have effects on symbol error rate performance due to inter symbol interference (ISI). In this paper Contribute to symbol error rate (SER) performance in GFDM system with additive white Gaussian noise channel (AWGN), zero forcing channel (ZF) rayleigh fading has been analyzed for pulse shaping filter namely raised cosine (RC) and root raised cosine filter (RRC) and also Simulation is done and results are reported in terms of symbol error rate (SER), signal to noise ratio (SNR), different value of roll off factor and different modulation technique. Comparison of simulation results of this method with existing methods is done and improvements in result are obtained as compared to existing.
this paper presents implementation of switch capacitor filter with sample and hold circuit, nonov... more this paper presents implementation of switch capacitor filter with sample and hold circuit, nonoverlapping clock and a gain stage using 180 nm CMOS technology. After implementation, an integration of a Sampler circuit is done with help of Implemented basic blocks with sampling frequency of 2.0 GHz. Finally complete design of band pass filter having a band width of ≤13 Hz is designed which is used for EEG signals application. This band pass filter is a combination of lower cut off frequency 0.7123 Hz and higher cut off frequency of 12.895 Hz which is ideal in detecting EEG Signals (Theta, Alpha, Beta and Delta EEG wave forms). Op-amp used in these circuits having a gain of 47.779 db.
This paper reports design of a ring oscillator using CS-COMS low noise logic family for mixed sig... more This paper reports design of a ring oscillator using CS-COMS low noise logic family for mixed signal SOCs. Design has been implemented using 180nm technology with 1.8V supply voltage using CSCMOS logic. CS-CMOS logic efficiently reduce switching noise while maintaining the speed as compare to the other logics like CSL, CBL etc. After completion of the design authors have simulated the design in Spectre simulator and obtained the best simulation results. Authors have determined the parameters like phase noise, delay.
This paper reports an area-efficient LNA design using an active inductor which can be realised in... more This paper reports an area-efficient LNA design using an active inductor which can be realised in various UHF band receivers. The overall low noise performance of LNA is achieved by cancelling the inductor noise through additional feed forward path. This circuit is implemented using 0.18μm CMOS technology with cadence environment and its operating range is 0.4 to 1GHz. Design is simulated in virtuoso simulator and simulation results are measured. Noise figure is 1.6 to 3.0 dB for the UHF band and power dissipation of overall circuit is 14.03mw at 1.8V supply. KEYWORD: Cadence, MOS based Active Inductor, Feed forward path logic (FFP), Low Noise Amplifier (LNA), Spectre Simulator.
IOP Conference Series: Materials Science and Engineering
Electronics engineers are currently faced with the task of designing linear and broad scale volta... more Electronics engineers are currently faced with the task of designing linear and broad scale voltage regulated oscillator for analogue and a varied signal applications for a shorter design period of time. The Band gap reference source is used here to compensate the noise which affects the Phase lock loop operation from power supplied noise. A cascode current mirror based band gap reference current starved voltage controlled Oscillator (BG-CSVCO) is discussed in detailed as a new design strategy for reducing power supplied noise in Phase lock loop (PLL) applications. A cascode current mirror based band gap reference CS-VCO design is simulated and direct employing in 180nm Cadence CMOS technology. A frequency range of band gap reference CS-VCO is 0.009 GHz up to the 2.07 GHz for adjusting range of 0.5V to 1.8V with the power dissipation is 0.564mW. The VDD as supplied voltage was 1.8volt.
2021 12th International Conference on Computing Communication and Networking Technologies (ICCCNT), 2021
This study describes the design of a novel 13-transistor (13T) Static Random Access Memory (SRAM)... more This study describes the design of a novel 13-transistor (13T) Static Random Access Memory (SRAM) bitcell that employs a single bitline design with isolated transistors used for write and read operation. The bitcell incorporates Schmitt- Trigger based inverters, resulting in a considerable rise in cell's static noise margin. A power gating approach is also used to increase the bitcell's write capabilities, resulting in reduced power consumption during write operations. The proposed bitcell was designed using a 0.18μm technology in Cadence Virtuoso Software. The various performance parameters like stability, Power Consumption, Delay and Leakage power are compared against the conventional 6T SRAM bitcell. Overall, the proposed 13T SRAM bitcell outperforms the conventional 6T SRAM cell in every aspect.
Journal of Telecommunication, Electronic and Computer Engineering, 2019
This paper presents the design of a QVCO (Quadrature voltage controlled oscillator) with high tun... more This paper presents the design of a QVCO (Quadrature voltage controlled oscillator) with high tuning range and low phase noise for Radio Frequency applications. The proposed VCO has been designed to produce quadrature signal by using cross coupled topology. Extra pair of MOSFETS are added to improve the quality factor of the LC tank, which helps to improve the phase noise. The tuning range of VCO ranges from 3.8 GHz to 4.52 GHz, which is nearly 20%. Additionally, the obtained phase noise is -120.31 dBc/Hz at 1MHz offset frequency. The observed power dissipation is 13.21 mW.
In this work, a single-ended 10T static random access memory (SRAM) cell is presented. Proposed c... more In this work, a single-ended 10T static random access memory (SRAM) cell is presented. Proposed cell employs Schmitt-trigger (ST) based inverter to enhance read stability. Single ended feature of the cell saves switching power. Simulation is carried out on 180nm technology using Cadence. Results revealed that our cell provides 1.40x larger read static noise margin (RSNM) compared to conventional 6T cell at 0.7V. During write '0' proposed cell offers 312mV of write static noise margin (WSNM) at 0.7V. During read operation, our cell offers 3.29x lower switching power compared to 6T cell. Standby power dissipation in proposed cellis1.16x of convention 6T cell at 0.7V.
Various improved method for Analog to digital converter (ADC) testing are evaluated. The ADC stat... more Various improved method for Analog to digital converter (ADC) testing are evaluated. The ADC static and dynamic parameters i.e. offset error, gain error, NOB and nonlinearity errors like INL, DNL are obtained from sinewave histogram test. Therefore, the relationships among these parameters are analyzed. With the appropriate approximation in the reference sine wave histogram and the estimation of the ADC parameters, the realization of an ADC output analyzer.
2017 8th International Conference on Computing, Communication and Networking Technologies (ICCCNT), 2017
Biological information processing system, a neuron, is an astonishing piece of design with an ene... more Biological information processing system, a neuron, is an astonishing piece of design with an energy efficiency unmatched to any human-engineered counterpart. This proposed design is an inspired effort to implement a neuron with adaptability. The designed neuron has improved spike-control and thus can be used in advanced neural networks. The proposed controllable-spike Integrate and fire neurons are highly energy efficient. Comparison of different ameliorated silicon neuron designs are described with experimental results. Electronic synthesis of neurons can be utilized for neuromorphic modeling of large-scale neural systems like brain-scanning and sensing technology. The proposed work has been designed using Cadence tool on 180 nm technology node with 1.8 V source.
A single stage source coupled Complementary Metal Oxide Semiconductor Voltage Controlled Oscillat... more A single stage source coupled Complementary Metal Oxide Semiconductor Voltage Controlled Oscillator (CMOS VCO) is designed in this paper. The design is implemented in Cadence environment with high oscillation frequency and low power consumption. This design is a single stage and it has low phase noise because author has reduced noise sources. Oscillation frequency of the designed VCO is ranges from 1.052 GHz to 2.136 GHz. The circuit is simulated using 180nm UMC Technology. Simulation results are reported that the phase noise is -64.96dBc/Hz@1MHz and power consumption is 6.951 mW with 2.136 GHz oscillation frequency and 1.8 V supply voltage. Present results are compared with earlier published work and improvements are observed.
This paper reveals the present status of wireless telemedicine system for m-health application. W... more This paper reveals the present status of wireless telemedicine system for m-health application. Wireless telemedicine network equipped with mobile, computer and telecommunication technologies which provide medical data, information and services from distant locations. Telemedicine opens a world of healthcare delivery by building clinical bridges between patients and available healthcare by integrating Information and Communication Technology, Biomedical Engineering, Medical Science, etc. using minimum costs, effective develop- ment and utilization of ancillary infrastructure and services. We have studied 130 research papers on telemedicine and its aspects, this paper is an extrac- tion which emphasized on wireless technologies like GSM, General Packet Radio Services, EDGE, 3G, 4G, 5G, Cognitive Radio Network, World Wide interoperability of Microwave Access, Wireless Local Area Network, Wireless Body Area Network, Very Small Aperture Terminal, Satellite communication and WPAN (Blueto...
This paper presents a design of low power data channel for application in High Definition Multime... more This paper presents a design of low power data channel for application in High Definition Multimedia Interface (HDMI) Transmitter circuit. The input is 10 bit parallel data and output is serial data at 1.65 Gbps. This circuit uses only a single frequency of serial clock input. All other timing signals are derived within the circuit from the serial clock. This design has dedicated lines to disable and enable all its channels within two pixel-clock periods only. A pair of disable and enable functions performed immediately after power-on of the circuit serves as the reset function. The presented design is immune to data-dependent switching spikes in supply current and pushes them in the range of serial frequency and its multiples. Thus filtering requirements are relaxed. The output stage uses a bias voltage of 2.8 volts for a receiver pull-up voltage of 3.3 volts. The reported data channel is designed using UMC 180 nm CMOS Technology. The design is modifiable for other inter-board seri...
In this work, we present a single-ended Schmitt-trigger (ST) based 12T static random access memor... more In this work, we present a single-ended Schmitt-trigger (ST) based 12T static random access memory (SRAM) cell. The proposed cell employs cross-point data aware write structure, and thus supports bit interleaving architecture to mitigate soft errors. The proposed cell does not suffer from read disturbance as bit line is completely isolated from bit storage node. Simulation is done on 180 nm CMOS technology on Cadence. Read static noise margin (RSNM) of the proposed cell is improved by1.42X as compared to conventional 6T bit cell at Vdd=0.7 V. The proposed cell offers 0.0065X lesser write ‘1’ delay as compared to previously proposed ST based 11T SRAM. Keywords: HSNM, read delay, RSNM, SRAM, write delay, WSNM Cite this Article Mansore SR, Gamad RS, Mishra DK. Schmitt-Trigger Based 12T SRAM Cell with Enhanced Stability . Journal of Semiconductor Devices and Circuits . 2018; 5(1): 5–10p.
International Journal of Advance Research, Ideas and Innovations in Technology, 2018
This paper presents a design of Low power 4 bits Counter at circuit and system level of abstracti... more This paper presents a design of Low power 4 bits Counter at circuit and system level of abstraction using Cadence Virtuoso and Xilinx ISE 14.7 respectively. The laboratory work described includes the CMOS based transistor level design and VHDL based synthesis and implementation of the counter using back end and front end tools respectively. The functionality of the design has been simulated and tested using 0.18µm gdpk CMOS technology with 1.8V supply voltage using cadence virtuoso for back-end designing whereas, Xilinx ISE 14.7 is used for front-end simulation, synthesized using plan¬-ahead and is implemented on ArtixTM-7(family), with device xC7A100TTM. Power calculation has been done at 100 MHz clock frequency for the 1.8V supply voltage.
This paper presents the analysis and design of high speed, high gain fully differential operation... more This paper presents the analysis and design of high speed, high gain fully differential operational amplifier (opamp). Both the main op-amp and the boosting op-amp are fully differential folded-cascode. The main op-amp has a switched capacitor common mode feedback circuit. Two fully differential folded-cascode op amps with continuoustime CMFBs are used as auxiliary op amps to increase the open-loop gain of the main op amp. Common mode feedback (CMFB) is used to stable the designed op-amp against temperature. This design has been implemented in 0.18μm UMC mixed signal CMOS Technology using Cadence. Spectre simulation shows that the op-amp has the DC gain of 112dB and the unity gain bandwidth of 1.15GHz.
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Papers by R. S. Gamad