Bigger designs with hundred of cores are creating an explosion in the volume of scan test data, significantly bumping up the amount of time spent on test. That raises the cost of test, forcing chipmakers to trade off higher costs with reliability. The solution is to raise the level of abstraction for scan tests, using a bus and packetized data that can run at much higher frequencies than is possible with the internal scan chains in each core. Ron Press, senior director of technology enablement at Siemens EDA, talks about what needs to change in the scan test architecture to make all this work, along with the advantages of using different sized patterns for different cores, and how that can improve reliability while reducing costs.<\/p>\n