tag: verification

Separating The Chaff From The Wheat: Focusing On Only The RDC Violations You Care About
By Reetika - 06 Aug, 2026 - Comments: 0

Modern system-on-chips (SoCs) are no longer built around a single clock and a single reset. Today's designs integrate hundreds of IP blocks, multiple power domains, software-controlled reset sequences, and sophisticated power-management techniques. While these advancements have enabled remarkable functionality and performance, they have also introduced new verification challenges—one of the m... » read more

Invest In Junior Engineers
By Brian Bailey - 04 Aug, 2026 - Comments: 0

How many junior engineers can be replaced by AI, and how many AI agents can a senior engineer successfully manage? This seems to be a common theme these days, especially in the software development world where there are lots of freely available examples on which AI can be trained. Whether that can expand into embedded software is still somewhat uncertain. There are numerous reports about new... » read more

Untangling Chip Traffic Jams
By Liz Allan - 23 Jul, 2026 - Comments: 0

Key Takeaways: Defining all possible cases of coherent and non-coherent traffic is non-trivial, and designers need to use a mix of hardware-assisted verification and simulation tools to do so. For NoCs connecting multiple dies, simulation is challenging due to the very large number of interconnects and multiphysics issues involving thermal and crosstalk. Advanced verification approac... » read more

From Future Vision To Running Hardware: Verification At DAC 2026
By Frank Schirrmeister - 23 Jul, 2026 - Comments: 0

At last year's DAC in San Francisco, I sat in "A Look into the Future of Verification," an Engineering Track special session debating where our discipline is headed — multi-language flows, AI co-pilots, portable stimulus, formal methods. The discussion was energizing, and what struck me then stayed with me since: whatever that future looks like, it has to execute somewhere. And increasingly, ... » read more

UALink Under The Hood: Why Full-Stack Verification Wins
By Sandeep Grover - 09 Jul, 2026 - Comments: 0

It is tempting to picture UALink as a clean line between two accelerators: requests enter one side, responses emerge from the other. The abstraction is useful — but it conceals almost everything that makes the protocol interesting, and almost everything that makes it difficult to verify. Verifying UALink means following a transaction the way the silicon does: down through four layers, out ... » read more

A Self-Evolving Agent Framework That Treats Hardware Design as Repository-Level Code Evolution (Nvidia Research)
By Technical Paper Link - 30 Jun, 2026 - Comments: 0

A new technical paper, Agentic Hardware Design as Repository-Level Code Evolution, was published by researchers at Nvidia Research. Abstract "We present HORIZON, a self-evolving agent framework that treats hardware design as repository-level code evolution. A Markdown harness is compiled into a project pack containing domain knowledge, an executable evaluator, an acceptance predicate, and... » read more

Rethinking Chip Verification
By Ann Mutschler - 29 Jun, 2026 - Comments: 0

Key Takeaways: AI and modern tools are easing traditional verification pain, but they're not addressing the underlying bottleneck in complex designs. Work is underway to create a golden, unambiguous spec above RTL, tracing requirements from spec to implementation to verification and checking for gaps, conflicts, and inconsistencies across levels and blocks, often with AI help. Tool c... » read more

Verification Methodologies Struggle To Keep Up With AI
By Brian Bailey - 25 Jun, 2026 - Comments: 0

Key Takeaways:  The rapid development of AI has resulted in new capabilities being provided to verification teams, beyond their ability to rationally insert them into accepted methodologies. There is a lot of uncertainty about who will benefit the most from this technology. Is AI a junior engineer replacement or an enhancer? The biggest benefits will come when AI helps engineers und... » read more

How Far Left Can We Really Shift Verification?
By Frank Schirrmeister - 25 Jun, 2026 - Comments: 0

"Shift left" has been in the engineering lexicon for so long that it risks becoming wallpaper. We nod at it, we put it on slides, and we move on. But the goalposts keep moving. Things that used to live comfortably at the tail end of the design flow — software bring-up, power and performance characterization, thermal analysis — are being dragged earlier and earlier into the schedule, driven ... » read more

How Far Left Can You Shift?
By Ed Sperling - 24 Jun, 2026 - Comments: 0

More steps in the design flow are shifting left, which makes a complicated design process even more complex. This includes early software prototyping, workload mapping, verification, multi-physics integration, verification, IP qualification. Frank Schirrmeister, executive director of strategic programs for System Solutions at Synopsys, talks about the increasing number of steps, the potential t... » read more

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