tag: through-silicon vias

Open-Source Benchmark Suite For 2.5D/3D Heterogeneous Integration Research in Physical Design (UCLA)
By Technical Paper Link - 28 Aug, 2026 - Comments: 0

Researchers from University of California, Los Angeles published a technical paper titled “An Open-Source Benchmark Suite of 3D-IC Testcases.” Abstract Excerpt: The paper presents an “open-source suite of 3D-IC benchmark testcases” and provides “reusable virtual chiplet models covering compute, memory, I/O, analog, and substrate components.” Find the technical paper here. Augu... » read more

Issues Stack Up With More HBM Layers
By Ed Sperling - 27 Aug, 2026 - Comments: 0

Key Takeaways: HBM scaling is running into physical limitations. More bandwidth translates into higher area and capacity costs. AI demand is intensifying the DRAM shortage. DRAM is under stress, and the fallout is affecting the entire chip industry. Pressed by large systems companies to move data in and out of memory faster, the big three DRAM vendors — Micron, Samsung,... » read more

Optimizing The Nano-TSV-to-BPR Connection In Backside Power Networks
By Assawer Soussou - 16 Jul, 2026 - Comments: 0

As technology nodes continue to scale, maintaining power and performance while reducing the footprint has become increasingly challenging. Backside power delivery networks (BSPDNs) address this challenge by moving the power delivery network to the wafer backside. What is backside power delivery (BSPDN)? The problem being solved by BSPDNs is similar to getting people out of a crowded offic... » read more

Powering AI At Scale: Why 3D-ICs Demand A New Approach To Power Integrity
By Muhammad Hassan - 07 May, 2026 - Comments: 0

By Muhammad Hassan and Sudarshan Deo The semiconductor industry is undergoing a fundamental transition. Performance scaling is no longer driven primarily by transistor density, but by advanced packaging—2.5D, 3D-ICs, chiplets, and heterogeneous integration. Fig. 1: 3D-IC and 2.5D structure. These architectures are essential to meeting the extreme performance and bandwidth demands... » read more

TSV Complexity Leads To Manufacturing Bottleneck
By Laura Peters - 22 Apr, 2026 - Comments: 1

Key Takeaways: Through-silicon vias are the biggest enabler of 3D chip stacking and chip-to-PCB connections through silicon interposers. The AI boom is causing HBM and advanced assembly shortages, straining the supply chain. Optimization around etch, fill and reveal help reduce TSV cost. Through-silicon vias (TSVs) provide essential interconnects between DRAM dies inside hig... » read more

An Explosion In Interconnect Complexity
By Bryon Moyer - 22 Jan, 2026 - Comments: 0

For decades, electronics offered two levels of routing structure to manage signals that originate or terminate in an integrated circuit. Recently, that number has risen to five, and while it adds far more flexibility for structuring electronic equipment, it also brings greater complexity and ratchets up the number of design decisions needed to complete a project. This transition has been evo... » read more

Structural Integrity Assessment of IC Packaging Using Scanning Acoustic Microscopy (Arizona State Univ., Fraunhofer IMWS)
By Technical Paper Link - 19 Dec, 2025 - Comments: 0

A new technical paper titled "Recent Progress in Structural Integrity Evaluation of Microelectronic Packaging Using Scanning Acoustic Microscopy (SAM): A Review" was published by researchers at Arizona State University and Fraunhofer Institute for Microstructure of Materials and Systems IMWS. Abstract "Microelectronic packaging is crucial for protecting, powering, and interconnecting semi... » read more

What Is 3D-IC Technology? Fundamentals, Architecture, And Design Concepts
By Reela Samuel - 25 Nov, 2025 - Comments: 0

As process nodes continue to advance into the sub-micron era, the limitations of traditional scaling are becoming increasingly evident. Larger monolithic chips are facing challenges such as higher power density, routing congestion, and reduced yield. Three-dimensional integrated circuits (3D-IC) technology represents a breakthrough approach by stacking multiple dies vertically. This design red... » read more

Monolithic Integration of Air-Clad Optical Through-Silicon Waveguides in Silicon (TH Wildau et al.)
By Technical Paper Link - 08 Oct, 2025 - Comments: 0

A new technical paper titled "Monolithically Integrated Optical Through-Silicon Waveguides for 3D Chip-to-Chip Photonic Interconnects" was published by researchers at the Technical University of Applied Sciences Wildau, TU of Applied Sciences Mittelhessen, TU Ilmenau, Brandenburg University of Technology and Fraunhofer IPMS. Abstract "The scaling limitations of electrical interconnects are ... » read more

On-Die And In-Package Interconnects: eBook
By Bryon Moyer - 28 Jul, 2025 - Comments: 0

We live in the Information Age, but if information cannot get to where it's intended to go, it does no good. And the way information gets from here to there is through interconnects. This report focuses on different interconnect structures, such as lines, vias, buses, and networks-on-chip, and how they’re constructed. As always, we consider the design, test, reliability, and security impli... » read more

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